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Imran Wali
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2020 – today
- 2020
- [c7]Imran Wali, Alfonso Sánchez-Macián
, Alexis Ramos, Juan Antonio Maestro:
Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation. ICECS 2020: 1-4
2010 – 2019
- 2017
- [j2]Imran Wali, Bastien Deveautour, Arnaud Virazel
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33(1): 25-36 (2017) - [c6]Imran Wali, Emmanuel Casseau, Arnaud Tisserand:
An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. DASIP 2017: 1-6 - [c5]Imran Wali, Marcello Traiola
Towards approximation during test of Integrated Circuits. DDECS 2017: 28-33 - 2016
- [j1]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32(2): 147-161 (2016) - [c4]Imran Wali, Bastien Deveautour, Arnaud Virazel
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS 2016: 1-2 - 2015
- [c3]Imran Wali, Arnaud Virazel
An effective hybrid fault-tolerant architecture for pipelined cores. ETS 2015: 1-6 - [c2]Imran Wali, Arnaud Virazel
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS 2015: 89-94 - 2014
- [c1]Imran Wali, Arnaud Virazel
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS 2014: 223-225
Coauthor Index
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