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Yuanqing Cheng
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2020 – today
- 2024
- [j22]Xinmiao Zhang
, Cheng Liu
PDG: A Prefetcher for Dynamic Graph Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1246-1259 (2024) - [j21]Wei W. Xing
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2151-2162 (2024) - [c27]Hang Wu, Ning Xu, Wei W. Xing, Yuanqing Cheng:
BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization. ASPDAC 2024: 183-188 - [c26]Mingyue Wang, Yuanqing Cheng, Yage Lin, Kelin Peng, Shunchuan Yang, Zhou Jin, Wei W. Xing:
MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction. DAC 2024: 264:1-264:6 - 2023
- [c25]Wei W. Xing, Zheng Xing, Rongqi Lu, Zhelong Wang, Ning Xu, Yuanqing Cheng, Weisheng Zhao:
TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning. DAC 2023: 1-6 - [c24]Yanfang Liu
OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits. ICCAD 2023: 1-9 - 2022
- [j20]Yuanqing Cheng
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective. Integr. 85: 97-107 (2022) - [j19]Kangwei Xu
All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits. ACM J. Emerg. Technol. Comput. Syst. 18(4): 71:1-71:20 (2022) - [j18]Rongmei Chen
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 432-439 (2022) - [j17]Rongmei Chen
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 440-448 (2022) - [c23]Kangwei Xu
Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs. ASP-DAC 2022: 479-484 - [c22]Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li:
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. ICCAD 2022: 42:1-42:9 - [c21]Baoli Peng, Vasilis F. Pavlidis, Yi-Chung Chen, Yuanqing Cheng:
Thermal Modeling and Design Exploration for Monolithic 3D ICs. ISQED 2022: 1-6 - 2021
- [j16]Patrick Girard
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE 109(2): 149-169 (2021) - [j15]Jinbo Chen
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1325-1334 (2021) - [i1]Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Yuanqing Cheng, Huawei Li, Xiaowei Li:
Taming Process Variations in CNFET for Efficient Last Level Cache Design. CoRR abs/2108.05023 (2021) - 2020
- [j14]Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. ACM J. Emerg. Technol. Comput. Syst. 16(3): 29:1-29:18 (2020) - [j13]Bi Wu
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 803-815 (2020) - [j12]Bi Wu
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 108-120 (2020) - [c20]Jiacheng Ni, Xiaochen Guo, Yuanqing Cheng:
SIP: Boosting Up Graph Computing by Separating the Irregular Property Data. ACM Great Lakes Symposium on VLSI 2020: 15-20 - [c19]Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng:
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. ACM Great Lakes Symposium on VLSI 2020: 399-404 - [c18]Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard, Yuanqing Cheng:
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. ISQED 2020: 408-414
2010 – 2019
- 2019
- [j11]Bi Wu
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1851-1860 (2019) - 2018
- [j10]Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. J. Comput. Sci. Technol. 33(5): 966-983 (2018) - [j9]Linuo Xue
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 484-495 (2018) - [c17]Chen Liu, Yuanqing Cheng, Ying Wang, Youguang Zhang, Weisheng Zhao:
NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs. ISCAS 2018: 1-5 - [c16]Bi Wu
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. ISVLSI 2018: 333-338 - 2017
- [j8]Lili Song, Ying Wang
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1285-1296 (2017) - [c15]Liu Liu
Building energy-efficient multi-level cell STT-RAM caches with data compression. ASP-DAC 2017: 751-756 - [c14]Bi Wu
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. ICCAD 2017: 474-481 - 2016
- [j7]Jianlei Yang
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 380-393 (2016) - [j6]Bi Wu
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. IEEE Trans. Reliab. 65(4): 1755-1768 (2016) - [j5]Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1613-1625 (2016) - [j4]Aida Todri-Sanial
A Study of 3-D Power Delivery Networks With Multiple Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3218-3231 (2016) - [j3]Yuanqing Cheng
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3310-3322 (2016) - [c13]Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung-Hyuk Kang, Yuan Xie:
Architecture design with STT-RAM: Opportunities and challenges. ASP-DAC 2016: 109-114 - [c12]Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie:
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. ICCAD 2016: 118 - [c11]Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi, Mark M. Tehranipoor:
An efficient all-digital IR-Drop Alarmer for DVFS-based SoC. ISCAS 2016: 221-224 - [c10]Liuyang Zhang, Aida Todri-Sanial
Quantitative evaluation of reliability and performance for STT-MRAM. ISCAS 2016: 1150-1153 - [c9]Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi, Mark M. Tehranipoor:
AES design improvement towards information safety. ISCAS 2016: 1706-1709 - 2015
- [c8]Lun Yang, Yuanqing Cheng, Yuhao Wang, Hao Yu, Weisheng Zhao, Aida Todri-Sanial
A body-biasing of readout circuit for STT-RAM with improved thermal reliability. ISCAS 2015: 1530-1533 - [c7]Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li
A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS 2015: 1534-1537 - [c6]Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. ISVLSI 2015: 461-466 - [c5]Bi Wu
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. NANOARCH 2015: 7-12 - 2014
- [c4]Yuanqing Cheng, Aida Todri-Sanial
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC 2014: 544-549 - [c3]Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li:
HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. ISVLSI 2014: 392-397 - 2013
- [j2]Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li:
TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. J. Comput. Sci. Technol. 28(1): 119-128 (2013) - [j1]Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li:
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 239-249 (2013) - [c2]Yuanqing Cheng, Aida Todri-Sanial
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI 2013: 121-126 - 2011
- [c1]Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu, Xiaowei Li:
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. Asian Test Symposium 2011: 181-186
Coauthor Index
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