research-article

PDS: pseudo-differential sensing scheme for STT-MRAM

Authors:

Youguang Zhang,

Weisheng ZhaoAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 120, Pages 1 - 6

https://doi.org/10.1145/2897937.2898058

Published: 05 June 2016 Publication History

Abstract

STT-MRAM has been considered as one of the most promising nonvolatile memory candidates in the next-generation of computer architecture. However, the read reliability and dynamic write power concerns greatly hinder its practical application. In this paper, we propose a synergistic solution, namely pseudo-differential sensing (PDS), to jointly address these two concerns. Three techniques, including cell cluster, asymmetric sensing amplifier (ASA) and self-error-detection-correction (SEDC), are proposed to implement the PDS concept. Our experimental results show that the PDS scheme with the 3T3MTJ cell cluster can reduce the area (~21.7%) and write power (~25.6%) of the differential sensing (DS) scheme while improve the read reliability (read margin, ~35.6%) of the typical sensing (TS) scheme for a 16 Mbit cache. Furthermore, the PDS scheme with the 1T3MTJ cell cluster can outperform both the TS and DS schemes in terms of area (~40.0%, ~66.1%), read latency (~16.6%, ~32.1%), read power (~16.7%, ~37.1%), write latency (~5.4%, 16.3%) and write power (~18.6%, ~43.4%).

References

[1]

"International Technology Roadmap for Semiconductors". Online http://www.itrs.net/, 2013.

[2]

C. J. Xue et al., "Emerging non-volatile memories: opportunities and challenges", in IEEE/ACM/IFIP Int. Conf. Hardware/Software codesign and system synthesis, pp. 325--334, 2011.

Digital Library

[3]

H.-S. Philip Wong and S. Salahuddin, "Memory leads the way to better computing", Nature Nanotechnol., vol. 10, pp. 191--194, 2015.

[4]

G. W. Burr, et al., "Overview of candidate device technologies for storage-class memory", IBM J. Res. Dev., vol. 52, no. 4.5, pp. 449--464, 2008.

Digital Library

[5]

W. Kang, et al., "Spintronics: Emerging ultra-low power circuits and systems beyond MOS technology", ACM J. Emerg. Technol. Comput. Syst., vol. 12, no. 2, Article 16, 2015.

Digital Library

[6]

A. Jog, et al., Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs, in ACM/EDAC/IEEE DAC, pp. 1187--1192, 2012.

Digital Library

[7]

D. Lee and K. Roy, "Energy-delay optimization of the STT-MRAM write operation under process variations. IEEE Trans. Nanotechnol., vol. 13, no. 4, pp. 714--723, 2014.

[8]

D. Suzuki, et al. "Cost-efficient self-terminated write driver for spin-transfer-torque RAM and logic", IEEE Trans. Magn., vol. 50, no. 11, pp. 3402104, 2014.

[9]

Y. Zhang et al., "Read Performance: The Newest Barrier in Scaled STT-RAM", IEEE Trans. VLSI., vol. 23, no. 6, pp. 1170--1174, 2015.

Digital Library

[10]

W. Kang, et al., "Variation-tolerant and disturbance-free sensing circuit for deep nanometer STT-MRAM". IEEE Trans. Nanotechnol., vol. 13, no. 6, pp. 1088--1092, 2014.

[11]

R. Sbiaa, et al., "Reduction of switching current by spin transfer torque effect in perpendicular anisotropy magneto-resistive devices", J. Appl. Phys., vol. 109, no. 7, pp. 07C707, 2011.

[12]

E. Eken, et al. "A new field-assisted access scheme of STT-RAM with self-reference capability", in ACM/EDAC/IEEE DAC, pp. 1--6, 2014.

Digital Library

[13]

P. Zhou, et al. "Energy reduction for STT-RAM using early write ermination", in IEEE/ACM ICCAD, pp. 264--268, 2009.

Digital Library

[14]

R. Bishnoi, et al., "Avoiding unnecessary write operations in STT-MRAM for low power implementation", in ISQED, pp. 548--553, 2014.

[15]

H. Tanizaki, et al., "A high-density and high-speed 1T-4MTJ MRAM with voltage offset self-reference sensing scheme", in IEEE ASSCC, pp. 303--306, 2006.

[16]

Y. Chen, et al., "A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)," in IEEE DATE, pp. 148--153, 2010.

Digital Library

[17]

H. Noguchi, et al., "Variable nonvolatile memory arrays for adaptive computing systems", in IEEE IEDM., pp. 25.4.1-25.4.4, 2013.

[18]

W. Kang, et al, Reconfigurable codesign of STT-MRAM under process variations in deeply scaled technology. IEEE Trans. Electron Devices, vol. 62, no. 6, pp. 1769--1777, 2015.

[19]

J. C. Slonczewski, "Current-driven excitation of magnetic multilayers," J. Magn. Magn. Mater., vol. 159, nos-. 1-2, pp. L1--L7, 1996.

[20]

Y. Zhang, et al., "Asymmetry of MTJ Switching and Its Implication to the STT-RAM Designs", in IEEE DATE, pp. 1313--1318, 2012.

Digital Library

[21]

J. Kim, et al., "A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM)". IEEE Trans. VLSI. Syst., vol. 20, no. 1, pp. 181--186, 2012.

Digital Library

[22]

W. Kang, et al, High reliability sensing circuit for deep submicron spin transfer torque magnetic random access memory. Electron. Lett., vol. 49, no. 20, pp. 1283--1285, 2013.

[23]

W. S. Zhao, et al., "Failure and reliability analysis of STT-MRAM," Microelectron. Releliability., vol. 52, no. 9, pp. 1848--1852, 2012.

[24]

M. C. Gaidis, et al., "Two-level BEOL processing for rapid iteration in MRAM development", IBM J. Res. Dev., vol. 50, no. 1, pp. 41--54, 2006.

Digital Library

[25]

Y. Zhang, et al., "Compact model of subvolume MTJ and its design application at nanoscale technology nodes", IEEE Trans. Electron Devices, vol. 62, no. 6, pp. 2048--2055, 2015.

[26]

X. Dong et al., "Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory", IEEE Trans. Comput. Aided Des. Integr. Circ. Syst., vol. 31, no. 7, pp. 994--1007, 2012.

Digital Library

Cited By

Na TKang SJung S(2021)STT-MRAM Sensing: A ReviewIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2020.304042568:1(12-18)Online publication date: Jan-2021
https://doi.org/10.1109/TCSII.2020.3040425
Mondal ASrivastava A(2019)Energy-efficient Design of MTJ-based Neural Networks with Stochastic ComputingACM Journal on Emerging Technologies in Computing Systems10.1145/335962216:1(1-27)Online publication date: 15-Oct-2019
https://dl.acm.org/doi/10.1145/3359622
Na TSong BKim JKang SJung S(2018)Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAMIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.271236365:1(163-174)Online publication date: Jan-2018
https://doi.org/10.1109/TCSI.2017.2712363

Index Terms

PDS: pseudo-differential sensing scheme for STT-MRAM
1. Hardware
  1. Emerging technologies
  2. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

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Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Cited By

Na TKang SJung S(2021)STT-MRAM Sensing: A ReviewIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2020.304042568:1(12-18)Online publication date: Jan-2021
https://doi.org/10.1109/TCSII.2020.3040425
Mondal ASrivastava A(2019)Energy-efficient Design of MTJ-based Neural Networks with Stochastic ComputingACM Journal on Emerging Technologies in Computing Systems10.1145/335962216:1(1-27)Online publication date: 15-Oct-2019
https://dl.acm.org/doi/10.1145/3359622
Na TSong BKim JKang SJung S(2018)Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAMIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.271236365:1(163-174)Online publication date: Jan-2018
https://doi.org/10.1109/TCSI.2017.2712363

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