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Paolo Maistri
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2020 – today
- 2024
- [j10]Ihab Alshaer
, Gijs Burghoorn, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri:
Cross-layer analysis of clock glitch fault injection while fetching variable-length instructions. J. Cryptogr. Eng. 14(2): 325-342 (2024) - [c62]Nasr-Eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri:
Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification. DATE 2024: 1-6 - [c61]Sami El Amraoui
Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints. DDECS 2024: 118-123 - [c60]Aghiles Douadi, Elena-Ioana Vatajelu, Paolo Maistri, David Hély, Vincent Beroulle, Giorgio Di Natale:
Modeling Thermal Effects For Biasing PUFs. ETS 2024: 1-4 - [c59]Nasr-Eddine Ouldei Tebina, Aghiles Douadi, Luc Salvo, Vincent Beroulle, Nacer-Eddine Zergainoh, Guillaume Hubert, Elena-Ioana Vatajelu, Giorgio Di Natale, Paolo Maistri:
Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation. HOST 2024: 1-11 - [c58]Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri:
Harmonic Response of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection. LATS 2024: 1-6 - [c57]Roua Boulifa, Giorgio Di Natale, Paolo Maistri:
Internal State Monitoring in RISC-V Microarchitectures for Security Purpose. LATS 2024: 1-5 - 2023
- [c56]Ihab Alshaer
Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault Injection. CARDIS 2023: 3-22 - [c55]Nasr-Eddine Ouldei Tebina
Simulation Methodology for Assessing X-Ray Effects on Digital Circuits. DFT 2023: 1-6 - [c54]Aghiles Douadi, Giorgio Di Natale, Paolo Maistri, Elena-Ioana Vatajelu, Vincent Beroulle:
A Study of High Temperature Effects on Ring Oscillator Based Physical Unclonable Functions. IOLTS 2023: 1-7 - [c53]Maryam Esmaeilian, Aghiles Douadi, Zahra Kazemi, Vincent Beroulle, Amir-Pasha Mirbaha, Mahdi Fazeli, Elena-Ioana Vatajelu, Paolo Maistri, Giorgio Di Natale:
Experimental Evaluation of Delayed-Based Detectors Against Power-off Attack. IOLTS 2023: 1-3 - [c52]Nasr-Eddine Ouldei Tebina
Ray-Spect: Local Parametric Degradation for Secure Designs: An application to X-Ray Fault Injection. IOLTS 2023: 1-7 - 2022
- [j9]Michele Portolan
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions. IEEE Des. Test 39(3): 117-124 (2022) - [c51]Paolo Maistri, Jiayun Po:
A Low-Cost Methodology for EM Fault Emulation on FPGA. DATE 2022: 1185-1188 - [c50]Nasr-Eddine Ouldei Tebina
X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective. DFT 2022: 1-4 - [c49]Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri:
Variable-Length Instruction Set: Feature or Bug? DSD 2022: 464-471 - [c48]Nicolas Bordes, Paolo Maistri:
Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box. DSD 2022: 520-527 - 2021
- [c47]Ihab Alshaer
Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology. DTIS 2021: 1-6 - [c46]Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale:
Security EDA Extension through P1687.1 and 1687 Callbacks. ITC 2021: 344-353 - [c45]Paolo Maistri, Vincent Reynaud, Michele Portolan, Régis Leveugle:
Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. NEWCAS 2021: 1-4 - 2020
- [c44]Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle:
Dynamic Authentication-Based Secure Access to Test Infrastructure. ETS 2020: 1-6 - [c43]Michele Portolan
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS 2020: 1-4 - [c42]G. Surya, Paolo Maistri, Sriram Sankaran:
Local Clock Glitching Fault Injection with Application to the ASCON Cipher. iSES 2020: 271-276
2010 – 2019
- 2019
- [c41]Marc Merandat, Vincent Reynaud, Emanuele Valea
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW 2019: 43-48 - 2018
- [j8]Régis Leveugle
Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption. Inf. 9(5): 114 (2018) - [c40]Jean-Max Dutertre
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC 2018: 1-6 - [c39]Jean-Max Dutertre
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS 2018: 214-219 - 2017
- [c38]Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki:
HLS design of a hardware accelerator for Homomorphic Encryption. DDECS 2017: 178-183 - 2016
- [j7]Simon Pontie
Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance. Microprocess. Microsystems 47: 23-36 (2016) - [j6]Athanasios Papadimitriou
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics. Microprocess. Microsystems 47: 64-73 (2016) - [c37]Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
On the development of a new countermeasure based on a laser attack RTL fault model. DATE 2016: 445-450 - [c36]Simon Pontie, Alban Bourge, Adrien Prost-Boucle
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD 2016: 511-518 - [c35]Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki, Mohsen Machhout
A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption. IDT 2016: 131-136 - [c34]Régis Leveugle, A. Chahed, Paolo Maistri, Athanasios Papadimitriou
On fault injections for early security evaluation vs. laser-based attacks. IVSW 2016: 1-6 - 2015
- [c33]Athanasios Papadimitriou
Validation of RTL laser fault injection model with respect to layout information. HOST 2015: 78-81 - [c32]C. Jayet-Griffon, Marie-Angela Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle:
Polynomial multipliers for fully homomorphic encryption on FPGA. ReConFig 2015: 1-6 - 2014
- [c31]Simon Pontie, Paolo Maistri:
Randomized windows for secure scalar multiplication on elliptic curves. ASAP 2014: 78-79 - [c30]Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks. DATE 2014: 1-4 - [c29]Simon Pontie, Paolo Maistri, Régis Leveugle:
An Elliptic Curve Crypto-Processor Secured by Randomized Windows. DSD 2014: 535-542 - [c28]Diego Alberto, Paolo Maistri, Régis Leveugle:
Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling. DTIS 2014: 1-6 - [c27]Pierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou
On error models for RTL security evaluations. DTIS 2014: 1-6 - [c26]Matteo Bollo, Paolo Maistri:
Composite fields against side channel analysis for the advanced encryption standard. ICECS 2014: 542-545 - [c25]Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou
Laser-induced fault effects in security-dedicated circuits. VLSI-SoC 2014: 1-6 - [c24]Paolo Maistri, Régis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, Bruno Robisson
Electromagnetic analysis and fault injection onto secure circuits. VLSI-SoC 2014: 1-6 - [c23]Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre
Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) 2014: 220-240 - 2013
- [j5]Diego Alberto, Paolo Maistri, Régis Leveugle:
Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems. Inf. Secur. J. A Glob. Perspect. 22(5-6): 237-243 (2013) - [c22]Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle:
An evaluation of an AES implementation protected against EM analysis. ACM Great Lakes Symposium on VLSI 2013: 317-318 - [c21]Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle:
Countermeasures against EM analysis for a secured FPGA-based AES implementation. ReConFig 2013: 1-6 - 2011
- [j4]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 24(2): 247-268 (2011) - [c20]Paolo Maistri, Régis Leveugle:
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. DSD 2011: 266-269 - [c19]Paolo Maistri:
Countermeasures against fault attacks: The good, the bad, and the ugly. IOLTS 2011: 134-137 - 2010
- [c18]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP 2010: 115-122
2000 – 2009
- 2009
- [c17]Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert:
Statistical fault injection: Quantified error and confidence. DATE 2009: 502-506 - [c16]Paolo Maistri, Régis Leveugle:
Towards automated fault pruning with Petri Nets. IOLTS 2009: 41-46 - [c15]Paolo Maistri:
Pruning single event upset faults with petri nets. LATW 2009: 1-6 - 2008
- [j3]Paolo Maistri, Régis Leveugle:
Double-Data-Rate Computation as a Countermeasure against Fault Analysis. IEEE Trans. Computers 57(11): 1528-1539 (2008) - [c14]Paolo Maistri, Cyril Excoffon, Régis Leveugle:
Software BIST capabilities of a symmetric cipher. ICECS 2008: 414-417 - [c13]Paolo Maistri, Cyril Excoffon, Régis Leveugle:
Software Self-Testing of a Symmetric Cipher with Error Detection Capability. IOLTS 2008: 79-84 - 2007
- [j2]Luca Breveglieri, Israel Koren, Paolo Maistri:
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers. IEEE Trans. Computers 56(5): 635-649 (2007) - [c12]Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle:
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. DFT 2007: 499-507 - [c11]Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle:
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. FDTC 2007: 54-61 - 2006
- [b1]Paolo Maistri:
Cryptographic algorithms and architectures and their connections with errors and reliability. Polytechnic University of Milan, Italy, 2006 - [c10]Luca Breveglieri, Israel Koren, Paolo Maistri, M. Ravasio:
Incorporating Error Detection in an RSA Architecture. FDTC 2006: 71-79 - [c9]Luca Breveglieri, Israel Koren, Paolo Maistri:
A Fault Attack Against the FOX Cipher Family. FDTC 2006: 98-105 - [c8]Luca Breveglieri, Paolo Maistri, Israel Koren:
A Note on Error Detection in an RSA Architecture by Means of Residue Codes. IOLTS 2006: 176-177 - 2005
- [c7]Luca Breveglieri, Israel Koren, Paolo Maistri:
Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard. DFT 2005: 72-80 - 2004
- [c6]Luca Breveglieri, Israel Koren, Paolo Maistri:
Detecting Faults in Four Symmetric Key Block Ciphers. ASAP 2004: 258-268 - [c5]Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri:
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost. DFT 2004: 130-138 - 2003
- [j1]Guido Bertoni
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard. IEEE Trans. Computers 52(4): 492-505 (2003) - [c4]Guido Bertoni
Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm. ASAP 2003: 423-432 - [c3]Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri:
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard. DFT 2003: 105- - 2002
- [c2]Guido Bertoni
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard. ASAP 2002: 303- - [c1]Guido Bertoni
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard. DFT 2002: 51-59
Coauthor Index
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last updated on 2024-11-11 21:32 CET by the dblp team
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