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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15
Volume 15, Number 1, December 2009
- Christophe Wolinski, Krzysztof Kuchcinski
, Erwan Raffin
Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel. 1:1-1:36 - Jingqing Mu, Roman L. Lysecky:
Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems. 2:1-2:20 - Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou:
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. 3:1-3:17 - Jaehyun Kim, Chungki Oh, Youngsoo Shin:
Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates. 4:1-4:22 - Rajeev R. Rao, Vivek Joshi, David T. Blaauw, Dennis Sylvester:
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic. 5:1-5:27 - Li-Pin Chang, Chun-Da Du:
Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollers. 6:1-6:36 - Irith Pomeranz, Sudhakar M. Reddy:
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. 7:1-7:22 - Bert Geelen, Vissarion Ferentinos, Francky Catthoor, Gauthier Lafruit, Diederik Verkest, Rudy Lauwereins, Thanos Stouraitis
Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts. 8:1-8:6 - Kurt Keutzer, Peng Li, Li Shang, Hai Zhou:
ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming. 9:1-9:2
Volume 15, Number 2, February 2010
- Gunar Schirner
Fast and accurate processor models for efficient MPSoC design. 10:1-10:26 - Somnath Paul, Hamid Mahmoodi
Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. 19:1-19:34 - Seongnam Kwon, Soonhoi Ha:
Serialized parallel code generation framework for MPSoC. 11:1-11:27 - Gianpiero Cabodi, Luciano Lavagno, Marco Murciano, Alex Kondratyev, Yosinori Watanabe:
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques. 12:1-12:34 - Mingxuan Yuan, Zonghua Gu
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs. 13:1-13:41 - Peter Jamieson, Tobias Becker
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. 14:1-14:24 - Dipankar Das, P. P. Chakrabarti, Rajeev Kumar:
Thermal analysis of multiprocessor SoC applications by simulation and verification. 15:1-15:52 - Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala:
Parameterized architecture-level dynamic thermal models for multicore microprocessors. 16:1-16:22 - Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara:
Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. 17:1-17:17 - Pedro Reviriego, Juan Antonio Maestro
Reliability analysis of memories protected with BICS and a per-word parity bit. 18:1-18:15 - Naehyuck Chang, Jörg Henkel:
Call for papers ACM transactions on design automation of electronic systems (TODAES) special section on low-power electronics and design. 20:1-20:2
Volume 15, Number 3, May 2010
- Nicolas Blanc, Daniel Kroening
Race analysis for systemc using model checking. 21:1-21:32 - Waseem Ahmed, Doug Myers:
Concept-based partitioning for large multidomain multifunctional embedded systems. 22:1-22:41 - Rajkumar K. Raval, Carlos Fernández, Chris J. Bleakley
Low-power TinyOS tuned processor platform for wireless sensor network motes. 23:1-23:17 - Xuan Guan, Yunsi Fei
Register file partitioning and recompilation for register file power reduction. 24:1-24:30 - Yufu Zhang, Ankur Srivastava
On-chip sensor-driven efficient thermal profile estimation algorithms. 25:1-25:27 - Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko:
Logic synthesis and circuit customization using extensive external don't-cares. 26:1-26:24 - Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Effective congestion reduction for IC package substrate routing. 27:1-27:21
Volume 15, Number 4, September 2010
- Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai:
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. 28:1-28:37 - Cheng-Juei Yu, Yi-Hsin Wu, Sheng-De Wang:
An in-place search algorithm for the resource constrained scheduling problem during high-level synthesis. 29:1-29:13 - Kyoungwoo Lee, Aviral Shrivastava
Partitioning techniques for partially protected caches in resource-constrained embedded systems. 30:1-30:30 - Talal Bonny
Huffman-based code compression techniques for embedded processors. 31:1-31:37 - Zhifang Li, Wenjian Luo, Lihua Yue, Xufa Wang:
On the completeness of the polymorphic gate set. 32:1-32:25 - Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng:
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. 33:1-33:22
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