research-article

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain

Authors:

Peter Jamieson,

Peter Y. K. Cheung,

Teemu PitkänenAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15, Issue 2

Article No.: 14, Pages 1 - 24

https://doi.org/10.1145/1698759.1698764

Published: 02 March 2010 Publication History

Abstract

We present the GroundHog 2009 benchmarking suite that evaluates the power consumption of reconfigurable technology for applications targeting the mobile computing domain. This benchmark suite includes seven designs; one design targets fine-grained FPGA fabrics allowing for quick state-of-the-art evaluation, and six designs are specified at a high level allowing them to target a range of existing and future reconfigurable technologies. Each of the six designs can be stimulated with the help of synthetically generated input stimuli created by an open-source tool included in the downloadable suite. Another tool is included to help verify the correctness of each implemented design. To demonstrate the potential of this benchmark suite, we evaluate the power consumption of two modern industrial FPGAs targeting the mobile domain. Also, we show how an academic FPGA framework, VPR 5.0, that has been updated for power estimates can be used to estimates the power consumption of different FPGA architectures and an open-source CAD flow mapping to these architectures.

References

[1]

Actel. 2008. Igloo Handbook. Actel.

[2]

Altera. 2006. Stratix III Device Handbook. Altera.

[3]

Altera. 2007. Cyclone II Device Handbook. Altera.

[4]

Anderson, J. and Najm, F. 2004. Power estimation techniques for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12, 10, 1015--1027.

Digital Library

[5]

Becker, T., Jamieson, P., Luk, W., Cheung, P., and Rissa, T. 2008. Towards benchmarking energy efficiency of reconfigurable architectures. In Proceedings of the International Conference on Field-Programmable Logic and Applications. 691--694.

[6]

Becker, T., Jamieson, P., Luk, W., Cheung, P., and Rissa, T. 2009. Power characterisation for the fabric in fine-grain reconfigurable architectures. In Proceedings of the Southern Programmabla Logic Conference.

[7]

Betz, V. and Rose, J. 1996. Directional bias and non-uniformity in FPGA global routing architectures. In Proceedings of the 14th IEEE/ACM International Conference on CAD. 652--659.

Digital Library

[8]

Betz, V., Rose, J., and Marquardt, A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic.

Digital Library

[9]

Burleson, W., Tessier, R., Goeckel, D., Swaminathan, S., Jain, P., Euh, J., Venkatraman, S., and Thyagarajan, V. 2001. Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing.

Digital Library

[10]

Gayasen, A., Lee, K., Vijaykrishnan, N., Kandemir, M., Irwin, M., and Tuan, T. 2004. A dual-Vdd low power FPGA architecture. In Proceedings of the International Conference on Field Programmable Logic and Application. 145--157.

[11]

Gustafson, J., Rover, D., Elbert, S., and Carter, M. 1991. The design of a scalable, fixed-time computer benchmark. J. Parallel Distrib. Comput. 12, 4, 388--401.

Digital Library

[12]

Havinga, P., Smit, L., Smit, G., Bos, M., and Heysters, P. 2001. Energy management for dynamically reconfigurable heterogeneous mobile systems. In Proceedings of the 15th International Parallel and Distributed Processing Symposium (IPDPS). 840--852.

Digital Library

[13]

Jamieson, P., Becker, T., Luk, W., Cheung, P., and Rissa, T. 2009. Benchmarking reconfigurable architectures in the mobile domain. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines.

Digital Library

[14]

Jamieson, P. and Rose, J. 2005. A Verilog RTL synthesis tool for heterogeneous FPGAs. In Proceedings of the International Conference on Field-Programmable Logic and Applications. 305--310.

[15]

Kuon, I. and Rose, J. 2008. Automated transistor sizing for FPGA architecture exploration. In Proceedings of the IEEE-ACM Design Automation Conference (DAC'08). 792--795.

Digital Library

[16]

Lamoureux, J. 2007. On the interaction between power-aware computer-aided design algorithms for field-programmable gate arrays. Ph.D. thesis, University of British Columbia.

[17]

Lemieux, G. and Lewis, D. 2001. Using sparse crossbars within LUT clusters. In Proceedings of the ACM/SIGDA International Symposium on FPGAs. 59--68.

Digital Library

[18]

Lemieux, G. and Lewis, D. 2004. Directional and single-driver wires in FPGA interconnect. In Proceedings of the IEEE International Conference on Field-Programmable Technology. 41--48.

[19]

Lewis, D., Ahmed, E., Baeckler, G., Betz, V., Bourgeault, M., Cashman, D., Galloway, D., Hutton, M., Lane, C., Lee, A., Leventis, P., Marquardt, S., McClintock, C., Padalia, K., Pedersen, B., Powell, G., Ratchev, B., Reddy, S., Schleicher, J., Stevens, K., Yuan, R., Cliff, R., and Rose, J. 2005. The Stratix II logic and routing architecture. In Proceedings of the ACM/SIGDA International Symposium on FPGAs. 14--20.

Digital Library

[20]

Liang, J., Tessier, R., and Goeckel, D. 2004. A dynamically-reconfigurable, power-efficient turbo decoder. In Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04). 91--100.

Digital Library

[21]

Luu, J., Kuon, I., Jamieson, P., Campbell, T., Ye, A., Fang, W. M., and Rose, J. 2009. VPR 5.0: FPGA CAD and architecture xploration tools with single-driver routing, heterogeneity and process scaling. In Proceedings of the ACM/SIGDA International Symposium on FPGAs.

Digital Library

[22]

Marquardt, A., Betz, V., and Rose, J. 1999. Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density. In Proceedings of the ACM/SIGDA International Symposium on FPGAs. 37--46.

Digital Library

[23]

Mishchenko, A., Chatterjee, S., and Brayton, R. K. 2007. Improvements to technology mapping for LUT-based FPGAs. IEEE Trans. CAD 26, 2, 240--253.

Digital Library

[24]

National Instruments. 2008. NI PXI-4130 - 20V 2A Source Measure Unit. National Instruments.

[25]

Noguera, J. and Kennedy, I. 2007. Power reduction in network equipment through adaptive partial reconfiguration. In Proceedings of the International Conference on Field Programmable Logic and Application. 240--245.

[26]

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., and Trester, G. 2003. The case for reconfigurable hardware in wearable computing. Personal Ubiq. Comput. 7, 5, 299--308.

Digital Library

[27]

Poon, K., Yan, A., and Wilton, S. 2002. A flexible power model for FPGAs. In Proceedings of the Field-Programmable Logic and Applications. 312--321.

Digital Library

[28]

Shang, L., Kaviani, A. S., and Bathala, K. 2002. Dynamic power consumption in Virtex-II FPGA family. In Proceedings of the ACM/SIGDA 10th International Symposium on Field-Programmable Gate Arrays (FPGA'02). 157--164.

Digital Library

[29]

SiliconBlue 2008. iCE DiCE: iCE65L04 Ultra Low-Power FPGA Known Good Die. SiliconBlue.

[30]

Singh, A. and Marek-Sadowska, M. 2002. Efficient circuit clustering for area and power reduction in FPGAs. In Proceedings of the ACM/SIGDA International Symposium on FPGAs. 59--66.

Digital Library

[31]

Tinmaung, K. O., Howland, D., and Tessier, R. 2007. Power-Aware FPGA logic synthesis using binary decision diagrams. In Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays (FPGA'07). 148--155.

Digital Library

[32]

Tuan, I., Kao, S., Rahman, A., Das, S., and Trimberger, S. 2006. A 90nm low-power FPGA for battery-powered applications In Proceedings of the International Symposium on Field Programmable Gate Arrays. 3-11.

Digital Library

[33]

Xilinx. 2003. Virtex-II Pro Platform FPGAs: Functional Description. Xilinx.

[34]

Xilinx. 2006. Virtex-5 Family Overview. Xilinx.

[35]

Yang, S. 1991. Logic synthesis and optimization benchmarks, version 3.0. Tech. rep. Microelectronics Centre of North Carolina. Research Triangle Park, NC.

Cited By

Bauer LNassar HKhan NBecker JHenkel J(2024)Machine-Learning-Based Side-Channel Attack Detection for FPGA SoCsIEEE Transactions on Circuits and Systems for Artificial Intelligence10.1109/TCASAI.2024.34831181:2(178-190)Online publication date: Dec-2024
https://doi.org/10.1109/TCASAI.2024.3483118
Nassar HKrautter JBauer LGnad DTahoori MHenkel J(2024)Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs MetadataIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344376943:11(3443-3454)Online publication date: 1-Nov-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3443769
Alrahis LNassar HKrautter JGnad DBauer LHenkel JTahoori M(2024)MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HOST55342.2024.10545411(383-393)Online publication date: 6-May-2024
https://doi.org/10.1109/HOST55342.2024.10545411
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Index Terms

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
1. Hardware
  1. Robustness
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 15, Issue 2

February 2010

294 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1698759

Issue’s Table of Contents

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 02 March 2010

Accepted: 01 December 2009

Revised: 01 October 2009

Received: 01 June 2009

Published in TODAES Volume 15, Issue 2

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Cited By

Bauer LNassar HKhan NBecker JHenkel J(2024)Machine-Learning-Based Side-Channel Attack Detection for FPGA SoCsIEEE Transactions on Circuits and Systems for Artificial Intelligence10.1109/TCASAI.2024.34831181:2(178-190)Online publication date: Dec-2024
https://doi.org/10.1109/TCASAI.2024.3483118
Nassar HKrautter JBauer LGnad DTahoori MHenkel J(2024)Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs MetadataIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344376943:11(3443-3454)Online publication date: 1-Nov-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3443769
Alrahis LNassar HKrautter JGnad DBauer LHenkel JTahoori M(2024)MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HOST55342.2024.10545411(383-393)Online publication date: 6-May-2024
https://doi.org/10.1109/HOST55342.2024.10545411
Arora ABoutros ADamghani SMathur KMohanty VAnand TElgammal MKent KBetz VJohn L(2023)Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD ResearchIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.327258242:11(3895-3909)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3272582
Jamieson PBlank DGhanem JMcGrew TCorti G(2022)A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition SystemInternational Journal of Reconfigurable Computing10.1155/2022/88274172022Online publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1155/2022/8827417
Arora ABoutros ARauch DRajen ABorda ADamghani SMehta SKate SPatel PKent KBetz VJohn L(2021)Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research2021 31st International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL53798.2021.00068(355-362)Online publication date: Aug-2021
https://doi.org/10.1109/FPL53798.2021.00068
Rafii ASun WChow P(2021)Pharos: a Multi-FPGA Performance Monitor2021 31st International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL53798.2021.00048(257-262)Online publication date: Aug-2021
https://doi.org/10.1109/FPL53798.2021.00048
Jamieson PSanaullah AHerbordt M(2018)Benchmarking Heterogeneous HPC Systems Including Reconfigurable Fabrics: Community Aspirations for Ideal Comparisons2018 IEEE High Performance extreme Computing Conference (HPEC)10.1109/HPEC.2018.8547635(1-6)Online publication date: Sep-2018
https://doi.org/10.1109/HPEC.2018.8547635
Chau TLuk WCheung P(2012)RobertsACM SIGARCH Computer Architecture News10.1145/2460216.246021940:5(10-15)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2460216.2460219
Nakutis Z(2012)A consumption current measurement approach for FPGA based embedded systems2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings10.1109/I2MTC.2012.6229202(328-333)Online publication date: May-2012
https://doi.org/10.1109/I2MTC.2012.6229202
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