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Effective congestion reduction for IC package substrate routing

Published: 10 June 2010 Publication History

Abstract

Off-chip substrate routing for high-density packages is challenging due to requirements such as high density, lack of vertical detour, non-Manhattan routing, and primarily planar routing. The existing substrate routing algorithms often result in a large number of unrouted nets that have to be routed manually. This article develops an effective yet efficient diffusion-driven method D-Router to reduce congestion. Starting with an initial routing, we develop an effective diffusion-based congestion reduction. We iteratively find a congested window and spread out connections to reduce congestion inside the window by a simulated diffusion process based on the duality between congestion and concentration. The window is released after the congestion is eliminated. Compared with the state-of-the-art substrate routing method that leads to 480 nets unrouted for ten industrial designs with a total of 6415 nets, the D-Router reduces the amount of unrouted nets to 104, a reduction to the 4.6 multiple. In addition, the D-Router obtains a similar reduction on unrouted nets but runs up to 94 times faster when compared with a negotiation-based substrate routing.

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  • (2023)Deep Learning based Refinement for Package Substrate Routing2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)10.1109/ECTC51909.2023.00320(1871-1874)Online publication date: May-2023

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      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 15, Issue 3
      May 2010
      192 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/1754405
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 10 June 2010
      Accepted: 01 February 2010
      Revised: 01 November 2009
      Received: 01 May 2008
      Published in TODAES Volume 15, Issue 3

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      Author Tags

      1. IC package
      2. congestion reduction
      3. routability
      4. routing
      5. substrate

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      • (2023)Deep Learning based Refinement for Package Substrate Routing2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)10.1109/ECTC51909.2023.00320(1871-1874)Online publication date: May-2023

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