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VLSI-SoC 2013: Istanbul, Turkey
- Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag:
21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013. IEEE 2013, ISBN 978-1-4799-0522-5 - Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören:
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. - Sani R. Nassif, Yale N. Patt, Magdy S. Abadir:
Keynote 1 - VLSI 2.0: R&D Post Moore. - Ali Fazli Yeknami, Atila Alvandpour:
A 0.7-V 400-nW fourth-order active-passive ΔΣ modulator with one active stage. 1-6 - Mostafa Rahimi Azghadi, Said F. Al-Sarawi
, Nicolangelo Iannella
A new compact analog VLSI model for Spike Timing Dependent Plasticity. 7-12 - Hussain A. Alzaher, Noman Tasadduq:
Fully electronically programmable complex filter for multistandard applications. 13-18 - Ricardo Povoa
Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners. 19-22 - Hussein Adel, Marie-Minerve Louërat, Marc Sabut:
Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs. 23-26 - Michael Schaffner, Pascal Hager, Lukas Cavigelli
A real-time 720p feature extraction core based on Semantic Kernels Binarized. 27-32 - Kostas Tsoumanis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi:
On the design of modulo 2n±1 residue generators. 33-38 - Stephen Richardson, Ofer Shacham, Dejan Markovic, Mark Horowitz:
An area-efficient minimum-time FFT schedule using single-ported memory. 39-44 - Sungho Kim, Urs Frey
An inverter-based neural amplifier for neural spike detection. 45-49 - Kemal Ozanoglu, Selçuk Talay:
Effects of the positive feedback loop in self biased bandgap reference circuits. 50-51 - Sharareh Zamanzadeh, Ali Jahanian
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. 52-53 - Elmira Karimi, Mohammad Hashem Haghbayan, Adele Maleki, Mahmoud Tabandeh:
Graph based fault model definition for bus testing. 54-55 - Alp Arslan Bayrakci
On the accuracy of Monte Carlo yield estimators. 56-57 - Somayeh Timarchi, Maryam Saremi, Mahmood Fazlali
High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. 58-59 - Manel Elloumi, Mohamed Krid
Implementation of Neuro-Fuzzy System based image edge detection. 60-61 - Mohsen Hassanpourghadi, Mohammad Sharifkhani:
Step response analysis of third order OpAmps With slew-rate. 62-63 - Farshad Eshghabadi, Fatemeh Banitorfian, Norlaili Mohd Noh, Mohd Tafir Mustaffa, Asrulnizam Bin Abd Manaf
Multi-band tunable low noise amplifiers operating at 850MHz and 1900MHz standards. 64-65 - Dogan Ulus
Analog layer extensions for analog/mixed-signal assertion languages. 66-71 - Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
SyntHorus-2: Automatic prototyping from PSL. 72-77 - Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
A debugging method for gate level circuit designs by introducing programmability. 78-83 - Davide Sabena, Matteo Sonza Reorda
On the development of diagnostic test programs for VLIW processors. 84-89 - Mohand Bentobache
New techniques for selecting test frequencies for linear analog circuits. 90-95 - Dong Xiang, Gang Liu, Krishnendu Chakrabarty
Thermal-aware test scheduling for NOC-based 3D integrated circuits. 96-101 - Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Power-aware SoC test optimization through dynamic voltage and frequency scaling. 102-107 - Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo:
FOF: Functionally Observable Fault and its ATPG techniques. 108-111 - Anna Bernasconi
Minimization of EP-SOPs via Boolean relations. 112-117 - Chien-Min Lee, Chi-Kang Chen, Ren-Song Tsay:
A basic-block power annotation approach for fast and accurate embedded software power estimation. 118-123 - Amir Hossein Ashouri
A framework for Compiler Level statistical analysis over customized VLIW architecture. 124-129 - Keni Qiu, Mengying Zhao, Chenchen Fu, Chun Jason Xue
Data re-allocation enabled cache locking for embedded systems. 130-133 - Leandro Nunes, Tiago Reimann, Ricardo Reis
GR-PA: A cost pre-allocation model for global routing. 134-137 - Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak:
Gate sizing in the presence of gate switching activity and input vector control. 138-143 - Yuan Ren, Tobias G. Noll:
An accurate power estimation model for low-power hierarchical-architecture SRAMs. 144-149 - Hailong Jiao, Volkan Kursun
Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits. 150-155 - Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. 156-161 - Joachim Knoch
Gate-controlled doping in carbon-based FETs. 162-167 - Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. 168-173 - Weisheng Zhao, Jacques-Olivier Klein
Spin-electronics based logic fabrics. 174-179 - Sébastien Le Beux, Zhen Li, Christelle Monat
Reconfigurable photonic switching: Towards all-optical FPGAs. 180-185 - Sotiris Thomas, Kyprianos Papadimitriou
Architecture and implementation of real-time 3D stereo vision on a Xilinx FPGA. 186-191 - Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Three-dimensional stacking FPGA architecture using face-to-face integration. 192-197 - Kaushik Triyambaka Mysur, Mihai Pricopi, Thomas Marconi, Tulika Mitra
Implementation of core coalition on FPGAs. 198-203 - Aydin Aysu, Murat Sayinta, Cevahir Cigla:
Low cost FPGA design and implementation of a stereo matching system for 3D-TV applications. 204-209 - Jie Meng, Tiansheng Zhang
Dynamic cache pooling for improving energy efficiency in 3D stacked multicore processors. 210-215 - Antonio Artés
Energy impact in the design space exploration of loop buffer schemes in embedded systems. 216-221 - Mehmet Burak Aykenar, Muhammet Ozgur, Osman Seckin Simsek, Oguz Ergin
Adapting the columns of storage components for lower static energy dissipation. 222-227 - Jongbum Park, Jongpil Jung, Kang Yi, Chong-Min Kyung:
Static energy minimization of 3D stacked L2 cache with selective cache compression. 228-233 - Sk Subidh Ali
New scan-based attack using only the test mode. 234-239 - Isil Öz, Haluk Rahmi Topcuoglu
Examining Thread Vulnerability analysis using fault-injection. 240-245 - Nicoleta Cucu Laurenciu, Yao Wang, Sorin Dan Cotofana
A direct measurement scheme of amalgamated aging effects with novel on-chip sensor. 246-251 - Wael Adi, Shaza Zeitouni, X. Huang, Marc Fyrbiak, Christian Kison, Marc Jeske, Z. Alnahhas:
IP-core protection for a non-volatile Self-reconfiguring SoC environment. 252-255 - Arezoo Kamran
Online periodic test mechanism for homogeneous many-core processors. 256-259 - H. Fatih Ugurdag, Fatih Temizkan, Sezer Gören
Generating fast logic circuits for m-select n-port Round Robin Arbitration. 260-265 - Seogoo Lee, Andreas Gerstlauer:
Fine grain word length optimization for dynamic precision scaling in DSP systems. 266-271 - Abdulkadir Akin, Ipek Baz, Luis Manuel Gaemperle, Alexandre Schmid
Compressed look-up-table based real-time rectification hardware. 272-277 - Qiuling Zhu, Navjot Garg, Yun-Ta Tsai, Kari Pulli:
An energy efficient time-sharing pyramid pipeline for multi-resolution computer vision. 278-281 - Yusuf Adibelli, Ilker Hamzaoglu:
A high performance and low energy hardware for intra prediction with Template Matching. 282-285 - Yankin Tanurhan, Pieter van der Wolf:
Processors as SoC building blocks. 286-287 - Baris Özgül, Jan Langer
Software-programmable digital pre-distortion on the Zynq SoC. 288-289 - Antonio Filgueras
Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq. 290-291 - Francisco-Jose Sanchis-Cases, Antonio Martínez-Álvarez
Automatic mapping of OpenCV based systems on new heterogeneous SoCs. 292-293 - Jonathan van de Belt, Paul D. Sutton
Accelerating software radio: Iris on the Zynq SoC. 294-295 - Melvin Eze, Ozcan Ozturk, Vijaykrishnan Narayanan:
Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. 296-301 - Eric Guthmuller
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. 302-307 - Debora Matos, Cezar Reinbrecht, Tiago Motta, Altamiro Amadeu Susin:
A power-efficient hierarchical network-on-chip topology for stacked 3D ICs. 308-313 - Bharath Sudev, Leandro Soares Indrusiak
PFT - A low overhead predictability enhancement technique for non-preemptive NoCs. 314-317 - Yuhui Bai, Syed Zahid Ahmed, Imen Mhedhbi, Khalil Hachicha, Cedric Champion, Patrick Garda, Bertrand Granado:
FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding. 318-321 - Vazgen Melikyan, Abraham Balabanyan, Armen Durgaryan, Harutyun Stepanyan, Karen Sloyan, Hovik Musayelyan, Gayane Markosyan:
PVT variation detection and compensation methods for high-speed systems. 322-327 - Levent Aksoy
Towards the least complex time-multiplexed constant multiplication. 328-331 - Giray Kömürcü, Ali Emre Pusane, Günhan Dündar
Analysis of Ring Oscillator structures to develop a design methodology for RO-PUF circuits. 332-335 - Ioannis Vourkas
Improved read voltage margins with alternative topologies for memristor-based crossbar memories. 336-339 - Soumya Banerjee, Kai Da Zhao, Wenjing Rao, Milos Zefran
Decentralized self-balancing systems. 340-343 - Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas:
A framework to accelerate sequential programs on homogeneous multicores. 344-347 - Yajuan He, Bo Chen, Qiang Li:
Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC. 348-351 - Majid Zamani, Clemens Eder, Andreas Demosthenous
Analog-to-digital converters power dissipation limits of CBSC-based pipelined. 352-357 - Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Variation-aware and adaptive-latency accesses for reliable low voltage caches. 358-363 - Assia Hamouda, Rüdiger Arnold, Otto Manck, Nour-Eddine Bouguechal:
7.72 ppm/°C, ultralow power, high PSRR CMOS bandgap reference voltage. 364-367 - Amr M. S. Tosson, Siddharth Garg, Mohab H. Anis:
Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. 368-373 - Vikas S. Vij, Kenneth S. Stevens:
Automatic addition of reset in asynchronous sequential control circuits. 374-379 - Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson
A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. 380-385 - Chien-Hung Kuo, Cin-De Jhang:
A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters. 386-389
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