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H. Fatih Ugurdag
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- affiliation: Ozyegin University, Istanbul, Turkey
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2020 – today
- 2024
- [j14]Gokce Guven, Hasan F. Ates
, H. Fatih Ugurdag
X2V: 3D Organ Volume Reconstruction From a Planar X-Ray Image With Neural Implicit Methods. IEEE Access 12: 50898-50910 (2024) - 2023
- [j13]Mustafa Ghanim
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture. Integr. 93: 102069 (2023) - [c35]H. Umut Suluhan
PyTorch and CEDR: Enabling Deployment of Machine Learning Models on Heterogeneous Computing Systems. AICCSA 2023: 1-8 - [i5]Ahmad Houraniah, H. Fatih Ugurdag, Cengiz Emre Dedeagac:
2CIM: Area-Efficient 2-Cycle Integer Multipliers. CoRR abs/2301.13332 (2023) - [i4]Ahmad Houraniah, H. Fatih Ugurdag, Furkan Aydin:
JugglePAC: A Pipelined Accumulation Circuit. CoRR abs/2310.01336 (2023) - 2022
- [j12]Hakki Motorcu
HM-Net: A Regression Network for Object Center Detection and Tracking on Wide Area Motion Imagery. IEEE Access 10: 1346-1359 (2022) - [c34]Eren Dogan, H. Fatih Ugurdag, Hasan Unlu:
Using Deep Compression on PyTorch Models for Autonomous Systems. SIU 2022: 1-4 - 2021
- [j11]Pakize Ergül
HC-FFT: highly configurable and efficient FFT implementation on FPGA. Turkish J. Electr. Eng. Comput. Sci. 29(7): 3150-3164 (2021) - [i3]Eren Dogan, H. Fatih Ugurdag, Hasan Unlu:
Deep Compression for PyTorch Model Deployment on Microcontrollers. CoRR abs/2103.15972 (2021) - [i2]Bilgiday Yuce, H. Fatih Ugurdag, Iskender Agi, Gokhan Guner, Vahap Baris Esen, Seyrani Korkmaz, I. Faik Baskaya, Günhan Dündar:
ACTreS: Analog Clock Tree Synthesis. CoRR abs/2108.12897 (2021) - [i1]Hakki Motorcu, Hasan F. Ates, H. Fatih Ugurdag, Bahadir K. Güntürk:
HM-Net: A Regression Network for Object Center Detection and Tracking on Wide Area Motion Imagery. CoRR abs/2110.09881 (2021) - 2020
- [c33]N. Fajar R. Annafianto, M. V. Jabir
FPGA Implementation of a Low Latency and High SFDR Direct Digital Synthesizer for Resource-Efficient Quantum-Enhanced Communication. EWDTS 2020: 1-8 - [c32]Burak Tufekci
Efficient FPGA Implementation of Field Oriented Control for 3-Phase Machine Drives. EWDTS 2020: 1-5 - [c31]Aydin Emre Güzel, Dilara Hisar, Luc Claesen, H. Fatih Ugurdag:
Fast Incremental Least Square Pose Estimation for Hardware Implementation with Rolling Shutter Camera. SIU 2020: 1-4
2010 – 2019
- 2019
- [j10]Vecdi Emre Levent
Tools and Techniques for Implementation of Real-time Video Processing Algorithms. J. Signal Process. Syst. 91(1): 93-113 (2019) - [c30]Abdullah Varici, Gurol Saglam, Seckin Ipek, Abdullah Yildiz, Sezer Gören, Aydin Aysu, Deniz Iskender, T. Baris Aktemur, H. Fatih Ugurdag:
Fast and Efficient Implementation of Lightweight Crypto Algorithm PRESENT on FPGA through Processor Instruction Set Extension. EWDTS 2019: 1-5 - [c29]Y. Serhan Gener
Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions. VLSI-SoC 2019: 52-57 - [c28]Y. Serhan Gener
Semi- and Fully-Random Access LUTs for Smooth Functions. VLSI-SoC (Selected Papers) 2019: 279-306 - [e3]Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro, Ricardo Reis:
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 500, Springer 2019, ISBN 978-3-030-15662-6 [contents] - 2018
- [j9]Ibrahim Abe M. Elfadel
25th IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2017). IEEE Des. Test 35(1): 97-98 (2018) - [c27]Furkan Aydin
Rapid Design of Real-Time Image Fusion on FPGA using HLS and Other Techniques. AICCSA 2018: 1-6 - 2017
- [j8]Ahmet Kakacak, Aydin Emre Guzel, Ozan Cihangir, Sezer Gören
Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression. Integr. 57: 147-157 (2017) - [j7]H. Fatih Ugurdag
Hardware Division by Small Integer Constants. IEEE Trans. Computers 66(12): 2097-2110 (2017) - [j6]Okan Palaz, H. Fatih Ugurdag, Ozgur Ozkurt, Bugra Kertmen, Faruk Donmez:
RImCom: Raster-order Image Compressor for Embedded Video Applications. J. Signal Process. Syst. 88(2): 149-165 (2017) - [c26]Umut Ulutas
FPGA Implementation of a Dense Optical Flow Algorithm Using Altera OpenCL SDK. ICT Innovations 2017: 89-101 - 2016
- [c25]H. Fatih Ugurdag, Anil Bayram, Vecdi Emre Levent
Efficient Combinational Circuits for Division by Small Integer Constants. ARITH 2016: 1-7 - [c24]Aydin Emre Guzel, Vecdi Emre Levent
Using high-level synthesis for rapid design of video processing pipes. EWDTS 2016: 1-4 - [c23]Mustafa Tosun, M. Akif Ozkan
Fast one- and two-pick fixed-priority selection and muxing circuits. EWDTS 2016: 1-4 - [c22]Mert Büyükmihçi, Vecdi Emre Levent
Output Domain Downscaler. ISCIS 2016: 262-269 - 2015
- [c21]Ferhat Canbay, Vecdi Emre Levent
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays. BIBE 2015: 1-5 - [c20]Waqas Hussain, H. Fatih Ugurdag, Murat Uysal
Software defined VLC system: Implementation and performance evaluation. IWOW 2015: 117-121 - [e2]Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis:
VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 461, Springer 2015, ISBN 978-3-319-23798-5 [contents] - 2014
- [j5]Bilgiday Yuce, H. Fatih Ugurdag, Sezer Gören
Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers. IEEE Trans. Computers 63(8): 1868-1881 (2014) - [c19]Furkan Sahin, H. Fatih Ugurdag, Tolga Yalçin
Combined AES + AEGIS Architectures for High Performance and Lightweight Security Applications. ICT Innovations 2014: 213-224 - [c18]Koray Ozansoy, Nuri Ozer, Faruk Donmez, H. Fatih Ugurdag:
A new method for no-reference image Blockiness measurement. SIU 2014: 2114-2117 - 2013
- [j4]Sezer Gören
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration. Comput. Electr. Eng. 39(2): 386-397 (2013) - [c17]Bilgiday Yuce, H. Fatih Ugurdag, Sezer Gören
A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers. IEEE Symposium on Computer Arithmetic 2013: 59-66 - [c16]H. Fatih Ugurdag:
Experiences on the road from EDA developer to designer to educator. EWDTS 2013: 1-4 - [c15]Bilgiday Yuce, Seyrani Korkmaz, Vahap Baris Esen, Fatih Temizkan, Cihan Tunc
Synthesis of clock trees for Sampled-Data Analog IC blocks. EWDTS 2013: 1-4 - [c14]Sezer Gören, Yusuf Turk, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag:
Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only). FPGA 2013: 270 - [c13]Sezer Gören
Enabling difference-based dynamic partial self reconfiguration for large differences. IDT 2013: 1-6 - [c12]H. Fatih Ugurdag, Fatih Temizkan, Sezer Gören
Generating fast logic circuits for m-select n-port Round Robin Arbitration. VLSI-SoC 2013: 260-265 - [e1]Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag:
21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013. IEEE 2013, ISBN 978-1-4799-0522-5 [contents] - 2012
- [j3]H. Fatih Ugurdag, Onur Baskirt:
Fast parallel prefix logic circuits for n2n round-robin arbitration. Microelectron. J. 43(8): 573-581 (2012) - [c11]H. Fatih Ugurdag, Ali Basaran, Taylan Akdogan, V. Ugur Güney, Sezer Gören
FPGA Based Particle Identification in High Energy Physics Experiments. ASAP 2012: 181-184 - [c10]Ali Basaran, H. Fatih Ugurdag, Taylan Akdogan, V. Ugur Güney, Sezer Gören
Ultra-fast curve fitting for pulses on FPGA. SIU 2012: 1-4 - 2011
- [j2]Sezer Gören
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort. ACM J. Emerg. Technol. Comput. Syst. 7(3): 12:1-12:16 (2011) - [c9]H. Fatih Ugurdag, Okan Keskin, Cihan Tunc
RoCoCo: Row and Column Compression for high-performance multiplication on FPGAs. EWDTS 2011: 98-101 - [c8]Sezer Gören
FPGA bitstream protection with PUFs, obfuscation, and multi-boot. ReCoSoC 2011: 1-2 - 2010
- [j1]H. Fatih Ugurdag, Sezer Gören
Gravitational pose estimation. Comput. Electr. Eng. 36(6): 1165-1180 (2010) - [c7]Sezer Gören
Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. ETS 2010: 246 - [c6]Sezer Gören
FPGA design security with time division multiplexed PUFs. HPCS 2010: 608-614 - [c5]Sezer Gören
Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort. ISCIS 2010: 399-404
2000 – 2009
- 2006
- [c4]H. Fatih Ugurdag, Yahya Sahin, Onur Baskirt, Soner Dedeoglu, Sezer Gören
Population-Based FPGA Solution to Mastermind Game. AHS 2006: 237-246
1990 – 1999
- 1996
- [c3]H. Fatih Ugurdag, Thomas E. Fuhrman:
Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. ICCD 1996: 514-529 - 1993
- [c2]H. Fatih Ugurdag, Christos A. Papachristou:
A VLIW architecture based on shifting register files. MICRO 1993: 263-268 - 1992
- [c1]H. Fatih Ugurdag, Christos A. Papachristou:
ALMP: A Shifting Memory Architecture for Loop Pipelining. ICCD 1992: 564-568
Coauthor Index
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last updated on 2024-10-07 21:23 CEST by the dblp team
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