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SoCC 2006: Austin, Texas, USA
- 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006. IEEE 2006, ISBN 0-7803-9781-9
- Weixun Yan, Horst Zimmermann
:
A 120nm CMOS Fully Differential Rail-to-Rail I/O Opamp with Highly Constant Signal Behavior. 3-6 - Wonseok Oh, Bertan Bakkaloglu
A CMOS Low-Noise, Low-Dropout Regulator for Transceiver SOC Supply Management. 7-10 - Antoni Portero
Energy-Aware MPEG-4 Single Profile in HW-SW Multi-Platform Implementation. 13-16 - Zahid Khan, Tughrul Arslan, Scott MacDougall:
A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 Standard and its Efficient Implementation on a DSP Processor. 17-20 - Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. 21-24 - Dhruba Chandra, Ullas Pazhayaveetil, Paul D. Franzon
Architecture for Low Power Large Vocabulary Speech Recognition. 25-28 - Hongjiang Song:
A General Method to VLSI Polyphase Filter Analysis and Design for Integrated RF Applications. 31-34 - Hongjiang Song, Syed R. Naqvi, Bertan Bakkaloglu
I/Q-Channel Mismatch Transfer and Amplification Effects and Applications to the Measurement and Calibration of Integrated VLIF RF Receivers. 35-38 - Anh Dinh, Bi Pham:
A Dual-Function Filter for 5.25GHZ Narrowband and 3.6GHZ-10.1GHZ Ultrawideband Systems. 39-42 - Hongjiang Song:
Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication. 43-46 - Adam Major, Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan:
H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture. 49-52 - Phi-Hung Pham, Yogendera Kumar
A Compact and High Performance Switch for Circuit-Switched Network-On-Chip. 53-56 - Yuhua Chen:
Cell Switched Network-on-Chip - Candidate for Billion-Transistor System-on-Chips. 57-60 - Janne Maunu, Joona Marku, Mika Laiho
An On-Chip Measurement Circuit for Calibration by Combination Selection. 63-64 - Chung-Yuan Chen, Jia-Hong Wang, Tai-Ping Sun:
A Novel Mini-LVDS Receiver in 0.35-um CMOS. 65-68 - Seok-Oh Yun, Hyung-Joun Yoo:
A Reconfigurable CMOS Power Amplifier Operating from 0.9 TO 2.4 GHZ for WPAN Application. 69-72 - Haolu Xie, Siqiang Fan, Xin Wang, Albert Z. Wang, Zhihua Wang, Hongyi Chen:
A Pulse-Based Full-Band UWB Transceiver SoC in 0.18μm SiGe BiCMOS. 73-76 - Guilin Chen, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir:
Energy-Aware Code Replication for Improving Reliability in Embedded Chip Multiprocessors. 77-78 - Ya-Nan Wen, Sao-Jie Chen
Optimal Multiple-Bit Huffman Decoding. 79-82 - Martin Hansson, Atila Alvandpour:
A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOS. 83-84 - Hosun Shin, Naeun Zang
Stochastic Glitch Estimation and Path Balancing for Statistical Optimization. 85-88 - Ranjith Kumar, Volkan Kursun
Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison. 89-90 - Xiaoxia Wu, Feng Wang, Yuan Xie:
Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design. 91-92 - Preetham Lakshmikanthan, Karan Sahni, Adrian Nunez:
Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction Methodology. 93-94 - Karen Chow, David Abercrombie, Mark Basel:
Method for Managing Electromigration in SOC'S When Designing for Both Reliability and Manufacturing. 95-102 - ChangRyul Yun, YoungHwan Bae, HanJin Cho, KyoungSon Jhang
Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols and Matching Information. 103-104 - Priya Sundararajan, Sridhar Krishnamurthy, Narayanan Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman:
Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs. 105-106 - Imran Ahmed, Tughrul Arslan:
A Reconfigurable Viterbi Traceback for Implemenation on Turbo Decoding Array. 107-108 - Deepak Mathaikutty, Sandeep K. Shukla:
SoC Design Space Exploration through Automated IP Selection from SystemC IP Library. 109-110 - Zhenyu Qi, Wei Huang, Adam C. Cabe, Wenqian Wu, Yan Zhang, Garrett S. Rose, Mircea R. Stan
A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors. 111-112 - G. Chen, Liping Xue, Jungsub Kim, Kanwaldeep Sobti, Lanping Deng, Xiaobai Sun, Nikos Pitsianis, Chaitali Chakrabarti, Mahmut T. Kandemir, Narayanan Vijaykrishnan:
Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations. 113-114 - Zhiyu Liu, Volkan Kursun
High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling. 115-116 - Rui Tang, Yong-Bin Kim:
A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits. 119-122 - Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski:
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. 123-126 - Ying Wei, Pengbo Sun, Alex Doboli:
Reconfigurable Switched-Capacitor ΔΣ Modulator Topology Design. 127-130 - Jing-Hu Li
A 1.3 V 30-mW 8-BIT 166-MS/s A/D Converter in 0.18 μm CMOS with Reference Generator. 131-134 - Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou:
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. 137-140 - Oluwayomi B. Adamo, Saraju P. Mohanty, Elias Kougianos, Murali R. Varanasi:
VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure Camera. 141-144 - Jayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir:
A Trace-Driven Validation Methodology for Multi-Processor SOCS. 145-148 - Juergen Saalmueller, Jörg Würtz:
Embedded Controllers for Solving Complex Industry Applications. 149-152 - Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, Kaushik Roy:
Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies. 155-159 - Thanh-Tung Hoang, Jong-Pil Son, Yu-Ri Kang, Chae-Ryung Kim, Hae-Young Chung, Soo-Won Kim:
A low complexity, low power, programmable QRS detector based on wavelet transform for Implantable Pacemaker IC. 160-163 - Manjari Agarwal, Praveen Elakkumanan, Ramalingam Sridhar:
Leakage Reduction for Domino Circuits in Sub-65nm Technologies. 164-167 - Alan P. Su, Robert Chen:
Applying ESL in A Dual-Core SoC Platform Designing. 171-174 - Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau:
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. 175-178 - Suresh Srinivasan, Raghavan Ramadoss, Narayanan Vijaykrishnan:
Process Variation Aware Parallelization Strategies for MPSoCs. 179-182 - Christopher K. Y. Chun:
eXtreme Energy Conservation for Mobile Communications. 185-188 - Guangyu Chen, Mahmut T. Kandemir, Mustafa Karaköy:
Compiler Support for Voltage Islands. 189-192 - Balaji Vaidyanathan, Yuan Xie:
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression. 193-196 - Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
Platform-Based Behavior-Level and System-Level Synthesis. 199-202 - Huang-Liang Chen, Hung-Ming Chen:
On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study. 203-206 - Takeshi Kouno, Hidetoshi Onodera:
Consideration of Transition-Time Variability in Statistical Timing Analysis. 207-210 - Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang:
Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. 211-214 - Raj Varada, Simon Tarn, John Benoit, Kris Chou:
SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor. 217-220 - Simon Provost, Bruno Lavigueur, Guy Bois, Gabriela Nicolescu:
Integration of Configurable Processors in a Multiprocessor Platform. 221-224 - Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu:
Crosstalk-aware Energy Reduction in NoC Communication Fabrics. 225-228 - Appaya Devaraj Swaminathan, Tiberiu Seceleanu
Interrupt Communication on the SegBus platform. 229-232 - Akhil Garg, Prashant Dubey:
Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost. 235-238 - Dan Zhao, Yi Wang:
MTNET: Design and Optimization of a Wireless SOC Test Framework. 239-242 - Qian Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie:
Modeling the Impact of Process Variation on Critical Charge Distribution. 243-246 - Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
A Trace Based Framework for Validation of SoC Designs with GALS Systems. 247-250 - Nitin Mohan, Wilson Fung, Manoj Sachdev:
Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory. 253-256 - Behzad Mesgarzadeh, Atila Alvandpour:
A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS. 257-260 - Joyce Yeung, Hamid Mahmoodi
Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies. 261-264 - Ravi Jenkal, Hao Hua, Ambarish M. Sule, W. Rhett Davis
Architecture for Energy Efficient Sphere Decoding. 267-270 - Kieran McLaughlin, Sakir Sezer, Holger Blume
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. 271-274 - Tongtong Chen, Zhengtao Yu, Yuantao Peng, Yanbing Zhang, Huaiyu Dai, Xun Liu:
A Mimo Receiver SOC for CDMA Applications. 275-278 - Ertugrul Demircan:
Effects of Interconnect Process Variations on Signal Integrity. 281-284 - Vasilis F. Pavlidis, Eby G. Friedman:
3-D Topologies for Networks-on-Chip. 285-288 - Vishak Venkatraman, Mark A. Anders, Himanshu Kaul, Wayne P. Burleson, Ram Krishnamurthy:
A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects. 289-292 - Emre Salman, Eby G. Friedman, Radu M. Secareanu:
Substrate and Ground Noise Interactions in Mixed-Signal Circuits. 293-296 - Baker Mohammad
Cache Organization for Embeded Processors: CAM-vs-SRAM. 299-302 - William R. Reohr:
Memories: Exploiting Them and Developing Them. 303-310 - Nitin Mohan, Manoj Sachdev:
Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM. 311-314 - Masanao Yamaoka, Hidetoshi Onodera:
A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. 315-318 - Martin Margala
Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs. 321 - Amit Agarwal, Ram Krishnamurthy:
High-performance energy-efficient memory circuit technologies for sub-45nm technologies. 322 - Azad Naeemi
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities. 323-324 - K. Nagaraj, N. Nayak:
Design of Low Power Digital Phase Lock Loops. 325-326 - N. Dakwala:
Silicon Debug and DFT for SOC IP. 327-328 - Tiberiu Seceleanu
On-Chip Distributed Architectures. 329-330
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