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ISQED 2005: San Jose, California, USA
- 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA. IEEE Computer Society 2005, ISBN 0-7695-2301-3
- Welcome Notes.
- Organizing Committee.
- Technical Subcommittees.
- Steering/Advisory Committee.
- Conference at a Glance.
Tutorial I
- Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi:
Design of sub-90nm Circuits and Design Methodologies. 3-4
Tutorial II
- Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He:
Modeling and Design of Chip-Package Interface. 6
Session EP1- Panel
- Pallab K. Chatterjee:
IP Creation and Use What Roadblocks are Ahead or it is Just Clear and Bumpy Road? 7-9
Plenary Session 1P
- John Kibarian:
Enabling True Design for Manufacturability. 15 - Ashok K. Sinha:
Recent Progress and Remaining Challenges in Pattern Transfer Technologies for Advanced Chip Designs. 17 - Joseph Sawicki:
Shifting Perspective on DFM. 19
Session 1A: Tools and Flows for Quality Design
- Aaron N. Ng, Igor L. Markov:
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing. 22-27 - Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda:
Noise Library Characterization for Large Capacity Static Noise Analysis Tools. 28-34 - Qianying Tang, Jianwen Zhu:
Two-Dimensional Layout Migration by Soft Constraint Satisfaction. 35-39 - Chun Luo, Jun Yang, Longxing Shi, Xufan Wu, Yu Zhang:
Domain Strategy and Coverage Metric for Validation. 40-45
Session 1B: High Level Power/Noise Reduction Techniques
- Dongku Kang, Yiran Chen, Kaushik Roy:
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. 48-53 - Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman:
Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor. 54-58 - Keejong Kim, Chris H. Kim, Kaushik Roy:
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. 59-64 - David Roberts, Todd M. Austin, David T. Blaauw, Trevor N. Mudge, Krisztián Flautner:
Error Analysis for the Support of Robust Voltage Scaling. 65-70
Session 1C: Leakage and Dynamic Power Issues
- Bhavana Jharia, Sankar Sarkar, Rajendra Prasad Agarwal:
Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET. 72-76 - Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits. 77-82 - Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka
, Robert K. Montoye, Richard B. Brown:
Controlled-Load Limited Switch Dynamic Logic Circuit. 83-87 - Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. 88-93
Session 1D: Poster Session
- Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu:
Charge-Based Core and the Model Architecture of BSIM5. 96-101 - Lionel Riviere-Cazaux, Kevin Lucas, Jon Fitch:
Integration Of Design For Manufacturability (DFM) Practices In Design Flows. 102-106 - Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles:
How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. 107-112 - Mini Nanua, David T. Blaauw, Chanhee Oh:
Leakage Current Modeling in PD SOI Circuits. 113-117 - Jasjeet Kaur:
A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA Company. 118-122 - Arun Shrimali, Anand Venkitachalam, Ravi Arora:
Issues and Challenges in Ramp to Production. 123-127 - C. K. Tang, Parag K. Lala, James Patrick Parkerson:
A Technique for Designing Totally Self-Checking Domino Logic Circuits. 128-132 - Claudio Talarico, B. Pillilli, K. L. Vakati, Janet M. Wang:
Early Assessment of Leakage Power for System Level Design. 133-136 - Zhaojun Wo, Israel Koren:
Technology Mapping for Reliability Enhancement in Logic Synthesis. 137-142 - DiaaEldin Khalil, Mohamed Dessouky, Vincent Bourguet, Marie-Minerve Louërat, Andreia Cathelin, Hani F. Ragai
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays. 143-147 - Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders. 148-152 - Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. 153-158 - Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong:
Testing for Resistive Shorts in FPGA Interconnects. 159-163 - Ewa Sokolowska, M. Barszcz, Bozena Kaminska:
TED Thermo Electrical Designer: A New Physical Design Verification Tool. 164-168 - Yong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-Hyun Kim, Jisuk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong:
A Fast Lithography Verification Framework for Litho-Friendly Layout Design. 169-174 - Harmander Deogun, Dennis Sylvester, David T. Blaauw:
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. 175-180 - Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. 181-186 - J. Huynh, B. Ngo, M. Pham, Lili He:
Design of a 10-bit TSMC 0.25um CMOS Digital to Analog Converter. 187-192 - R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh:
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. 193-196 - Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
Design and Evaluation of a Security Scheme for Sensor Networks. 197-201 - M. Welling, Spyros Tragoudas, Haibo Wang:
A Minimum Cut Based Re-Synthesis Approach. 202-207 - Young-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong:
Analysis for Complex Power Distribution Networks Considering Densely Populated Vias. 208-212 - Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. 213-219
ISQED Luncheon Speech
- Michael Keating:
IP Quality: A Design, Not a Verification Problem. 220-224
Session 2A: Test Application and Cost Reduction
- Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos:
Reseeding-Based Test Set Embedding with Reduced Test Sequences. 226-231 - Themistoklis Haniotakis, Spyros Tragoudas, G. Pani:
Reduced Test Application Time Based on Reachability Analysis. 232-237 - Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Using MUXs Network to Hide Bunches of Scan Chains. 238-243 - Ahmad A. Al-Yamani, Edward J. McCluskey:
BIST-Guided ATPG. 244-249 - Irith Pomeranz, Sudhakar M. Reddy:
Dynamic Test Compaction for Bridging Faults. 250-255
Session 2B: DFM and Physical Layout
- Xin Wang, Charles C. Chiang, Jamil Kawa, Qing Su:
A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing. 258-263 - Michel Côté, Philippe Hurat:
Standard Cell Printability Grading and Hot Spot Detection. 264-269 - Puneet Gupta
Performance Driven OPC for Mask Cost Reduction. 270-275 - Jay Jahangiri, David Abercrombie:
Meeting Nanometer DPM Requirements Through DFT. 276-282
Session 2C: Performance and Reliability Analysis for Yield Optimization
- Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. 284-290 - Dipanjan Sengupta, Resve A. Saleh:
Power-Delay Metrics Revisited for 90nm CMOS Technology. 291-296 - Justin Gregg, Tom W. Chen:
Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm. 297-302 - Syed M. Alam, Frank L. Wei, Chee Lip Gan
Electromigration Reliability Comparison of Cu and Al Interconnects. 303-308
Session 3A: Functional Verification and Test Generation
- Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal, Lyes Benalycherif, Romain Kamdem, Younes Lahbib:
Combining System Level Modeling with Assertion Based Verification. 310-315 - Haihua Yan, Gefu Xu, Adit D. Singh:
Low Voltage Test in Place of Fast Clock in DDSI Delay Test. 316-320 - Nicola Bombieri
Functional Verification of Networked Embedded Systems. 321-326 - Maria K. Michael, Stelios Neophytou
Functions for Quality Transition Fault Tests. 327-332
Session 3B: Power Delivery and Distribution
- Mikhail Popovich, Eby G. Friedman:
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems. 334-339 - Aishwarya Dubey:
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop. 340-345 - Navin Srivastava, Xiaoning Qi, Kaustav Banerjee:
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. 346-351 - Qing K. Zhu, David Ayers:
Power Grid Planning for Microprocessors and SOCS. 352-356
Session 3C: Quality System Level Design and Synthesis
- Animesh Datta, Swarup Bhunia
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. 358-363 - Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
An ILP Formulation for Reliability-Oriented High-Level Synthesis. 364-369 - Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong:
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations. 370-374 - Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
Reliability-Centric Hardware/Software Co-Design. 375-380
Session 4A: DFM for Circuit Design
- Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael Talmor, Z. Gur, Joseph B. Bernstein
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE. 382-389 - Henry H. Y. Chan, Zeljko Zilic:
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. 390-395 - Kambiz Rahimi, Chris Diorio:
In-Circuit Self-Tuning of Clock Latencies. 396-401 - Masanori Hashimoto
Statistical Analysis of Clock Skew Variation in H-Tree Structure. 402-407
Session 4B: Leakage and Reliability Management
- Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. 410-415 - Ananth Somayaji Goda, Gautam Kapila:
Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms. 416-420 - Puneet Gupta
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. 421-426 - Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev:
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. 427-432
Session 4C: Analog Test and BIST
- Amit Laknaur, Haibo Wang:
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. 434-439 - Daniela De Venuto
A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC. 440-447 - Lampros Dermentzoglou, Y. Tsiatouhas
A Built-In Self-Test Scheme for Differential Ring Oscillators. 448-452 - Swarup Bhunia
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. 453-458
Session EP2
- Mark S. Lundstrom, Philip Wong, Kazuo Yano:
Nanoelectronics: Evolution or Revolution? 459
Plenary Session 2P
- Lech Józwiak, Kaustav Banerjee:
Plenary Session 2P. 461 - Aki Fujimura:
Quality and EDA. 463-463 - Kurt A. Wolf:
IP Quality: A New Model that Faces Methodology and Management Challenges. 465-465 - Bernard Candaele:
SoC Engineering Trends as Impacted by New Applications and System Level Requirements. 467-467
Session 5A: Design Methods and Tools in DSM
- Jihyun Lee, Yong-Bin Kim:
ASLIC: A Low Power CMOS Analog Circuit Design Automation. 470-475 - Yuanzhong Paul Zhou, Duane Connerney, Ronald Carroll, Timwah Luk:
Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models. 476-481 - Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin:
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. 482-487
Session 5B: Design Techniques for Leakage Reduction
- Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. 490-495 - Xiaojun Li, Joerg D. Walter, Joseph B. Bernstein
Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature. 496-502 - Vishal Gupta, Gabriel A. Rincón-Mora:
Predicting and Designing for the Impact of Process Variations and Mismatch on the Trim Range and Yield of Bandgap References. 503-508
Session 5C: Variability Issues in Nanoscale Circuits
- Norman G. Gunther, Emad Hamadeh, Darrell Niemann, Iliya Pesic, Mahmud Rahman:
Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOS. 510-515 - Paul Friedberg, Yu Cao, Jason Cain, Ruth Wang, Jan M. Rabaey, Costas J. Spanos:
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization. 516-521 - Vishak Venkatraman, Wayne P. Burleson:
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. 522-527
Session 6A: Issues in Noise and Timing
- Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan:
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. 530-535 - Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin:
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis. 536-541 - Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. 542-547 - Deepak C. Sekar:
Clock trees: differential or single ended?. 548-553
Session 6B: Design Approaches for System in Package (SiP)
- Bill McCaffrey:
Exploring the Challenges in Creating a High-Quality Mainstream Design Solution for System-in-Package (SiP) Design. 556-561 - Anru Wang, Wayne Wei-Ming Dai:
Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP). 562-566 - Chung-Seok (Andy) Seo, Abhijit Chatterjee, Nan M. Jokerst:
This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms. 567-572 - Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen:
Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. 573-578
Session 6C: DSM Interconnect Issues
- Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong
Current Calculation on VLSI Signal Interconnects. 580-585 - Atsushi Kurokawa, Toshiki Kanamoto
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. 586-591 - Vinita V. Deodhar, Jeffrey A. Davis:
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. 592-597 - Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye
Interconnect Delay and Slew Metrics Using the First Three Moments. 598-602 - Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan:
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. 603-608
Session 7A: Advances in Floor Planning
- Meng-Chiou Wu, Rung-Bin Lin:
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. 610-615 - Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang:
Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. 616-621 - Hua Xiang, I-Min Liu, Martin D. F. Wong
Wire Planning with Bounded Over-the-Block Wires. 622-627 - Song Chen
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. 628-633 - Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye
Thermal-Aware Floorplanning Using Genetic Algorithms. 634-639
Session 7B: Issues in On-Chip Communication and Analog/RF Designs
- Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan:
Joint Equalization and Coding for On-Chip Bus Communication. 642-647 - Sani R. Nassif, Zhuo Li:
A More Effective CEFF. 648-653 - Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. 654-661 - Ali Zahabi, Omid Shoaei
Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder Filter. 662-667 - Payam Heydari:
Design Considerations for Low-Power Ultra Wideband Receivers. 668-673
Session 7C: Robust Design under Parameter Variations
- Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung
A New Method for Design of Robust Digital Circuits. 676-681 - Hao Yu, Lei He:
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. 682-687 - Wei Ling, Yvon Savaria:
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. 688-693 - Andres Teene, Bob Davis, Ruggero Castagnetti, Jeff Brown, S. Ramesh:
Impact of Interconnect Process Variations on Memory Performance and Design. 694-699
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