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ISPD 2002: Del Mar, CA, USA
- Sachin S. Sapatnekar, Massoud Pedram:
Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002. ACM 2002, ISBN 1-58113-460-6 - Steven L. Teig:
Challenges and principles of physical design. 3-4
Placement
- Ulrich Brenner, André Rohe:
An effective congestion driven placement framework. 6-11 - Saurabh N. Adya, Igor L. Markov:
Consistent placement of macro-blocks using floorplanning and standard-cell placement. 12-17
Leakage Current
- Geoffrey C.-F. Yeap:
Leakage current in low standby power and high performance devices: trends and challenges. 22-27 - Vivek De:
Leakage-tolerant design techniques for high performance processors. 28-28
Physical Hierarchy
- Yongseok Cheon, D. F. Wong
:
Design hierarchy guided multilevel circuit partitioning. 30-35 - Chin-Chih Chang, Jason Cong, David Zhigang Pan:
Physical hierarchy generation with routing congestion control. 36-41 - Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh:
Routability driven white space allocation for fixed-die standard-cell placement. 42-47
Floorplanning and Postlayout Optimization
- Chiu-Wing Sham, Evangeline F. Y. Young:
Routability driven floorplanner with buffer block planning. 50-55 - Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. 56-61 - Shuo Zhang, Wayne Wei-Ming Dai:
TEG: a new post-layout optimization method. 62-67 - Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif:
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. 68-73
Thermal Issues
- Sung-Mo Kang:
On-chip thermal engineering for peta-scale integration. 76-76
Crosstalk Noise
- Prashant Saxena, Satyanarayan Gupta:
Shield count minimization in congested regions. 78-83 - Pinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer:
On convergence of switching windows computation in presence of crosstalk noise. 84-89
Butffer Insertion
- Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. 92-97 - Milos Hrkic, John Lillis:
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. 98-103 - Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. 104-109
Future Design Trends
- Andrew B. Kahng:
A roadmap and vision for physical design. 112-117 - Chunhong Chen:
Physical design with multiple on-chip voltages. 118-118
Poster Paper Introductions
- Lauren Hui Chen, Malgorzata Marek-Sadowska:
Incremental delay change due to crosstalk noise. 120-125 - Masanori Hashimoto
Crosstalk noise optimization by post-layout transistor sizing. 126-130 - Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Understanding and addressing the impact of wiring congestion during technology mapping. 131-136 - Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Closing the smoothness and uniformity gap in area fill synthesis. 137-142 - Andrew B. Kahng, Stefanus Mantik, Igor L. Markov:
Min-max placement for large-scale timing optimization. 143-148 - Jason Cong, Chang Wu:
Global clustering-based performance-driven circuit partitioning. 149-154 - H. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul:
Net criticality revisited: an effective method to improve timing in physical design. 155-160 - Bo Hu, Malgorzata Marek-Sadowska:
FAR: fixed-points addition & relaxation based placement. 161-166
Timing Closure
- Jason Cong:
Timing closure based on physical hierarchy. 170-174
Routing
- Seokjin Lee, D. F. Wong
Timing-driven routing for FPGAs based on Lagrangian relaxation. 176-181 - Hui Xu, Rob A. Rutenbar, Karem A. Sakallah:
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. 182-187
Topics in Physical Design
- Wai-Kei Mak, Evangeline F. Y. Young:
Temporal logic replication for dynamically reconfigurable FPGA partitioning. 190-195 - Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen:
Twin binary sequences: a non-redundant representation for general non-slicing floorplan. 196-201 - Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob White:
Geometrically parameterized interconnect performance models for interconnect synthesis. 202-207
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