Article

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages

Authors:

Miloš Hrkić,

John LillisAuthors Info & Claims

ISPD '02: Proceedings of the 2002 international symposium on Physical design

Pages 98 - 103

https://doi.org/10.1145/505388.505413

Published: 07 April 2002 Publication History

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Abstract

We give an overview of a buffer tree synthesis package which pays particular attention to the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, exploitation of temporal locality among the sinks and addressing sink polarity requirements. Experimental results demonstrate the effectiveness of the tool in comparison with previously proposed techniques.

References

[1]

C. Alpert, et. al. "Buffered Steiner Trees for Difficult Instances," ISPD-01, pp. 4--9.

Digital Library

Google Scholar

[2]

J. Cong, "Challenges and Opportunities for Design Innovations in Nanometer Technologies," Frontiers in Semiconductor Research: A Collection of SRC Working Papers. SRC, 1997.

Google Scholar

[3]

J. Cong, X. Yuan, "Routing Tree Construction Under Fixed Buffer Locations," DAC-2000, pp. 368--373.

Digital Library

Google Scholar

[4]

M. Hrkić, J. Lillis, "S-Tree: A Technique for Buffered Routing Tree Synthesis" SASIMI-2001, pp. 242--249.

Digital Library

Google Scholar

[5]

M. Hrkić, J. Lillis, TR# UIC-CS-02-1, http://www.cs.uic.edu/~jlillis/sptree_tech.pdf

Google Scholar

[6]

S.-W. Hur, A. Jagannathan, J. Lillis, "Timing-Driven Maze Routing," IEEE Transactions on Computer Aided Design Feb. 2000, vol. 19, no. 2, pp. 234--241.

Digital Library

Google Scholar

[7]

A. Jagannathan, S.-W. Hur, J. Lillis, "A Fast Algorithm for Context-Aware Buffer Insertion," DAC-2000, pp. 368--373.

Digital Library

Google Scholar

[8]

J. Lillis, C.-K. Cheng, T.-T. Y Lin, "Optimal Wire Sizing and Buffer insertion for Low Power and a Generalized Delay Model," IEEE Journal of Solid State Circuits, 31 (3): pp. 437--447, March 1996.

Crossref

Google Scholar

[9]

J. Lillis, C.-K. Cheng, T.-T. Y. Lin, "Simultaneous Routing and Buffer Insertion for High Performance Interconnect," Proc. 6th IEEE Great Lakes Symposium on VLSI, Ames, Iowa, Mar. 1996, pp. 148--153.

Digital Library

Google Scholar

[10]

J. Lillis, C.-K. Cheng, T.-T. Y Lin, "New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing," DAC-96.

Digital Library

Google Scholar

[11]

T. Okamoto, J. Cong, "Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization," ICCAD-96, pp. 44--49, 1996.

Digital Library

Google Scholar

[12]

L.P.P.P. van Ginneken, "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay," ISCAS-90, pp. 865--868, 1990.

Google Scholar

[13]

H. Zhou, D.F. Wong, I.M. Liu, A. Aziz, "Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations," DAC-99, pp. 96--99.

Digital Library

Google Scholar

Cited By

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Qi CWang GChen Y(2007)Performance-Driven Routing Tree Construction with Buffer Insertion, Wire Sizing under RLC Delay Model2007 International Conference on Mechatronics and Automation10.1109/ICMA.2007.4304112(3418-3423)Online publication date: Aug-2007
https://doi.org/10.1109/ICMA.2007.4304112
Bartoschek CHeld SRautenbach DVygen JScheffer L(2006)Efficient generation of short and fast repeater tree topologiesProceedings of the 2006 international symposium on Physical design10.1145/1123008.1123032(120-127)Online publication date: 9-Apr-2006
https://dl.acm.org/doi/10.1145/1123008.1123032
Peng YLiu X(2006)An Efficient Low-Power Repeater-Insertion SchemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88260125:12(2726-2736)Online publication date: 1-Dec-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.882601
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Index Terms

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Information & Contributors

Information

Published In

ISPD '02: Proceedings of the 2002 international symposium on Physical design

April 2002

216 pages

ISBN:1581134606

DOI:10.1145/505388

General Chair:
Sachin Sapatnekar
University of Minnesota
,
Program Chair:
Massoud Pedram
USC

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 April 2002

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ISPD02: International Symposium on Physical Design

April 7 - 10, 2002

CA, San Diego, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

View all

Qi CWang GChen Y(2007)Performance-Driven Routing Tree Construction with Buffer Insertion, Wire Sizing under RLC Delay Model2007 International Conference on Mechatronics and Automation10.1109/ICMA.2007.4304112(3418-3423)Online publication date: Aug-2007
https://doi.org/10.1109/ICMA.2007.4304112
Bartoschek CHeld SRautenbach DVygen JScheffer L(2006)Efficient generation of short and fast repeater tree topologiesProceedings of the 2006 international symposium on Physical design10.1145/1123008.1123032(120-127)Online publication date: 9-Apr-2006
https://dl.acm.org/doi/10.1145/1123008.1123032
Peng YLiu X(2006)An Efficient Low-Power Repeater-Insertion SchemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88260125:12(2726-2736)Online publication date: 1-Dec-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.882601
Alpert CHu JSapatnekar SSze C(2006)Accurate estimation of global buffer delay within a floorplanIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85588925:6(1140-1145)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.855889
Li ZShi W(2006)An O(bn2) time algorithm for optimal buffer insertion with b buffer typesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85463125:3(484-489)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.854631
Dechu SShen CChu C(2006)An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.84410724:4(600-608)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.844107
Alpert CGandham GHrkic MHu JQuay SSze C(2006)Porosity-aware buffered Steiner tree constructionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82586423:4(517-526)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.825864
Saxena PMenezes NCocchini PKirkpatrick D(2006)Repeater scaling and its impact on CADIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82584123:4(451-463)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.825841
Jing THong XXu JBao HCheng CGu J(2006)UTACOIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82335423:3(358-365)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.823354
Hrkic MLillis J(2006)Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockagesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.80964822:4(481-491)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2003.809648
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