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21st IOLTS 2015: Halkidiki, Greece
- 21st IEEE International On-Line Testing Symposium, IOLTS 2015, Halkidiki, Greece, July 6-8, 2015. IEEE 2015, ISBN 978-1-4673-7905-2
- Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria:
Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients. 1-6 - Alessandro Vallero, Alessandro Savino, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Gianfranco Politano, Dimitris Gizopoulos, Stefano Di Carlo:
Bayesian network early reliability evaluation analysis for both permanent and transient faults. 7-12 - Marc Lacruche, Nicolas Borrel, Clement Champeix, Cyril Roscian, Alexandre Sarafianos, Jean-Baptiste Rigaud
, Jean-Max Dutertre
Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses. 13-18 - Dan Alexandrescu, Adrian Evans, Enrico Costenaro, Maximilien Glorieux:
A call for cross-layer and cross-domain reliability analysis and management. 19-22 - Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi
An accurate soft error propagation analysis technique considering temporal masking disablement. 23-25 - Serhiy Avramenko, Stefano Esposito, Massimo Violante, Marco Sozzi, Massimo Traversone, Marco Binello, Marco Terrone:
An Hybrid Architecture for consolidating mixed criticality applications on multicore systems. 26-29 - Vasileios Gerakis, Leonidas Katselas, Alkis A. Hatzopoulos
Fault modeling and testing of through silicon via interconnections. 30-31 - Chiara Sandionigi, Olivier Héron:
Identifying aging-aware representative paths in processors. 32-33 - Riccardo Cantoro
On the maximization of the sustained switching activity in a processor. 34-35 - Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco:
Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. 36-39 - Bodhisatwa Mazumdar, Sk Subidh Ali
Power analysis attacks on ARX: An application to Salsa20. 40-43 - Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah:
Simplification of fully delay testable combinational circuits. 44-45 - Katerina Katsarou, Yiorgos Tsiatouhas
Soft error immune latch under SEU related double-node charge collection. 46-49 - Joseph Lenox, Spyros Tragoudas:
Towards Trojan circuit detection with maximum state transition exploration. 50-52 - Suvadeep Banerjee
Concurrent error detection in nonlinear digital filters using checksum linearization and residue prediction. 53-58 - Diane Tchuani Tchakonte, Emmanuel Simeu, Maurice Tchuenté:
Adaptive healing procedure for lifetime improvement in Wireless Sensor Networks. 59-64 - Andreina Zambrano, Hans G. Kerkhoff:
Fault-tolerant system for catastrophic faults in AMR sensors. 65-70 - Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis:
MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip. 71-76 - Alexandros Panteloukas, Anastasios Psarras
Timing-resilient Network-on-Chip architectures. 77-82 - Gontran Sion, Yves Blaquière, Yvon Savaria:
Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. 83-88 - Imran Wali, Arnaud Virazel
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. 89-94 - Alexander Schöll, Claus Braun, Michael A. Kochte, Hans-Joachim Wunderlich:
Efficient on-line fault-tolerance for the preconditioned conjugate gradient method. 95-100 - Ijeoma Anarado, Yiannis Andreopoulos:
Mitigation of fail-stop failures in integer matrix products via numerical packing. 101-107 - Jacob A. Abraham, Ravishankar K. Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian:
The future of fault tolerant computing. 108-109 - Michael A. Skitsas, Chrysostomos Nicopoulos
Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors. 110-115 - Monir Zaman, Ali Ahmadi, Yiorgos Makris
Workload characterization and prediction: A pathway to reliable multi-core systems. 116-121 - Mohammad Ashraful Anam, Yiannis Andreopoulos:
Failure mitigation in linear, sesquilinear and bijective operations on integer data streams via numerical entanglement. 122-127 - Mehdi Baradaran Tahoori, Abhijit Chatterjee, Krishnendu Chakrabarty
Self-awareness and self-learning for resiliency in real-time systems. 128-131 - Tong-Yu Hsieh, Yi-Han Peng:
Filtering-based error-tolerability evaluation of image processing circuits. 132-137 - Nektarios Kranitis
A single chip dependable and adaptable payload Data Processing Unit. 138-143 - Jaime Espinosa
Characterizing fault propagation in safety-critical processor designs. 144-149 - Clement Champeix, Nicolas Borrel, Jean-Max Dutertre
Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currents. 150-155 - Jing Ye, Yu Hu, Xiaowei Li
OPUF: Obfuscation logic based physical unclonable function. 156-161 - Adrian Evans, Enrico Costenaro, Arkady Bramnik:
Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF). 162-167 - Gurgen Harutunyan, Yervant Zorian:
An effective embedded test & diagnosis solution for external memories. 168-170 - Panagiota Papavramidou, Michael Nicolaidis:
Low-power memory repair for high defect densities. 171-173 - Amr Haggag, Nik Sumikawa, Aamer Shaukat:
Reliability/yield trade-off in mitigating "no trouble found" field returns. 174-175 - Chang Liu, Michael A. Kochte, Hans-Joachim Wunderlich:
Efficient observation point selection for aging monitoring. 176-181 - Zissis Poulos, Andreas G. Veneris:
Mining simulation metrics for failure triage in regression testing. 182-187 - Miho Ueno, Masanori Hashimoto
Real-time on-chip supply voltage sensor and its application to trace-based timing error localization. 188-193 - Daniele Rossi
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories. 194-199 - Lake Bu, Mark G. Karpovsky, Zhen Wang:
New byte error correcting codes with simple decoding for reliable cache design. 200-205 - Nikolaos Eftaxiopoulos-Sarris, Nicholas Axelos, Kiamal Z. Pekmestzi:
Low leakage radiation tolerant CAM/TCAM cell. 206-211
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