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Dan Alexandrescu
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2020 – today
- 2023
- [c44]Fei Su, Meirav Nitzan, Ankush Sethi, Vaibhav Kumar, Dan Alexandrescu:
Innovation Practices Track: VLSI Functional Safety. VTS 2023: 1 - 2021
- [c43]Aneesh Balakrishnan
, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu:
Modeling Soft-Error Reliability Under Variability. DFT 2021: 1-6 - [c42]Aneesh Balakrishnan
Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis. ISQED 2021: 24-30 - [c41]Xinhui Lai, Thomas Lange, Aneesh Balakrishnan
On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. VLSI-SoC 2021: 1-6 - [i10]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. CoRR abs/2104.01812 (2021) - [i9]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. CoRR abs/2104.01900 (2021) - [i8]Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin:
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. CoRR abs/2104.01908 (2021) - [i7]Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux:
Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models. CoRR abs/2104.10941 (2021) - 2020
- [c40]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE 2020: 388-393 - [c39]Dan Alexandrescu, Aneesh Balakrishnan
Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models. IOLTS 2020: 1-6 - [c38]Thomas Lange, Aneesh Balakrishnan
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. IOLTS 2020: 1-7 - [c37]Aneesh Balakrishnan
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. MECO 2020: 1-5 - [i6]Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. CoRR abs/2002.05455 (2020) - [i5]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. CoRR abs/2002.08882 (2020) - [i4]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. CoRR abs/2002.09945 (2020) - [i3]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. CoRR abs/2008.13664 (2020)
2010 – 2019
- 2019
- [j6]Xinhui Lai, Aneesh Balakrishnan
Understanding multidimensional verification: Where functional meets non-functional. Microprocess. Microsystems 71 (2019) - [c36]Aneesh Balakrishnan
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. AHS 2019: 72-78 - [c35]Maksim Jenihhin, Matteo Sonza Reorda
Challenges of Reliability Assessment and Enhancement in Autonomous Systems. DFT 2019: 1-6 - [c34]Thomas Lange, Aneesh Balakrishnan
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. DSN (Supplements) 2019: 35-41 - [c33]Thomas Lange
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. DTIS 2019: 1-6 - [c32]Thomas Lange, Aneesh Balakrishnan
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. IOLTS 2019: 7-14 - [c31]Aneesh Balakrishnan
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. NORCAS 2019: 1-7 - [e2]Dimitris Gizopoulos, Dan Alexandrescu, Panagiota Papavramidou, Michail Maniatakos:
25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, Rhodes, Greece, July 1-3, 2019. IEEE 2019, ISBN 978-1-7281-2490-2 [contents] - [i2]Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu:
Challenges of Reliability Assessment and Enhancement in Autonomous Systems. CoRR abs/1909.03040 (2019) - [i1]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR abs/1912.01561 (2019) - 2018
- [c30]Luca Sterpone
A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. AHS 2018: 120-126 - [c29]Muhammed Ceylan Morgül, Onur Tunali
Integrated Synthesis Methodology for Crossbar Arrays. NANOARCH 2018: 91-97 - [e1]Dimitris Gizopoulos, Dan Alexandrescu, Mihalis Maniatakos, Panagiota Papavramidou:
24th IEEE International Symposium on On-Line Testing And Robust System Design, IOLTS 2018, Platja D'Aro, Spain, July 2-4, 2018. IEEE 2018, ISBN 978-1-5386-5992-2 [contents] - 2017
- [j5]Dan Alexandrescu, Mustafa Altun
Logic synthesis and testing techniques for switching nano-crossbar arrays. Microprocess. Microsystems 54: 14-25 (2017) - [c28]Dan Alexandrescu, Adrian Evans, Maximilien Glorieux, Issam Nofal:
EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety. IOLTS 2017: 145-150 - 2016
- [c27]Dan Alexandrescu, Mustafa Altun
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer. DSD 2016: 334-341 - 2015
- [j4]Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi:
Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10): 1586-1599 (2015) - [c26]Dan Alexandrescu, Adrian Evans, Enrico Costenaro, Maximilien Glorieux:
A call for cross-layer and cross-domain reliability analysis and management. IOLTS 2015: 19-22 - [c25]Jacob A. Abraham, Ravishankar K. Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian:
The future of fault tolerant computing. IOLTS 2015: 108-109 - [c24]Adrian Evans, Dan Alexandrescu, Veronique Ferlet-Cavrois, Kay-Obbe Voss:
Techniques for heavy ion microbeam analysis of FPGA SER sensitivty. IRPS 2015: 6 - 2014
- [c23]Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu:
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales. DATE 2014: 1-6 - [c22]Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio:
INFORMER: An integrated framework for early-stage memory robustness analysis. DATE 2014: 1-4 - [c21]Dan Alexandrescu, Luca Sterpone
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation. ETS 2014: 1-6 - [c20]Andreas Steininger
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD 2014: 61-67 - [c19]Hao Xie, Li Chen
New approaches for synthesis of redundant combinatorial logic for selective fault tolerance. IOLTS 2014: 62-68 - [c18]Dan Alexandrescu, Nematollah Bidokhti, Andy Yu, Adrian Evans, Enrico Costenaro:
Managing SER costs of complex systems through Linear Programming. IOLTS 2014: 216-219 - 2013
- [j3]Enrico Costenaro, Dan Alexandrescu, Kader Belhaddad, Michael Nicolaidis:
A Practical Approach to Single Event Transient Analysis for Highly Complex Design. J. Electron. Test. 29(3): 301-315 (2013) - [c17]Adrian Evans, Dan Alexandrescu, Enrico Costenaro, Liang Chen:
Hierarchical RTL-based combinatorial SER estimation. IOLTS 2013: 139-144 - [c16]Dan Alexandrescu, Enrico Costenaro, Adrian Evans:
State-aware single event analysis for sequential logic. IOLTS 2013: 151-156 - [c15]Alireza Rohani, Hans G. Kerkhoff, Enrico Costenaro, Dan Alexandrescu:
Pulse-length determination techniques in the rectangular single event transient fault model. ICSAMOS 2013: 213-218 - 2012
- [j2]Cécile Weulersse, Florent Miller, Dan Alexandrescu, Erwin Schaefer, Olivier Crépel, Rémi Gaillard:
Test methodology of a new upset mechanism induced by protons in deep sub-micron devices. Microelectron. Reliab. 52(9-10): 2482-2486 (2012) - [c14]Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. ICCD 2012: 472-477 - [c13]Miguel Vilchis, Ramnath Venkatraman, Enrico Costenaro, Dan Alexandrescu:
A real-case application of a synergetic design-flow-oriented SER analysis. IOLTS 2012: 43-48 - [c12]Adrian Evans, Michael Nicolaidis, Shi-Jie Wen, Dan Alexandrescu, Enrico Costenaro:
RIIF - Reliability information interchange format. IOLTS 2012: 103-108 - [c11]Dan Alexandrescu, Enrico Costenaro:
Towards optimized functional evaluation of SEE-induced failures in complex designs. IOLTS 2012: 182-187 - 2011
- [c10]Dan Alexandrescu, Enrico Costenaro, Michael Nicolaidis:
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs. DFT 2011: 155-163 - [c9]Enrico Costenaro, Massimo Violante, Dan Alexandrescu:
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. IOLTS 2011: 49-54 - [c8]Dan Alexandrescu:
A comprehensive soft error analysis methodology for SoCs/ASICs memory instances. IOLTS 2011: 175-176 - 2010
- [c7]Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota:
Panel: Reliability of data centers: Hardware vs. software. DATE 2010: 1620
2000 – 2009
- 2009
- [c6]Dan Alexandrescu, Anne-Lise Lhomme-Perrot, Erwin Schäfer, Cyrille Beltrando:
Highs and lows of radiation testing. IOLTS 2009: 179 - 2008
- [c5]Shi-Jie Wen, Dan Alexandrescu, Renaud Perez:
A Systematical Method of Quantifying SEU FIT. IOLTS 2008: 109-114 - [c4]Michael Nicolaidis, Renaud Perez, Dan Alexandrescu:
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors. VTS 2008: 371-376 - 2004
- [j1]Dan Alexandrescu, Lorena Anghel
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. J. Electron. Test. 20(4): 413-421 (2004) - 2002
- [c3]Dan Alexandrescu, Lorena Anghel
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. DFT 2002: 99-107 - [c2]Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis:
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. LATW 2002: 126-129 - 2000
- [c1]Lorena Anghel, Dan Alexandrescu, Michael Nicolaidis:
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy. SBCCI 2000: 237-242
Coauthor Index
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