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ICICDT 2017: Austin, TX, USA
- 2017 IEEE International Conference on IC Design and Technology, ICICDT 2017, Austin, TX, USA, May 23-25, 2017. IEEE 2017, ISBN 978-1-5090-4502-0
- Shinichi Takagi, D. H. Ahn, Takahiro Gotow
, M. Noguchi, K. Nishi, S.-H. Kim, M. Yokoyama, C.-Y. Chang, S.-H. Yoon, C. Yokoyama, Mitsuru Takenaka:
III-V-based low power CMOS devices on Si platform. 1-4 - Eunah Ko
Layout engineering to suppress hysteresis of negative capacitance FinFET. 1-3 - Walter Schwarzenbach, Manuel Sellier, Bich-Yen Nguyen, Christophe Girard, Christophe Maleville:
FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond. 1-2 - D. H. Triyoso
Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor. 1-4 - Kristy J. Kormondy, Alexander A. Demkov, Youri Popoff, Marilyne Sousa, Felix Eltes, Daniele Caimi, Chiara Marchiori, Jean Fompeyrine, Stefan Abel:
Microstructure and ferroelectricity of barium titanate thin films on Si for integrated photonics. 1-2 - Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta:
SRAM designs for 5nm node and beyond: Opportunities and challenges. 1-4 - Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene:
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. 1-4 - David C. Gilmer, Thomas Rueckes, Lee Cleveland, Darlene Viviani:
NRAM status and prospects. 1-4 - Eman Badr, Heba A. Shawkey
Wideband inductorless CMOS RF front-end for LTE receivers. 1-4 - Giuseppe E. Biccario, Massimo de Vittorio, Stefano D'Amico:
Fluids energy harvesting system with low cut-in velocity piezoelectric MEMS. 1-4 - Honghuang Lin, Asad M. Khan, Peng Li:
Statistical circuit performance dependency analysis via sparse relevance kernel machine. 1-4 - Louise De Conti, Thomas Bedecarrats, Maud Vinet, Sorin Cristoloveanu, Philippe Galy:
Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies. 1-4 - Milos Skalsky, Stanislav Banas, Vaclav Panko:
A resistance model of integrated octagonal-shaped Hall sensor using JFET compact model. 1-4 - Adam Issa, Rouwaida Kanj, Ali Chehab
Yield and energy tradeoffs of an NVLatch design using radial sampling. 1-4 - Takumi Hasegawa, Yoshiki Yamamoto, Hideki Makiyama, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi:
SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive. 1-4 - Olivier Weber:
FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications. 1-3 - Koichiro Ishibashi, Junya Kikuchi, Nobuyuki Sugii
A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applications. 1-3 - Hai-Phong Phan, Xuan-Tu Tran
Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip. 1-4 - Karthik Ramanan, Jacob Williams:
A low power fast wakeup flash memory system for embedded SOCs. 1-4 - Mei Han
Low power Adiabatic Logic based on 2PC2AL. 1-4 - Kiyoshi Mori, Giang Dao, Ziep Tran, Michael Ramon, Jason Woo, Peng Lu:
Innovative and 3D stacking Micro Electro Mechanical Systems (I-MEMS) for power saving. 1-3 - Eric Pop
Electrons, phonons, and unconventional applications of 2D materials. 1-2 - Carlotta Guiducci:
Integrated electrical sensing for high-throughput bioanalytics. 1-3 - Lauren Guckert, Earl E. Swartzlander Jr.:
Dadda Multiplier designs using memristors. 1-4 - Giulia Usai, Louis Hutin, Jose Luis Muñoz-Gamarra
Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays. 1-4 - Louis Hutin, Benoit Bertrand, Romain Maurand, Matias Urdampilleta
SOI CMOS technology for quantum information processing. 1-4 - Patrick Ponath, Agham B. Posadas, Yuan Ren, Xiaoyu Wu, Keji Lai, Alex Demkov, Michael Schmidt, Ray Duffy
Advances of the development of a ferroelectric field-effect transistor on Ge(001). 1-3 - Ryu Hasunuma:
Interfacial transition layer in thermally grown SiO2 film on 4H-SiC. 1-4 - Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi:
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. 1-4
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