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Trong Huynh Bao
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2010 – 2019
- 2019
- [c6]Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta:
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC 2019: 13 - 2017
- [j1]Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei
, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq:
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1669-1680 (2017) - [c5]Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta:
SRAM designs for 5nm node and beyond: Opportunities and challenges. ICICDT 2017: 1-4 - [c4]Manu Komalan, Sushil Sakhare, Trong Huynh Bao, Siddharth Rao
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. ISCAS 2017: 1-4 - 2015
- [c3]Trong Huynh Bao
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. ICICDT 2015: 1-4 - 2014
- [c2]Trong Huynh Bao
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC 2014: 102-105 - 2013
- [c1]Stefano Di Carlo
ZipStream: Improving dependability in dynamic partial reconfiguration. IDT 2013: 1-6
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