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ICCD 1994: Cambridge, MA, USA
- Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994. IEEE Computer Society 1994, ISBN 0-8186-6565-3
CAD Plenary
- Neil Weste:
OK, If These CAD Tools Are So Great, Why Isn't My Chip Design On Schedule?. 2-8
VLSI Plenary
- William S. Carter:
The Future of Programmable Logic and Its Impact on Digital System Design. 10-16
D&T Plenary
- Prathima Agrawal:
Emerging Techologies for Electronic Design and Test. 18
Combinational Logic Synthesis
- Andreas Kuehlmann, Lukas P. P. P. van Ginneken:
Grammar-Based Optimization of Synthesis Scenarios. 20-25 - Aiguo Lu, Jonathan Saul, Erik L. Dagless:
Architecture Oriented Logic Optimization for Lookup Table Based FPGAs. 26-29 - Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram:
FPGA Synthesis Using Function Decomposition. 30-35 - Qinghong Wu, C. Y. Roger Chen, John M. Acken:
Efficent Boolean Matching Algorithm for Cell Libraries. 36-39
Memory Architectures
- David J. Lilja, Shanthi Ambalavanan:
A Superassociative Tagged Cache Coherence Directory. 42-45 - Lishing Liu:
Issues in Multi-Level Cache Designs. 46-52 - Jeffrey D. Gee, Alan Jay Smith:
Analysis of Multiprocessor Memory Refernce Behavior. 53-59 - Rupinder Hundal, Vojin G. Oklobdzija:
Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination. 60-64
Parallel Processing and Fault Tolerance
- M. Morioka, K. Kurosawa, S. Miura, T. Nakamikawa, S. Ishikawa:
Design and Evaluation of the High Performance Multi-Processor Server. 66-69 - Sangho Ha, Junghwan Kim, Eunha Rho, Yoonhee Nah, Sangyong Han, Daejoon Hwang, Heunghwan Kim, Seung Ho Cho:
A Massively Parallel Multithreaded Architecture: DAVRID. 70-74 - Hussain Al-Asaad, Mankuan Michael Vai, James Feldman:
Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths. 75-78 - Choong Gun Oh, Hee Yong Youn:
Fault Tolerant Processor Arrays for Nonlinear Shortest Path Problem. 79-83
Synthesis for Testability
- Wuudiann Ke, Premachandran R. Menon:
Delay-Verifiability of Combinational Circuits Based on Primitive Faults. 86-90 - Sandeep Bhatia, Niraj K. Jha:
Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. 91-96 - Shangzhi Sun, David Hung-Chang Du, Duen-Ren Liu:
Testability Considerations. 97-100 - Ian G. Harris, Alex Orailoglu:
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. 101-104
Formal Representation
- Bernd Becker, Rolf Drechsler:
OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. 106-110 - Aarti Gupta
, Allan L. Fisher:
Tradeoffs in Canonical Sequential Function Representations. 111-116 - Zheng Zhu, Steven D. Johnson:
Capturing Synchronization Specifications for Sequential Compositions. 117-121
Concurrent Error Detection
- Chin-Long Wey:
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data. 124-127 - Stanislaw J. Piestrak:
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes. 128-131 - Fahad M. Alzahrani, Tom Chen:
On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. 132-137
Instruction Scheduling
- Ray A. Kamin III, George B. Adams III, Pradeep K. Dubey:
Dynamic List-Scheduling with Finite Resources. 140-144 - Rahul Razdan, Karl S. Brace, Michael D. Smith:
PRISC Software Acceleration Techniques. 145-149 - Sissades Tongsima, Nelson L. Passos, Edwin Hsing-Mean Sha:
Communication Sensitive Rotation Scheduling. 150-153
Timing Analysis
- Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen:
Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays. 156-159 - Rafael Peset Llopis, Lluís Ribas
Short Destabilizing Paths in Timing Verification. 160-163 - Xuguang Zhang, Ramalingam Sridhar:
Synchronization of Wave-Pipelined Circuits. 164-167
Field Programmable Systems
- Scott Hauck, Gaetano Borriello, Carl Ebeling:
Mesh Routing Topologies for Multi-FPGA Systems. 170-177 - Naohisa Ohta, Hiroshi Nakada, Kazuhisa Yamada, Akihiro Tsutsui, Toshiaki Miyazaki:
PROTEUS: Programmable Hardware for Telecommunication Systems. 178-183 - Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke:
Area & Time Limitations of FPGA-based Virtual Hardware. 184-189
Microprocessor Architecture
- John M. Borkenhagen, Glen H. Handlogten, John D. Irish, Sheldon B. Levenstein:
AS/400TM 64-bit PowerPCTM-Compatible Processor Implementaiton. 192-196 - Mike Gruver, Nghia Phan, Tony Aipperspach, Scott Hilker, Jerry Bartley:
AS/400 PowerPCTM Compatible Semi-Custom Technology. 197-202 - Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata:
A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface. 203-210
Asynchronous Circuit Design
- Ruchir Puri, Jun Gu:
Area Efficient Synthesis of Asynchronous Interface Circuits. 212-216 - Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods:
The Design and Evaluation of an Asynchronous Microprocessor. 217-220 - Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella:
Performance Analysis and Optimization of Asynchronous Circuits. 221-224
State-Based Formal Verification
- Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger:
Automatic Verification of Refinement. 225-229 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Efficient State Space Pruning in Symbolic Backward Traversal. 230-235 - Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. 236-239
Sequential Logic Synthesis
- Ellen Sentovich, Robert K. Brayton:
An Exact Optimization of Two-Level Acyclic Sequential Circuits. 242-249 - Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
State Assignment for Power and Area Minimization. 250-254 - Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton:
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. 255-261
Computer-Aided Embedded System Design
- M. Esen Tuna, Steven D. Johnson, Robert G. Burger:
Continuations in Hardware-Software Codesign. 264-269 - Michael Kozuch, Andrew Wolfe:
Compression of Embedded System Programs. 270-277 - Stefano Antoniazzi, Alessandro Balboni, William Fornaciari
HW/SW Codesign for Embedded Telecom Systems. 278-281
Bist/Testability Analysis
- Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
A Signature Analyzer for Analog and Mixed-signal Circuits. 284-287 - Amitava Majumdar:
WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing. 288-291 - Dimitrios Kagaris, Spyros Tragoudas:
A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators. 292-295
Architectural Building Blocks
- Z. Guan, P. Thomson, A. E. A. Almaini:
A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter. 298-301 - Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham:
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. 302-305 - Denis Archambaud, Pascal Faudemay:
An Arbitration Tree Adapted to Object Oriented Associative Memories. 306-310 - Pong P. Chu, Ramana Gottipati:
Write Buffer Design for On-Chip Cache. 311-316
Applications of High-Level Synthesis
- Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis for low Power. 318-322 - Laurence Goodby, Alex Orailoglu, Paul M. Chau:
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs. 323-326 - Sergei Sokolov, Ramesh Karri
Allocation and Binding During Fault-Secure Microarchitecture Synthesis. 327-330 - Karin Högstedt, Alex Orailoglu:
Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures. 331-334
Superscalar Processor Performance
- E. L. Hannon, Frank P. O'Connell, L. J. Shieh:
POWER2 Architecture and Performance. 336-339 - Katherine E. Stewart, Steven W. White:
The Effects of Compiler Options on Application Performance. 340-343 - S. Surya, Pradip Bose, Jacob A. Abraham:
Architectural Performance Verification: PowerPCTM Processors. 344-347
Test Generation
- R. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus:
Testability Analysis for Test Generation in Synchronous Sequential Circuits. 350-353 - Sanghyeon Baeg, William A. Rogers:
A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. 354-358 - Sungho Kang, Wai-On Law, Bill Underwood:
Path-Delay Fault Simulation for a Standard Scan Design Methodology. 359-362 - Sandip Kundu:
Multifault Testable Circuits Based on Binary Parity Diagrams. 363-366
System Technology
- Kevin Covey, Sandra Murdock, Thomas R. Shiple:
Two-phase Logic Design by Hardware Flowcharts. 368-380 - Shangzhi Sun, David Hung-Chang Du, Yaun-Chung Hsu, Hsi-Chuan Chen:
On Valid Clocking for Combinational Circuits. 381-384 - Hungse Cha, Janak H. Patel:
Latch Design for Transient Pulse Tolerance. 385-388
Timing Analysis and Optimization
- Robert E. Mains, Thomas A. Mosher, Lukas P. P. P. van Ginneken, Robert F. Damiano:
Timing Verification and Optimization for the PowerPCTM Processor Family. 390-393 - Yao-Ping Chen, D. F. Wong
On Retiming for FPGA Logic Module Minimization. 394-397 - Samir Lejmi, Bozena Kaminska, Edouard Wagneur:
Retiming for the Global Optimization of Synchronous Sequential Circuits. 398-403
PowerPC Alliance
- Charles P. Roth, Ricky Lewelling, Timothy B. Brodnax:
The PowerPCTM 604 Microprocessor Design Methodology. 404-408 - Michael J. Garcia, Brian K. Reynolds:
Single Chip PCI Bridge and Memory Controller for PowerPCTM Microprocessors. 409-412 - M. Armstead, Michael Cogswell, S. Halverson, T. Musta:
PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC Engine. 413-418
Embedded System Design Examples
- Jack P. F. Glas, Sándor E. Skolnik:
Fourier Transform based DS/FH Spread Spectrum Receiver. 420-423 - D. R. Woodward, D. C. Levy, R. G. Harley:
An FPGA based Configurable I/O System for AC Drive Controllers. 424-427 - Jörg Wilberg, Raul Camposano, Ursula Westerholz, Uwe Steinhausen:
Design of an Embedded Video Compression System - A Quantitative Approach. 428-431
Asynchronous Circuit Synthesis
- Steven M. Nowick, Bill Coates:
UCLOCK: Automated Design of High-Peformance Unclocked State Machines. 434-441 - Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand:
Peephole Optimization of Asynchronous Macromodule Networks. 442-446 - Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan:
Initialization Isuues in the Synthesis of Asynchronous Circuits. 447-452
Industrial Applications of Formal Methods
- Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen:
Architectural Verification of Processors Using Symbolic Instruction Graphs. 454-459 - Mark Genoe, Luc J. M. Claesen, Hugo De Man:
A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis. 460-463 - Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet:
The Structured Logic CAD Suite Used on the DPS7000 System. 464-467
Field Programmable Gate Array Architectures
- Faisal Haq, Samiha Mourad:
Optimal Logic Blocks for FPGAs, using Factorial Design Techniques. 470-474 - Aditya A. Aggarwal, David M. Lewis:
Routing Architectures for Hierarchical Field Programmable Gate Arrays. 475-478 - Jason L. Kelly, Peter A. Ivey:
Defect Tolerant SRAM Based FPGAs. 479-482
Software Testing
- Anneliese von Mayrhauser, Richard T. Mraz, Jeff Walls, Pete Ocken:
Domain Based Testing: Increasing Test Case Reuse. 484-491 - Raghu V. Hudli, Curtis L. Hoskins, Anand V. Hudli:
Software Metrics for Object-Oriented Designs. 492-495
Computer Arithmetic
- Luis A. Montalvo, Alain Guyot:
Combinational Digit-Set Converters for Hybrid Radix-4 Arithmetic. 498-503 - Kiyoung Choi, KiJong Lee, Jun-Woo Kang:
A Self-Timed Divider Using RSD Number System. 504-507 - Stanislaw J. Piestrak:
Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem. 508-511
Techniques Used in Production Logic Synthesis Systems
- Michael Quayle, ChiLai Huang:
Complex Operator Synthesis. 514-517 - Daniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm:
In the Driver's Seat of BooleDozer. 518-521 - Dileep Kumar, Bob Erickson:
ASOP: Arithmetic Sum-of-Products Generator. 522-526 - Hitomi Sato, Michihiro Yamazaki, Masahiro Fujita:
YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. 527-530
Embedded Systems Plenary
- Peter Thoma:
Future Needs for Automotive Electronics. 532-539
Special Purpose VLSI Architectures
- N. Ranganathan, Satish Venugopal:
A VLSI Chip for Template Matching. 542-545 - Glen Sunada, Jain Jin, Matt Berzins, Tom Chen:
COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. 546-550 - Dan Picker, Michael B. Bendak, Ronald D. Fellman:
A VLSI Priority Packet Queue with Overwrite and Inheritance. 551-555
High Speed Interconnect Analysis
- Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage:
Domain Characterization of Transmission Line Models for Efficient Simulation. 558-562 - Hong Liu, Fung-Yuel Chang, Omar Wing:
Transient Analysis of VLSI Interconnects with Arbitrary Initial Distributions and Nonlinear Terminations. 563-566 - Ali El-Zein, Monjurul Haque, Salim Chowdhury:
Simulating Uniform Lossy Lines by the Time-Domain Modal Analysis. 567-570
Scheduling and Allocation in High-Level Synthesis
- Mehmet Emin Dalkiliç, Vijay Pitchumani:
A Multi-Schedule Approach to High-Level Synthesis. 572-575 - Alok Sharma, Rajiv Jain:
Register Estimation from Behavioral Specifications. 576-580 - Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji:
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. 581-586 - Baher Haroun, Behzard Sajjadi:
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. 587-589
MCM Applications and Design Methodologies
- Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai:
Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules. 594-598 - James Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald:
Differential Routing of MCMs - CIF: The Ideal Bifurcation Medium. 599-603 - Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia:
Improved Techniques for MCM Layer Assignment. 604-607 - Atul Garg, T.-L. Sham
Thermal Design of an Advanced Multichip Module for a RISC Processor. 608-611
CMOS Circuit Techniques
- Razak Hossain, Menghui Zheng, Alexander Albicki:
Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering. 614-617 - Horng-Dar Lin, Ran-Hong Yan, Douglas Yu:
Improving CMOS Speed at Low Supply Voltages. 618-621 - Santanu Dutta, Wayne H. Wolf:
Asymptotic Limits of Video Signal Processing Architectures. 622-625 - Hans Lindkvist, Per Andersson:
Techniques for Fast CMOS-based Conditional Sum Adders. 626-635
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