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23rd FPL 2013: Porto, Portugal
- 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013. IEEE 2013, ISBN 978-1-4799-0004-6
- Ali Azarian
:
Pipelining computing stages in configurable multicore architectures. 1-2 - Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele:
Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS. 1-8 - Marco Alexandre Cravo Gomes
Magnitude modulation on reconfigurable computing devices. 1-4 - Janet Wyngaard
Towards a many-core architecture for HPC. 1-4 - Viktor Fischer, Florent Bernard, Patrick Haddad:
An open-source multi-FPGA modular system for fair benchmarking of True Random Number Generators. 1-4 - Pavel Zemcík
High performance architecture for object detection in streamed videos. 1-4 - Karel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS. 1-8 - Ondrej Sychrovsky, Martin Matousek, Radim Sára
FPGA-accelerated sliding window classifier with structured features. 1-4 - Andrew Love, Wenwei Zha, Peter Athanas:
In pursuit of instant gratification for FPGA design. 1-8 - Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). 1-4 - Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. 1 - Gabriel L. Nazar, Leonardo P. Santos
Accelerated FPGA repair through shifted scrubbing. 1-6 - Antonio de la Piedra
Compact implementation of CCM and GCM modes of AES using DSP blocks. 1-4 - Surendra Guntur, Feike Jansen, Jan Hoogerbrugge, Lotfi Abkari, Eric Vos:
Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation. 1-4 - Thilan Ganegedara, Viktor K. Prasanna:
A high-performance IPV6 lookup engine on FPGA. 1-4 - Yun Rock Qu, Viktor K. Prasanna:
Fast dynamically updatable packet classifier on FPGA. 1-4 - Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
A spiking neural network on a portable FPGA tablet. 1 - Felix Winterstein, Samuel Bayliss, George A. Constantinides:
FPGA-based K-means clustering using tree-based data structures. 1-6 - Kalin Ovtcharov, Ilian Tili, J. Gregory Steffan:
TILT: A multithreaded VLIW soft processor family. 1-4 - Yi Wang
FPGA based Rekeying for cryptographic key management in Storage Area Network. 1-6 - Susana Eiroa
FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash family. 1-4 - Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuyuki Ozaki, Hideharu Amano:
A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA. 1-4 - Ediz Cetin
Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. 1-4 - Anja Niedermeier, Jan Kuper, Gerard J. M. Smit:
A dataflow-inspired CGRA for streaming applications. 1-2 - Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
Managing the FPGA memory wall: Custom computing or vector processing? 1-6 - Jonathan Woodruff
A 64-bit MIPS processor running freebsd on a portable FPGA tablet. 1 - Yuan Yao, Zhongyong Lu, Qingsong Shi, Wenzhi Chen:
FPGA based hardware-software co-designed dynamic binary translation system. 1-4 - Martin Langhammer, Bogdan Pasca
Efficient floating-point polynomial evaluation on FPGAS. 1-6 - Oliver Knodel
Integration of a multi-FPGA system in a common cluster environment. 1-2 - Luís Gomes, Filipe Moutinho
IOPT-tools - A Web based tool framework for embedded systems controller development using Petri nets. 1 - Kiran Kumar Matam, Hoang Le, Viktor K. Prasanna:
Energy efficient architecture for matrix multiplication on FPGAs. 1-4 - Luiz G. A. Martins
Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimation. 1-2 - Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers:
A flexible hash table design for 10GBPS key-value stores on FPGAS. 1-8 - Daniel Kliem, Sven-Ole Voigt:
An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs. 1-4 - Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung
FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. 1-4 - Arvind Arasu, Ken Eguro, Raghav Kaushik, Donald Kossmann, Ravi Ramamurthy, Ramarathnam Venkatesan:
A secure coprocessor for database applications. 1-8 - Safeen Huda, Jason Helge Anderson, Hirotaka Tamura:
Charge recycling for power reduction in FPGA interconnect. 1-8 - Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Automated synthesis of FPGA-based heterogeneous interconnect topologies. 1-8 - Georgios Tzimpragos
A low-complexity implementation of QC-LDPC encoder in reconfigurable logic. 1-4 - Bruno da Silva
Comparing and combining GPU and FPGA accelerators in an image processing context. 1-4 - Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An automatic FPGA design and implementation framework. 1-4 - Tim Todman, Wayne Luk:
Runtime assertions and exceptions for streaming systems. 1-4 - Dirk Koch, Christian Beckhoff, Guy G. F. Lemieux:
An efficient FPGA overlay for portable custom instruction set extensions. 1-8 - Rodrigo Bernardo, Arley H. Salvador, Eduardo Mobilon, Luis R. Monte, Stephane Boisclair, Avrum Warshawsky:
Design and FPGA implementation of a 100 Gbit/s optical transport network processor. 1-4 - Ruediger Willenberg, Paul Chow:
Simulation-based HW/SW co-debugging for field-programmable systems-on-chip. 1-8 - Kenta Fujinami, Yoshiki Yamaguchi, Akira Sugiura, Yuetsu Kodama:
The study of three-dimensional multiphase-flow simulator. 1-4 - Dajung Lee, Pingfan Meng, Matthew Jacobsen, Henry Tse, Dino Di Carlo, Ryan Kastner
A hardware accelerated approach for imaging flow cytometry. 1-8 - David May, Walter Stechele:
A resource-efficient probabilistic fault simulator. 1-4 - Angel Gallego, Javier Mora
A self-adaptive image processing application based on evolvable and scalable hardware. 1 - Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang:
Timing-constrained minimum area/power FPGA memory mapping. 1-4 - Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio. 1-4 - Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz:
Titan: Enabling large and complex benchmarks in academic CAD. 1-8 - Christian Beckhoff, Alexander Wold, Anders Fritzell, Dirk Koch, Jim Tørresen:
Building partial systems with GoAhead. 1 - Ricardo S. Ferreira, Luciana Rocha, André G. Santos, José Augusto Miranda Nacif, Stephan Wong, Luigi Carro:
A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS. 1-8 - Ricardo Nobre
Identifying sequences of optimizations for HW/SW compilation. 1-2 - Christian Pilato
Bambu: A modular framework for the high level synthesis of memory-intensive applications. 1-4 - Tobias Strauch:
Timing driven RTL-to-RTL partitioner for multi-FPGA systems. 1-4 - Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer:
Optimizing under abstraction: Using prefetching to improve FPGA performance. 1-8 - Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito:
Image recognition operation on a dynamically reconfigurable vison architecture. 1-4 - Chin Hau Hoo, Yajun Ha, Akash Kumar
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. 1-4 - Panagiotis Papantonakis, Dionisios N. Pnevmatikatos
Fast, FPGA-based Rainbow Table creation for attacking encrypted mobile communications. 1-6 - Chuan Cheng, Christos-Savvas Bouganis
Accelerating Random Forest training process using FPGA. 1-7 - Erdem Ozcan, Yusuf Adibelli, Ilker Hamzaoglu:
A high performance deblocking filter hardware for High Efficiency Video Coding. 1-4 - Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado:
FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source. 1-6 - Stuart Byma, J. Gregory Steffan, Paul Chow:
NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract. 1 - Hussam Amrouch
Analyzing the thermal hotspots in FPGA-based embedded systems. 1-4 - Travis Haroldsen, Brent E. Nelson, Brad White:
Rapid FPGA design prototyping through preservation of system logic: A case study. 1-7 - Ruediger Willenberg, Paul Chow:
SimXMD: Simulation-based HW/SW co-debugging. 1 - Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf
Multiple constant multiplication with ternary adders. 1-8 - Shakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk
MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis. 1 - Wilson José
Analysis of matrix multiplication on high density Virtex-7 FPGA. 1-4 - Miguel Morales-Sandoval
Area/performance evaluation of digit-digit GF(2K) multipliers on FPGAS. 1-6 - Sambit Kumar Shukla, Yang Yang, Laxmi N. Bhuyan, Philip Brisk
Shared memory heterogeneous computation on PCIe-supported platforms. 1-4 - Louis Woods, Zsolt István, Gustavo Alonso:
Hybrid FPGA-accelerated SQL query processing. 1 - Stefano Di Carlo
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS. 1-4 - Chun Zhu, Jian Wang, Jinmei Lai:
A novel net-partition-based multithread FPGA routing method. 1-4 - Parthasarathy M. B. Rao, Abdulazim Amouri, Saman Kiamehr, Mehdi Baradaran Tahoori:
Altering LUT configuration for wear-out mitigation of FPGA-mapped designs. 1-8 - François Philipp, Manfred Glesner:
An event-based middleware for the remote management of runtime hardware reconfiguration. 1-4 - Nikolaos Kavvadias, Kostas Masselos:
The HercuLeS high-level synthesis environment. 1 - Stefano Di Carlo
FEMIP: A high performance FPGA-based features extractor & matcher for space applications. 1-4 - Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz:
From Quartus to VPR: Converting HDL to BLIF with the Titan flow. 1 - Jirí Matousek, Martin Skacan, Jan Korenek:
Memory efficient IP lookup in 100 GBPS networks. 1-8 - Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang
Accelerating solvers for global atmospheric equations through mixed-precision data flow engine. 1-6 - Sheng Wei, Jason Xin Zheng, Miodrag Potkonjak:
Aging-based leakage energy reduction in FPGAs. 1-4 - Aaron Severance, Guy G. F. Lemieux:
TputCache: High-frequency, multi-way cache for high-throughput FPGA applications. 1-6 - Victor Silva, Jorge R. Fernandes
A reconfigurable computing architecture using magnetic tunneling junction memories. 1-2 - Stefanie Castillo
SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems. 1-4 - Matthew Jacobsen, Ryan Kastner
RIFFA 2.0: A reusable integration framework for FPGA accelerators. 1-8 - Wei Ting Loke, Wenfeng Zhao, Yajun Ha:
Criticality-based routing for FPGAS with reverse body bias switch box architectures. 1-6 - Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. 1-4 - Rodolfo Redlich, Miguel E. Figueroa
A digital architecture for real-time nonuniformity correction of infrared focal-plane arrays. 1-4 - Mohamed S. Abdelfattah, Vaughn Betz:
The power of communication: Energy-efficient NOCS for FPGAS. 1-8 - Myron King, Asif Khan, Abhinav Agarwal, Oriol Arcas
Generating infrastructure for FPGA-accelerated applications. 1-6 - Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow And-Inverter Cones. 1-4 - Zhenyu Guan, Justin S. J. Wong
A variation-adaptive retiming method exploiting reconfigurability. 1-4 - Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS. 1-7 - Jochen Vandorpe, Jo Vliegen, Ruben Smeets, Nele Mentens, Milos Drutarovský, Michal Varchola, Kerstin Lemke-Rust, Paul Plöger, Peter Samarin, Dirk Koch, Yngve Hafting, Jim Tørresen:
Remote FPGA design through eDiViDe - European Digital Virtual Design Lab. 1 - Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A packet classifier using LUT cascades based on EVMDDS (k). 1-6 - Harry Sidiropoulos, Peter Figuli, Kostas Siozios
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization. 1-4 - David B. Thomas, Hideharu Amano:
A fully pipelined FPGA architecture for stochastic simulation of chemical systems. 1-7 - Shweta Jain-Mendon, Ron Sass:
Performance evaluation of Sparse Matrix-Matrix Multiplication. 1-4 - Patrick Lehmann, Thomas Frank, Oliver Knodel
Weasel: A platform-independent streaming-optimized SATA controller. 1-4 - Filipe Moutinho
Distributed embedded systems design using Petri nets. 1-2 - Giovanni Mariani, Vlad Mihai Sima
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction. 1-8 - Di Wu, Kaveh Aasaraai, Andreas Moshovos:
Low-cost, high-performance branch predictors for soft processors. 1-6 - Fredrik Brosser, Hui Yan Cheah, Suhaib A. Fahmy
Iterative floating point computation using FPGA DSP blocks. 1-6 - Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Impact of hard macro size on FPGA clock rate and place/route time. 1-6 - José M. Leitão, José A. Germano
Scalable and high throughput biosensing platform. 1-6 - Nicolas Brunie
Arithmetic core generation using bit heaps. 1-8 - Abdulazim Amouri, Mehdi Baradaran Tahoori:
Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview). 1-2 - Fengbo Ren
A single-precision compressive sensing signal reconstruction engine on FPGAs. 1-4 - Anup Das
Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation. 1-8 - Raphael Polig, Kubilay Atasu
Token-based dictionary pattern matching for text analytics. 1-6 - Alexander Wold, Jim Tørresen, Andreas Agne:
Generation of multi-core systems from multithreaded software. 1-4 - Ren Chen, Hoang Le, Viktor K. Prasanna:
Energy efficient parameterized FFT architecture. 1-7 - Sebastian Manz, Jano Gebelein, Andrei Oancea, Heiko Engel, Udo Kebschull:
Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller. 1-6 - Shuai Xie, Yibin Li, Zhiping Jia, Lei Ju:
Binarization based implementation for real-time human detection. 1-4 - Kubilay Atasu
Hardware-accelerated regular expression matching for high-throughput text analytics. 1-7 - Davor Capalija, Tarek S. Abdelrahman:
A high-performance overlay architecture for pipelined execution of data flow graphs. 1-8 - Ce Guo, Wayne Luk:
Accelerating maximum likelihood estimation for Hawkes point processes. 1-6 - Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo:
Dynamic branch prediction for high-level synthesis. 1-6 - Kentaro Sano, Ryo Ito, Hayato Suzuki, Yoshiaki Kono:
Parallel and scalable custom computing for real-time fluid simulation on a cluster node with four tightly-coupled FPGAs. 1 - Charles Chiasson, Vaughn Betz:
Should FPGAS abandon the pass-gate? 1-8 - Yi-Chung Chen, Wei Zhang
A hardware security scheme for RRAM-based FPGA. 1-4 - Marco Forconesi, Gustavo Sutter
Accurate and flexible flow-based monitoring for high-speed networks. 1-4 - Pavel Zemcík
High performance FPGA object detector: Hardware prototype. 1 - Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Defect-robust FPGA architectures for intellectual property cores in system LSI. 1-7 - Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk:
A scalable design approach for stencil computation on reconfigurable clusters. 1-4 - Xiaoyan Cheng, Tao Yin, Qisong Wu, Yiping Jia, Haigang Yang:
A CMOS Field Programmable Analog Array for intelligent sensory application. 1-4 - Carlos Leong, Jorge Semião
Aging monitoring with local sensors in FPGA-based designs. 1-4 - Meng Yang, Jinmei Lai, Jiarong Tong:
Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD. 1-4 - Rinse Wester, Jan Kuper:
A space/time tradeoff methodology using higher-order functions. 1-2 - Oriol Font-Bach
Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems. 1-4 - Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow
High-level synthesis with behavioral level multi-cycle path analysis. 1-8 - Petr Pfeifer
On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA). 1-4 - Andrew Love, Peter Athanas:
Rapid modular assembly of Xilinx FPGA designs. 1 - Shane T. Fleming, David B. Thomas:
FPGA based control for real time systems. 1-2 - Dustin Richmond
A FPGA design for high speed feature extraction from a compressed measurement stream. 1-8
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