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29th FPL 2019: Barcelona, Spain
- Ioannis Sourdis, Christos-Savvas Bouganis, Carlos Álvarez, Leonel Antonio Toledo Díaz, Pedro Valero-Lara, Xavier Martorell:
29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019. IEEE 2019, ISBN 978-1-7281-4884-7
Session M1 - FPGA Architectures & Technology
- Ibrahim Ahmed, Linda L. Shen, Vaughn Betz:
Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage. 1-8 - Xibo Sun, Hao Zhou, Lingli Wang:
Bent Routing Pattern for FPGA. 9-16 - Mark Wijtvliet, Jos Huisken
, Luc Waeijen, Henk Corporaal:
Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency. 17-23 - Leo Liu, Nachiket Kapre:
Timing-Aware Routing in the RapidWright Framework. 24-30 - Stefan Nikolic
Finding a Needle in the Haystack of Hardened Interconnect Patterns. 31-37 - Konstantinos Maragos, Endri Taka, George Lentaris, Ioannis Stratakos, Dimitrios Soudris:
Analysis of Performance Variation in 16nm FinFET FPGA Devices. 38-44 - Ilias Giechaskiel
Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAs. 45-50
Session A1 - Application Acceleration
- Mrunal Patel, Shenghsun Cho, Michael Ferdman, Peter A. Milder
Runtime-Programmable Pipelines for Model Checkers on FPGAs. 51-58 - Kosuke Tatsumura
FPGA-Based Simulated Bifurcation Machine. 59-66 - Xinyu Chen, Ronak Bajaj, Yao Chen
On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs. 67-73 - Konstantina Koliogeorgi, Nils Voss, Sotiria Fytraki, Sotirios Xydis, Georgi Gaydadjiev
Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation Sequencing. 74-80 - Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. 81-87 - Petros Toupas
Accelerating Physics Engine Components with Embedded FPGAs. 88-94 - Nikolaos Kyparissas
An FPGA-Based Architecture to Simulate Cellular Automata with Large Neighborhoods in Real Time. 95-99 - Philippos Papaphilippou
Accelerating the Merge Phase of Sort-Merge Join. 100-105
Session A2 - Vision & Arithmetic
- Yohann Uguen, Luc Forget, Florent de Dinechin:
Evaluating the Hardware Cost of the Posit Number System. 106-113 - Martin Langhammer, Bogdan Pasca
Extracting INT8 Multipliers from INT18 Multipliers. 114-120 - Lester Kalms, Maximilian Hajduk, Diana Göhringer
Efficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA Implementation. 121-128 - Marie Nguyen, Robert Tamburo, Srinivasa G. Narasimhan
Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications. 129-135
Session M2 - Accelerated Machine Learning
- Di Wu, Yu Zhang, Xijie Jia
A High-Performance CNN Processor Based on FPGA for MobileNets. 136-143 - Rachit Rajat, Hanqing Zeng, Viktor K. Prasanna:
A Flexible Design Automation Tool for Accelerating Quantized Spectral CNNs. 144-150 - Xiaoyu Yu, Jianlin Gao, Yuwei Wang, Jie Miao, Ephrem Wu
A Data-Center FPGA Acceleration Platform for Convolutional Neural Networks. 151-158 - Glenn G. Ko, Yuji Chai, Rob A. Rutenbar
Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling. 159-165 - Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao
Automatic Compiler Based FPGA Accelerator for CNN Training. 166-172 - Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. 173-179 - Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato:
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. 180-186 - Shuanglong Liu, Wayne Luk:
Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs. 187-193
Session A3 - Security
- George Provelengios, Daniel E. Holcomb, Russell Tessier:
Characterizing Power Distribution Attacks in Multi-User FPGA Environments. 194-201 - Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey. 202-210 - Rashmi S. Agrawal, Lake Bu, Alan Ehret, Michel A. Kinsy:
Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives. 211-217 - Adriaan Peetermans, Vladimir Rozic, Ingrid Verbauwhede
A Highly-Portable True Random Number Generator Based on Coherent Sampling. 218-224 - Farnoud Farahmand, Duc Tri Nguyen, Viet Ba Dang, Ahmed Ferozpuri, Kris Gaj:
Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies. 225-231 - Lenos Ioannou
Network Intrusion Detection Using Neural Networks on FPGA SoCs. 232-238 - Victor Arribas:
Beyond the Limits: SHA-3 in Just 49 Slices. 239-245 - Andrew Maclellan, Lewis D. McLaughlin, Louise Crockett, Robert W. Stewart:
FPGA Accelerated Deep Learning Radio Modulation Classification Using MATLAB System Objects & PYNQ. 246-247
PhD Forum
- Ricardo Tapiador-Morales, Antonio Rios-Navarro, Juan Pedro Dominguez-Morales, Daniel Gutierrez-Galan, Alejandro Linares-Barranco:
Spiking Row-by-Row FPGA Multi-Kernel and Multi-Layer Convolution Processor. 248-249 - Paolo Cretaro:
A Distributed Model of Computation for Reconfigurable Devices Based on a Streaming Architecture. 250-251 - Lenos Ioannou
Neural Network Overlay Using FPGA DSP Blocks. 252-253
Session M3 - Memory, Network and Streams
- Mikhail Asiatici, Paolo Ienne:
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. 254-262 - Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Sander Stuijk
NARMADA: Near-Memory Horizontal Diffusion Accelerator for Scalable Stencil Computations. 263-269 - Johan Peltenburg, Jeroen van Straten
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow. 270-277 - Grigorios Chrysos, Odysseas Papapetrou, Dionisios N. Pnevmatikatos
Data Stream Statistics Over Sliding Windows: How to Summarize 150 Million Updates Per Second on a Single Node. 278-285 - Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo:
Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. 286-292 - Burkhard Ringlein
System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration. 293-300 - Seungwon Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong
Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device. 301-306 - Roberto Sierra, Filippo Mangani, Carlos Carreras
High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. 307-313 - Nicholas V. Giamblanco, Jason Helge Anderson:
A Dynamic Memory Allocation Library for High-Level Synthesis. 314-320 - Yuchen Ren, Zhijian Liao, Xiaozhong Shi, Jinyu Xie, Yunhui Qiu, Hankun Lv, Wenbo Yin, Lingli Wang, Bowei Yu, Hua Chen, Xianjun He:
A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform. 321-325
Session A4 - Architectures & Technology for Machine Learning
- Rui Ma, Derek Chiou, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu:
Specializing FGPU for Persistent Deep Learning. 326-333 - Abeer Alhyari
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement. 334-341 - Ananda Samajdar, Tushar Garg, Tushar Krishna, Nachiket Kapre:
Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. 342-349 - Mário P. Véstias
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. 350-353 - Duvindu Piyasena, Rukshan Wickramasinghe, Debdeep Paul, Siew-Kei Lam, Meiqing Wu:
Reducing Dynamic Power in Streaming CNN Hardware Accelerators by Exploiting Computational Redundancies. 354-359 - Stefan Hadjis, Kunle Olukotun
TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep Neural Networks. 360-366
Session A5 - Tools & Methods
- Xifan Tang, Edouard Giacomin
OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. 367-374 - Matthew Naylor, Simon W. Moore, David B. Thomas:
Tinsel: A Manythread Overlay for FPGA Clusters. 375-383 - Robert Hale, Brad L. Hutchings:
Preallocating Resources for Distributed Memory Based FPGA Debug. 384-390 - Hossein Omidian, Guy G. F. Lemieux:
Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs. 391-396 - Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarrao
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design. 397-403 - Shounak Dhar, Love Singhal, Mahesh A. Iyer
FPGA Accelerated FPGA Placement. 404-410
Demos
- Takuya Kojima
Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA. 411-412 - Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara:
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. 413-414 - Lucas Kuhring, Zsolt István:
Storing Parquet Tile by Tile: Application-Aware Storage with Deduplication. 415-416 - Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano:
Demonstration of Flow-in-Cloud: A Multi-FPGA System. 417-418 - Bruno da Silva
Demonstration of a Multimode SoC FPGA-Based Acoustic Camera. 419-420 - Younmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Hyesoon Kim:
Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs. 421 - Yasuhiro Nitta, Sou Tamura, Hideki Takase:
ZytleBot: FPGA Integrated Development Platform for ROS Based Autonomous Mobile Robot. 422-423 - Akira Jinguji, Youki Sada, Hiroki Nakahara:
Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA. 424-425 - Thomas Preußer, Alexander Weiss
The CEDARtools Platform - Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns. 426-427 - Adriaan Peetermans, Milos Grujic
A Self-Calibrating True Random Number Generator. 428 - Anuj Vaishnav, Khoa Dang Pham, Kristiyan Manev, Dirk Koch:
The FOS (FPGA Operating System) Demo. 429
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