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DFT 2001: San Francisco, CA, USA
- 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings. IEEE Computer Society 2001, ISBN 0-7695-1203-8
Wafer Scale
- Israel Koren, Zahava Koren, Glenn H. Chapman:
Advanced Fault-Tolerance Techniques for a Color Digital Camera-on-a-Chip. 3-10 - S. K. Tewksbury:
Challenges Facing Practical DFT for MEMS. 11-17 - Yves Audet, Glenn H. Chapman:
Design of a Self-Correcting Active Pixel Sensor. 18-
Yield
- Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. 29-38 - Neil Harrison:
A Simple via Duplication Tool for Yield Enhancement. 39-47 - Tianxu Zhao, Yue Hao, Peijun Ma, Taifeng Chen:
Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model. 48-
Dependable Design
- Hans A. R. Manhaeve, Stefaan Kerckenaere:
An On-Chip Detection Circuit for the Verification of IC Supply Connections. 57-65 - Parag K. Lala, Alvernon Walker:
On-Line Error Detectable Carry-Free Adder Design. 66-71 - Shugang Wei, Kensuke Shimizu:
Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System. 72-77 - Tat Ngai, Earl E. Swartzlander Jr., Chen He:
Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. 78-83 - Régis Leveugle, R. Cercueil:
High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. 84-
Testing Techniques 1
- J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone:
Embedded Core Testing Using Broadcast Test Architecture. 95-103 - Janusz Sosnowski
:
Analyzing BIST Robustness. 104-109 - Ondrej Novák, Jiri Nosek:
Test Pattern Decompression Using a Scan Chain. 110-115 - Xiaowei Li, Huawei Li, Yinghua Min:
Reducing Power Dissipation during At-Speed Test Application. 116-
Fault-Tolerance in Arrays
- Shu-Yi Yu, Edward J. McCluskey:
Permanent Fault Repair for FPGAs with Limited Redundant Area. 125-133 - Itsuo Takanami:
Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement. 134-142 - Nobuo Tsuda:
ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication . 143-148 - John Marty Emmert, Jason A. Cheatham:
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . 149-
Fault Detection
- Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi:
Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays. 161-169 - Cristiana Bolchini, Fabio Salice:
A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. 170-175 - Seok-Bum Ko
Efficient Parity Prediction in FPGA. 176-181 - Nahmsuk Oh, Edward J. McCluskey:
Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. 182-
FPGA Based Applications
- Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi:
A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application. 191-199 - Kaijie Wu, Ramesh Karri
Idle Cycles Based Concurrent Error Detection of RC6 Encryption. 200-205 - Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey:
Fast Run-Time Fault Location in Dependable FPGA-Based Applications. 206-214 - Jayabrata Ghosh-Dastidar, Nur A. Touba:
Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. 215-220 - Xiaoling Sun, Jian Xu, Pieter M. Trouborst:
Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules. 221-
Fault Injection
- Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil:
Comparison and Application of Different VHDL-Based Fault Injection Techniques. 233-241 - Régis Leveugle:
A Low-Cost Hardware Approach to Dependability Validation of Ips. 242-249 - Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . 250-258 - Raoul Velazco, Régis Leveugle, Oscar Calvo:
Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. 259-
Testing Techniques 2
- Farzin Karimi, Fabrizio Lombardi:
Parallel Testing of Multi-port Static Random Access Memories for BIST. 271-279 - Paul Lee, Alfred Chen, Dilip Mathew:
A Speed-Dependent Approach for Delta IDDQ Implementation. 280-286 - Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada:
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. 287-
Error Correcting Codes
- Kazuteru Namba, Eiji Fujiwara:
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. 299-307 - Amir Kazéminéjad, Eric Belhaire:
Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications. 308-313 - Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro:
Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes. 314-
Mixed Signal Circuits
- Xiangdong Xuan, Abhijit Chatterjee:
Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier Effects. 323-328 - Alvernon Walker:
A Step Response Based Mixed-Signal BIST Approach . 329-337 - Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Analog BIST Generator for ADC Testing. 338-346 - Mandeep Singh, Israel Koren:
Reliability Enhancement of Analog-to-Digital Converters (ADCs). 347-
Defect Analysis
- Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak:
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. 357-365 - Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams:
Defect Analysis and a New Fault Model for Multi-port SRAMs. 366-374 - Mykola Blyzniuk, Irena Kazymyra
Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library. 375-383 - Witold A. Pleskacz, Dominik Kasprowicz
CMOS Standard Cells Characterization for Defect Based Testing. 384-
Self-Checking and Fail-Safe Circuits
- Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin
Survivable Self-Checking Sequential Circuits. 395-402 - Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. 403-411 - Eleftherios Kolonis, Michael Nicolaidis:
Fail-Safe Synchronization Circuit for Duplicated Systems. 412-417 - Andreas Steininger, Christoph Scherrer:
How to Tune the MTTF of a Fail-Silent System. 418-
Fault-Tolerant Techniques
- Ramesh Karri
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. 427-435 - Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui:
On Variable-Shift-Based Fault Compensation of Fuzzy Controllers. 436-444 - John Marty Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici:
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. 445-454 - Salvatore Pontarelli, Gian Carlo Cardarilli, A. Malvoni, Marco Ottavi
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology. 455-460 - Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey:
Performance Evaluation of Checksum-Based ABFT. 461-
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