The effects of the most likely clock faults has then been analyzed by means of electrical level simulations. Differently from what is generally implicitly ...

Starting from the analysis of real process data and considering, as a reference, an Intel microprocessor, we evaluate the fault models that better describe ...

Only a small percentage of fault models better describe the manufacturing defects that are most likely to affect signals of the clock distribution network ...

PDF | Starting from the analysis of real process data and considering, as a reference, an Intel microprocessor we evaluate the fault models that better.

This paper investigates the impact of faults affecting the clock distribution network of synchronous systems on manufacturing testing.

The effects of the most likely faults have been evaluated by electrical level simulations. We have found that, contrary to common assumptions, only a small ...

This paper proposes an on-chip detector for the on-line testing of faults affecting clock signals and making them change with incorrect duty-cycle.

Clock Distribution Networks refer to on-chip interconnect networks that deliver synchronizing signals across a chip to coordinate the flow of data, ...

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can.

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects ... System-on-Chip Oriented Fault-Tolerant Sequential Systems ...