An initial list of suspect configuration logic blocks (CLBs) and interconnects is generated using six-valued fault-free simulation and critical path tracing.

Abstract. Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior.

Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior.

Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior.

This paper presents a new approach for locating any multiple faulty look-up tables (LUTs) in a field programmable gate array (FPGA). This is a high resolution ...

This paper presents a new technique for detecting resistive open defects in FPGAs. This technique is based on the reconfigurability feature of FPGAs. Using this ...

Improving diagnostic resolution of delay faults in FPGAs by exploiting reconfigurability ... Adaptive techniques for improving delay fault diagnosis.

In order to achieve maximum diagnostic resolution, every pair of faults must be non-equivalent in at least one configuration. 7. Page 8. We will define fault ...

The purpose of FPGA testing in this work is to achieve reliable reconfiguration for a FPGA-based runtime reconfigurable system. A pre-configuration test is ...

A test configuration scheme and its associated test sequence able to test exhaustively the delay faults in all LUTs of a symmetrical FPGA are proposed.