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A-SSCC 2011: Jeju, South Korea
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2011, Jeju, South Korea, November 14-16, 2011. IEEE 2011, ISBN 978-1-4577-1784-0
- Youm Huh:
Future direction of power management in mobile devices. 1-4 - Toshiaki Masuhara:
Challenge of low voltage and low power IC toward sustainable future. 5-8 - Pilsoon Choi, Yongseok Yi, Kilsik Ha, Yun-Gu Lee, Chil-Youl Hacky Yang, Seyoung Shin, Byung-Ho Ahn, Sung-Chul Park, Hyun-Tae Gil, Scott Seongwook Lee, Joongsuk Park, Jaemoon Jo:
An 18ms-latency wireless high quality codec SoC for full HD streaming. 9-12 - Marcelo Yuffe, Omer Vikinski, Ziv Shmuely, Ernest Knoll, Tsvika Kurts:
The Second Generation Intel® Core™: A highly integrated high performance multi IA-core and processor graphics chip. 13-16 - Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki:
A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems. 17-20 - Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu:
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. 21-24 - Amir Amirkhany, Wendemagegnehu T. Beyene, Chris J. Madden, Aliazam Abbasfar, Dave Secker, Dan Oh, Mohammad Hekmat, Ralf Schmitt, Chuck Yuan:
On overcoming the limitations of single-ended signaling for graphics memory interfaces. 25-28 - Philip Amberg, Frankie Liu, Michael Dayringer, Jon K. Lexau, Dinesh Patil, Jonathan Gainsley, Hesam Fathi Moghadam, Elad Alon, Xuezhe Zheng, John E. Cunningham, Ashok V. Krishnamoorthy, Ron Ho:
Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS. 29-32 - Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting. 33-36 - Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa:
A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. 37-40 - Se-Won Wang, Young-Jin Woo, Sung-Ho Bae, Tae-Hwang Kong, Gyu-Ha Cho, Gyu-Hyeong Cho:
A high stability DC-DC Boost Converter with Ripple Current Control and capacitor-free LDOs for AMOLED display. 41-44 - Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang:
An asynchronous digitally-controlled switching converter with adaptive resolution and dynamic power saving to achieve higher than 93.5% efficiency between 5mA and 250mA load. 45-48 - Yuya Hirano, Yasuhiro Sugimoto:
A MOS current-mode boost DC-DC converter with the duty-ratio-independent frequency characteristics. 49-52 - Chun-Sheng Huang, Chen-Yu Wang, Jia-Hui Wang, Chien-Hung Tsai:
A fast-transient quasi-V2 switching buck regulator using AOT control. 53-56 - Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. 61-64 - Jon Guerber, Manideep Gande, Hariprasath Venkatram, Allen Waters, Un-Ku Moon:
A 10b Ternary SAR ADC with decision time quantization based redundancy. 65-68 - Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu:
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. 69-72 - Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. 73-76 - Ji-Yong Um, Jae-Hwan Kim, Jae-Yoon Sim, Hong-June Park:
Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC. 77-80 - Tao-Yao Chang, Chao-Shiun Wang, Chorng-Kuang Wang:
A low power W-band PLL with 17-mW in 65-nm CMOS technology. 81-84 - Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing. 85-88 - Shu-Wei Chu, Chorng-Kuang Wang:
An 85-GHz injection-locked frequency divider with current-reuse pre-amplifier technique. 89-92 - I-Ting Lee, Chiao-Hsing Wang, Shen-Iuan Liu:
3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS. 93-96 - Lei Wang, Yong-Zhong Xiong, Sanming Hu
A 0.13-μm HBT divide-by-6 injection-locked frequency divider. 97-100 - Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng:
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. 101-104 - Zhichao Tan, Roel Daamen, Aurelie Humbert, Kamran Souri, Youngcheol Chae, Youri V. Ponomarev, Michiel A. P. Pertijs:
A 1.8V 11μW CMOS smart humidity sensor for RFID sensing applications. 105-108 - Valentijn De Smedt
A 0.6V to 1.6V, 46μW voltage and temperature independent 48 MHz pulsed LC oscillator for RFID tags. 109-112 - Nele Reynders, Wim Dehaene:
A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques. 113-116 - Hossein Fariborzi, Fred Chen, Rhesa Nathanael, Jaeseok Jeon:
Design and demonstration of micro-electro-mechanical relay multipliers. 117-120 - Neena A. Gilda, Sheetal Patil, V. Seena, Sanjay Joshi, Viral Thaker, Sanket Thakur, Amaravati Anvesha, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao
Piezoresistive 6-MNA coated microcantilevers with signal conditioning circuits for electronic nose. 121-124 - Peter Chung-Yu Wu:
Medical electronics - A challenging research and industry frontier. 125-128 - Chris Toumazou, Pantelis Georgiou
Bio-inspired semiconductors for early detection and therapy. 129-132 - Bruce Andrew Doyle, Alvin Leng Sun Loke, Sanjeev K. Maheshwari, Charles Lin Wang, Dennis Michael Fischette, Jeffrey G. Cooper, Sanjeev K. Aggarwal, Tin Tin Wee, Chad O. Lackey, Harishkumar S. Kedarnath, Michael M. Oshima, Gerry R. Talbot, Emerson S. Fang:
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. 133-136 - I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A leakage-current-recycling phase-locked loop in 65nm CMOS technology. 137-140 - Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, Kiat Seng Yeo:
A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. 141-144 - Won-Joo Yun, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. 145-148 - Jonathan C. Leu, Vladimir Stojanovic:
Injection-locked clock receiver for monolithic optical link in 45nm SOI. 149-152 - Dae Young Lee
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits. 153-156 - Jong-Chern Lee, Sin-Hyun Jin, Dae-Suk Kim, Young Jun Ku, Chul Kim, Byung-Kwon Park, Hong-Gyeom Kim, Seong-Jun Ahn, Jaejin Lee, Sung-Joo Hong:
A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM. 157-160 - Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe:
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. 161-164 - Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano:
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme. 165-168 - Samkyu Won, Yujong Noh, Hyunchul Cho, Jeil Ryu, Sungwook Choi, Sungdae Choi, DuckJu Kim, Junseop Chung, Bong-Seok Han, Eui-Young Chung:
High-voltage wordline generator for low-power program operation in NAND flash memories. 169-172 - Bruce L. Bateman, Chang Hua Siau, Christophe J. Chevallier:
Low power cross-point memory architecture. 173-176 - Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro:
1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller. 177-180 - Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yoo:
A low energy crystal-less double-FSK transceiver for wireless body-area-network. 181-184 - Tianjia Sun, Xiang Xie, Guolin Li, Yingke Gu, Xiaomeng Li, Zhihua Wang:
An omnidirectional wireless power receiving IC with 93.6% efficiency CMOS rectifier and Skipping Booster for implantable bio-microsystems. 185-188 - Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee:
A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications. 189-192 - Chin-Lin Lee, Chih-Cheng Hsieh:
A 0.8V 64×64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications. 193-196 - Jason Yi Jun Tan, Xu Liu
A programmable muscle stimulator based on dual-slope charge balance. 197-200 - Kiichi Niitsu
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. 201-204 - Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. 205-208 - Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. 209-212 - Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara:
A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic. 213-216 - Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
An area effective forward/reverse body bias generator for within-die variability compensation. 217-220 - Kuo-Hsin Chen, Yen-Shun Hsu:
A 106dB PSRR direct battery connected reconfigurable class-AB/D speaker amplifier for hands-free/receiver 2-in-1 loudspeaker. 221-224 - Nan Lin, Fei Fang, Zhiliang Hong, Hao Fang:
A CMOS broadband precise programmable gain amplifier with bandwidth extension technique. 225-228 - Liang Feng, Yu Mao, Yuhua Cheng:
An efficient and stable power management circuit with high output energy for wireless powering capsule endoscopy. 229-232 - Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. 233-236 - Kosuke Isono, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 18.9-nA standby current comparator with adaptive bias current generator. 237-240 - Rong Wu, Johan H. Huijsing, Kofi A. A. Makinwa:
A 21-bit read-out IC employing dynamic element matching with 0.037% gain error. 241-244 - Navid Sarhangnejad, Rong Wu, Youngcheol Chae, Kofi A. A. Makinwa:
A continuous-time ΣΔ modulator with a Gm-C input stage, 120-dB CMRR and -87 dB THD. 245-248 - Xinpeng Xing, Maarten De Bock, Pieter Rombouts
A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS. 249-252 - Kei-Tee Tiew, Minkyu Je:
A 0.06-mm2 double-sampling single-OTA 2nd-order ΔΣ modulator in 0.18-μm CMOS technology. 253-256 - Tien-Yu Lo:
A 102dB dynamic range audio sigma-delta modulator in 40nm CMOS. 257-260 - Chen-Yen Ho, Zwei-Mei Lee, Mu-Chen Huang, Sheng-Jui Huang:
A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application. 261-264 - Yu-Cheng Chang, Wei-Hao Chiu, Chen-Chien Lin, Tsung-Hsien Lin
A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter. 265-268 - Sanming Hu
A 434GHz SiGe BiCMOS transmitter with an on-chip SIW slot antenna. 269-272 - Ajay Balankutty, Stefano Pellerano, Telesphor Kamgaing, Kranti Tantwai, Yorgos Palaskas:
A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas. 273-276 - Morteza S. Alavi
A 2-GHz digital I/Q modulator in 65-nm CMOS. 277-280 - Yao-Hong Liu
A 15-mW 2.4-GHz IEEE 802.15.4 transmitter with a FIR-embedded phase modulator. 281-284 - Mark Ingels, Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto
An impedance modulated class-E polar amplifier in 90 nm CMOS. 285-288 - Zhiming Chen, Kuang-Wei Cheng, Yuanjin Zheng, Minkyu Je:
A 3.4-mW 54.24-Mbps burst-mode injection-locked CMOS FSK transmitter. 289-292 - Frank Hsiao, Adrian Tang, Derek Yang, Mike Pham, Mau-Chung Frank Chang
A 7Gb/s SC-FDE/OFDM MMSE equalizer for 60GHz wireless communications. 293-296 - Ippei Akita
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. 293-296 - Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Peter Burg
A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder. 297-300 - Shu-Yu Hsu, Yao-Lin Chen, Po-Yao Chang, Jui-Yuan Yu, Ten-Fang Yang, Ray-Jade Chen, Chen-Yi Lee:
A micropower biomedical signal processor for mobile healthcare applications. 301-304 - Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON. 305-308 - Po-Lin Chiu, Lin-Zheng Huang, Li-Wei Chai, Chun-Fu Liao, Yuan-Hao Huang:
A 684Mbps 57mW joint QR decomposition and MIMO processor for 4×4 MIMO-OFDM systems. 309-312 - Kai-Ting Shr, Yu-Cheng Chang, Chu-Yi Lin, Yuan-Hao Huang:
A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture. 313-316 - Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto:
A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS. 317-320 - Tom Redant, Frederic Stubbe, Wim Dehaene:
A low power time-of-arrival ranging front end based on a 8-channel 2.2mW, 53ps single-shot-precision Time-to-Digital converter. 321-324 - Hye-Jung Kwon, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park:
A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio. 325-328 - Yu-Huei Lee, Chao-Chang Chiu, Ke-Horng Chen
On-the-fly dynamic voltage scaling (DVS) in 65nm energy-efficient power management with frequency-based control (FBC) for SoC system. 329-332 - Yingchieh Ho, Yu-Sheng Yang, Chauchin Su:
A 0.2-0.6 V ring oscillator design using bootstrap technique. 333-336 - Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang
A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. 337-340 - Jae-Hyuck Woo, Jae-Goo Lee, In-Suk Kim, Young-Hyun Jun, Gyoo-Cheol Hwang, Myung-Hee Lee, Bai-Sun Kong:
Line inversion-based mobile TFT-LCD driver IC with accurate quadruple-gamma-curve correction. 341-344 - B. Robert Gregoire, Tawfiq Musah
A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp. 345-348 - Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye, Junyan Ren:
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. 349-352 - Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa:
A time-domain architecture and design method of high speed A-to-D converters with standard cells. 353-356 - Chang-Ming Lai, Meng-Hung Shen, Geng-Yi Pan, Po-Chiun Huang:
A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection. 357-360 - Ying Cao, Paul Leroux
A 0.7mW 13b temperature-stable MASH ΔΣ TDC with delay-line assisted calibration. 361-364 - Sam Chun-Geik Tan, Fei Song, Renliang Zheng, Jiqing Cui, Guoqin Yao, Litian Tang, Yuejin Yang, Dandan Guo, Alexander Tanzil, Junmin Cao, Ming Kong, KianTiong Wong, Chee-Lee Heng, Osama Shana'a
An ultra-low-cost Bluetooth SOC in 0.11-μm CMOS. 365-368 - Po-Yun Hsiao, Yao-Hong Liu
An energy-efficient super-regenerative ASK receiver with a ΔΣ-based pulse-width demodulator. 369-372 - Hiroki Asada, Keigo Bunsen
A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS. 373-376 - Rashmi Nanda, Henry Chen, Dejan Markovic:
A low-power digital front-end direct-sampling receiver for flexible radios. 377-380 - X. Wang, Kathleen Philips, C. Zhou, Ben Busze, Hans W. Pflug, Alex Young, Jac Romme, Pieter Harpe, Sumit Bagga, Stefano D'Amico
A high-band IR-UWB chipset for real-time duty-cycled communication and localization systems. 381-384 - Hao-Ming Chao, Kuei-Ann Wen, Michiel Steyaert
An active guarding technique for substrate noise suppression on LC-tank oscillators. 385-388 - Jinwook Oh, Gyeonghoon Kim, Hoi-Jun Yoo:
An asynchronous mixed-mode neuro-fuzzy controller for energy efficient machine intelligence SoC. 389-392 - Masanori Kurimoto, Yasuhiko Takahashi, Yuji Fujiwara, Mamoru Sakugawa, Souichi Kobayashi, Hiroyuki Kondo:
System performance and energy consumption improvement methodology by delay adjustable synchronizer. 393-396 - Junyoung Park, Joonsoo Kwon, Jinwook Oh, Seungjin Lee, Hoi-Jun Yoo:
A 92mW real-time traffic sign recognition system with robust light and dark adaptation. 397-400 - Rahul Rithe, Chih-Chi Cheng, Anantha P. Chandrakasan:
Quad Full-HD transform engine for dual-standard low-power video coding. 401-404 - Chia-Ming Chang, Yu-Jung Chen, Yen-Chang Lu, Chun-Yi Lin, Liang-Gee Chen
A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor for mobile multimedia applications. 405-408
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