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APCCAS 2012: Kaohsiung, Taiwan
- IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012. IEEE 2012, ISBN 978-1-4577-1728-4
- Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo
, Jia Hao Cheong, Lei Yao, Meng Tong Tan, Minkyu Je:
A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems. 1-4 - Chiang Liang Kok
A fully digital green LDO regulator dedicated for biomedical implant using a power-aware binary switching technique. 5-8 - Dinup Sukumaran, Enyi Yao, Sun Shuo, Arindam Basu
A low-power, reconfigurable smart sensor system for EEG acquisition and classification. 9-12 - Tongxi Wang, Xiwei Huang, Mei Yan, Hao Yu, Kiat Seng Yeo
A 96×96 1V ultra-low power CMOS image sensor for biomedical application. 13-16 - Xiaodan Zou, Lei Liu, Yung Sern Tan, Minkyu Je, Kiat Seng Yeo
Integrated circuits design for neural recording sensor interface. 17-20 - Bing Han, Jian-Guo Ma:
The evolution and developing tendency of DAC design methods. 21-24 - Nasim Soufizadeh-Balaneji, Khayrollah Hadidi:
A novel quantization algorithm suitable for high-speed analog-to-digital converters. 25-28 - Yun Du, Tao He, Yang Jiang
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. 29-32 - Tao He, Yun Du, Yang Jiang
A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. 33-36 - Shih-Hao Fang, Ju-Ya Chen, Jing-Shiun Lin, Ming-Der Shieh, Wei-Chieh Huang, Jen-Yuan Hsu:
Blind channel estimation for MIMO-OFDM systems with repeated time-domain symbols. 37-40 - Dragana Barjamovic, Izzet Kale:
Comparative performance analysis of a streamlined iteration cancellation technique for MIMO-OFDM systems with memoryless nonlinearity. 41-44 - Li-An Ou, Chih-Chia Wei, Kuang-Yi Hsu
Kernel-stopped parallel turbo decoding for HomePlug Green PHY systems. 45-48 - Wei Zhang, Xinmiao Zhang, Hao Wang:
Increasing the energy efficiency of WSNs using algebraic soft-decision reed-solomon decoders. 49-52 - Chen Liu, Xin Jin, Satoshi Goto:
Envelope detection based workload prediction for partial decoding scheme. 53-56 - King-Man Lai, Chenchang Zhan, Wing-Hung Ki
A comparative study of hysteretic voltage-mode buck converters for high switching frequency and high accuracy. 57-60 - Fenjie Yuan, Xiaobo Wu, Sheng Liu:
A reconfigurable seamless-transition DC-DC Converter With lossless current-sensing technique. 61-64 - Hong Gao, Lin Xing, Yasunori Kobori, Feng Zhao, Haruo Kobayashi, Shyunsuke Miwa, Atsushi Motozawa, Zachary Nosker, Kiichi Niitsu
DC-DC converter with continuous-time feed-forward Sigma-Delta modulator control. 65-68 - Kazuaki Fukui, Hirotaka Koizumi:
Half-wave Class DE Low dv/dt rectifier. 69-72 - Tomoharu Nagashima, Xiuqin Wei, Tadashi Suetsugu
Inductively coupled wireless power transfer with class-DE power amplifier. 73-76 - Ya-Hsin Hsueh, Guei-Rong Chen:
Design of high voltage digital-to-analog converter for electrical stimulator. 77-80 - Chang-Hung Lee
The heterogeneous sensor system on chip. 81-83 - Chen-Yueh Huang, Shuenn-Yuh Lee, Jia-Hua Hong, Ming-Chun Liang, Cheng-Han Hsieh:
Burst-pulse control of microstimulator for bladder controller. 84-87 - Hung-Yi Hsieh, Kea-Tiong Tang:
A spiking neural network chip for odor data classification. 88-91 - Yung-Chan Chen, Yu-Po Lin, Tsui-Ling Hsieh, Chun-Yi Yeh, Pin-Yang Huang, Hung-Chih Chiu, Zong-Ye Wang, Wen-Yang Hsu, Po-Chiun Huang, Kea-Tiong Tang, Hsi-Pin Ma, Hsin Chen:
An implantable microsystem for studying the Parkinson's Disease. 92-95 - Yutaka Izumi, Hiroyuki Asahara, Kazuyuki Aihara, Takuji Kousaka:
Analysis of an interrupted circuit with fast-slow bifurcation. 96-99 - Kotaro Fukuda, Akio Tsuneda:
Key-sensitivity improvement of block cipher systems based on nonlinear feedback shift registers. 100-103 - Toshiyasu Ohata, Shota Kirikawa, Toshimichi Saito:
Fault tolerance of simplified parallel power converters with current sharing function. 104-107 - Hailang Liang, Jin He, Cheng Wang, Xiaoan Zhu, Mansun Chan
A MATLAB program for Volterra distortion analysis in CMOS switched source follower. 108-111 - Yuki Urata, Yasuhiro Takahashi
A low-power sense amplifier for adiabatic memory using memristor. 112-115 - Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu:
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. 116-119 - Ko-Chi Kuo, Chung-Yuan Chang, Si-Hsien Li:
Low power delay locked loop with all digital controlled SAR delay cell. 120-123 - Yasuhiro Takahashi
2PCDAL: Two-phase clocking dual-rail adiabatic logic. 124-127 - Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye, Junyan Ren:
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. 128-131 - Chao-Chin Yang, Jen-Fa Huang, Ta-Chun Nieh, Chun-Ming Huang:
Improvements of quasi-cyclic low-density parity-check codes based on hybrid structures of BIBD's schemes. 132-135 - Chien-Chi Chen, Po-Hung Wu, Jian-Jiun Ding, Hsin-Hui Chen:
Saliency detection improved by Principle Component Analysis and boundary scoring approach. 136-139 - Ying-Tsung Lin, Sau-Gee Chen:
An SNR-aware inter-symbol data-mapping precoding scheme for single-carrier systems. 140-143 - Yi-Ching Ting, Tian-Sheuan Chang
Fast intra prediction algorithm with transform domain edge detection for HEVC. 144-147 - Yinsidi Jiao, Wei-Han Yu
A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation. 148-151 - Tsung-Sum Lee, Wen-Zhe Lu, Yi-Cheng Huang:
A 0.6-V subthreshold-leakage supressed CMOS fully differential switched-capacitor amplifier. 152-155 - Peng Sun, Menglian Zhao, Xiaobo Wu, Rui Fan:
A novel capacitively-coupled instrumentation amplifier employing chopping and auto-zeroing. 156-159 - Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Jin-Fu Lin:
A 1-V CDS bandgap reference without on-chip resistors. 160-163 - Keigo Oshiro, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel
A small die area and high linearity 10-bit capacitive three-level DAC. 164-167 - Kwan Wai Li, Ka Nang Leung
A low-power MICS fractional-N frequency synthesizer for implantable biomedical systems. 168-171 - Cihun-Siyong Alex Gong, Kai-Wen Yao, Muh-Tian Shiue, Yin Chang:
An impedance measurement analog front end for wirelessly bioimplantable applications. 172-175 - Shin-Il Lim, In-Sub Choi, Hanho Lee:
Biochemical sensor interface circuits with differential difference amplifier. 176-179 - Bharatha Kumar Thangarasu, Kaixue Ma, Kiat Seng Yeo, Wei Meng Lim:
A 12-GHz high output power amplifier using 0.18µm SiGe BiCMOS for low power applications. 180-183 - Jiang An Han, Zhi-Hui Kong, Kaixue Ma, Kiat Seng Yeo
Recent progress in silicon-based millimeter-wave power amplifier. 184-187 - Kaixue Ma, Shouxian Mou, Kiat Seng Yeo
On-chip tunable low pass filter with improved stopband using new cross coupled topology. 188-191 - Ming-Wei Wu, Chien-Pai Wu, Yen-Chung Chiang:
A V-band power amplifier with 11.6dB gain and 7.8% PAE in GaAs 0.15µm pHEMT process technology. 192-195 - Kohshi Okumura:
An approach to all modes of nonlinear oscillations in three-phase circuits by computer algebra system. 196-199 - Goki Ikeda, Hiroyuki Asahara, Kazuyuki Aihara, Takuji Kousaka:
A search algorithm of bifurcation point in an impact oscillator with periodic threshold. 200-203 - Masaaki Kojima
Double-mode oscillation in chaotic circuits coupled by a time-varying resistor. 204-207 - Takumi Hasegawa, Tadashi Tsubone:
Stabilizing unstable periodic orbits in higher dimensional systems based on stability transformation method. 208-211 - Donald Y. C. Lie, Yan Li, Ruili Wu, Weibo Hu, Jerry Lopez, Cliff Schecht, Yenting W. Liu:
Design of monolithic silicon-based envelope-tracking power amplifiers for broadband wireless applications. 212-215 - Hao Wang, Wei Zhang, Jing Wang, Zhe Jiang:
Hardware complexities of low-complexity Chase Reed Solomon decoders and comparisons. 216-219 - Sevket Cetinsel, Richard C. S. Morling, Izzet Kale:
A comparative study of a low doppler shift in a carrier tracking loop for GPS. 220-223 - I-Wen Liu, Chun-Fu Liao, Fang-Chun Lan, Yuan-Hao Huang:
Low-complexity lattice reduction architecture using interpolation-based QR decomposition for MIMO-OFDM systems. 224-227 - Tzung-Je Lee, Wen-Je Lu, Wei-Chih Hsiao, Chua-Chin Wang:
Linear programmable gain amplifier using reconfiguration local-feedback transconductors. 228-231 - Shunli Ma, Changming Chen, Yiwen Zhang, Junyan Ren:
A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system. 232-235 - Liang-Hung Wang, Tsung-Yen Chen, Shuenn-Yuh Lee, Huan Chen:
Implementation of a personal health monitoring system in cardiology application. 236-239 - Saumya Kareem, Izzet Kale, Richard C. S. Morling:
Automated malaria parasite detection in thin blood films: - A hybrid illumination and color constancy insensitive, morphological approach. 240-243 - Qiong Zou, Kaixue Ma, Wanxin Ye, Kiat Seng Yeo:
A low power millimetre-wave VCO in 0.18 µm SiGe BiCMOS technology. 244-247 - Fanyi Meng
Design of quarter-wavelength resonator filters with coupling controllable paths. 248-251 - Wanlan Yang, Kaixue Ma, Kiat Seng Yeo
A 60GHz on-chip antenna in standard CMOS silicon Technology. 252-255 - Keping Wang, Kaixue Ma, Kiat Seng Yeo
Low-power high-speed dual-modulus prescaler for Gb/s applications. 256-259 - Wen-Cheng Lai
1MS/s low power successive approximations register ADC for 67-fJ/conversion-step. 260-263 - Sheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, Soon-Jyh Chang:
A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology. 264-267 - Wen-Lan Wu, Sai-Weng Sin
A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. 268-271 - Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. 272-275 - Satoshi Matsumoto, Sumio Fukai, Akio Shimizu, Yohei Ishikawa:
Multiple-output neuron MOS current mirror with bias circuit suitable for Digital-to-Analog converter. 276-279 - Chien-Cheng Tseng, Su-Ling Lee:
Design and application of wide-range variable fractional delay filter. 280-283 - Takao Hinamoto, Akimitsu Doi, Wu-Sheng Lu:
Roundoff noise reduction in state-space digital filters using high-order error feedback and realization. 284-287 - Fumio Itami, Eiji Watanabe:
A design of a synthesis filter bank with fractional scalability factors. 288-291 - Chien-Cheng Tseng, Su-Ling Lee:
Weighted least squares design of wideband digital integrator using interlaced sampling method. 292-295 - Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
A unified {2n-1, 2n, 2n+1} RNS scaler with dual scaling constants. 296-299 - Chua-Chin Wang, Tzu-Chiao Sung, Yihong Wu, Chia-Hao Hsu, Doron Shmilovitz:
A reconfigurable 16-channel HV stimulator ASIC for Spinal Cord Stimulation systems. 300-303 - Shaista Hussain
DELTRON: Neuromorphic architectures for delay based learning. 304-307 - Kazuki Nakada, Keiji Miura, Tetsuya Asai, Hisa-Aki Tanaka:
Dynamical systems design of nonlinear oscillators using phase reduction approach. 308-311 - Torsten Lehmann, Louis H. Jung, Yashodhan Moghe, Hosung Chun, Yuanyuan Yang, Asish Zac Alex:
Low-power circuit structures for chip-scale stimulating implants. 312-315 - Longfei Wei, Jinyue Ji, Haiqi Liu, Qiang Li:
A multi-rate SerDes transceiver for IEEE 1394b applications. 316-319 - S. Pradeep Reddy, Ashudeb Dutta, Shiv Govind Singh:
A reconfigurable aperture coupled microstrip patch antenna with beam steering capability on silicon. 320-323 - A. Owzar, Ertan Baykal, P. Felicio, T. Zheng, Ralph Stephan, Markus Helfenstein, Rolf Becker:
SOI vs. bulk for wireless application. 324-327 - Yao Zhu, Yuanjin Zheng, Chee-Leong Wong, Minkyu Je, Khine Lynn, Piotr Kropelnicki, Julius Ming-Lin Tsai:
Design of a 843MHz 35µW SAW oscillator using device and circuit co-design technique. 328-331 - Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
Optimal design method for chip-area-efficient CMOS low-dropout regulator. 332-335 - T. O. Ting
Maximum Power Point Tracking (MPPT) via Weightless Swarm Algorithm (WSA) on cloudy days. 336-339 - Tomoyuki Mizuno, Tomoshige Inoue, Keisuke Iwasawa, Hirotaka Koizumi:
A voltage equalizer using flyback converter with active clamp. 340-343 - Ryota Mizutani, Hirotaka Koizumi, Eiji Kamiya, Kentaro Hirose:
Development of three-phase to single-phase matrix converter for improvement of three-phase voltage unbalance in distribution system. 344-347 - Libin George, Torsten Lehmann, Tara Julia Hamilton
A synchronous buck-boost converter on a Silicon-On-Sapphire 0.5µm process. 348-351 - Earn Tzeh Tan, Zaini Abdul Halim:
Development of an artificial neural network system for sulphate-reducing bacteria detection by using model-based design technique. 352-355 - Chihiro Ikuta, Yoko Uwate, Yoshifumi Nishio
Improvement of learning performance of multi-layer perceptron by two different pulse glial networks. 356-359 - Chien-Wei Chen, Chao-Yi Cho, Yi-Fa Sun, Tse-Min Chen, Ching-Lung Su:
Low complexity photo sensor dead pixel detection algorithm. 360-363 - Ahmad Mansour, Jürgen Götze:
An OMNeT++ based Network-on-Chip simulator for embedded systems. 364-367 - Edward T.-H. Chu, Wen-wei Lu:
Cache utilization-aware scheduling for multicore processors. 368-371 - Chung Chuang, Chun-Yen Wu, Chi-Chun Hsu, Li-Ren Huang, Wei-Min Cheng, Wen-Dar Hsieh:
A design for testability of non-volatile memory reliability test for automotive embedded processor. 372-375 - Hao-Chan Ting, Shih-Sheng Chen, Kevin Labille, Yu-Wen Tsai, Yen-Hsiang Chen, Shanq-Jang Ruan:
Intelligent applications design in automotive infortainment systems. 376-379 - Lih-Yih Chiou, Liang-Ying Lu, Bo-Chi Lin, Alan P. Su:
Buffer size minimization method considering mix-clock domains and discontinuous data access. 380-383 - Jun Zhang
A low-voltage, low-power subthreshold CMOS voltage reference without resistors and high threshold voltage devices. 384-387 - Li Chuang Quek, Bok Eng Cheah, Wai Ling Lee, Weng Chong Sam:
Intrinsic capacitance extraction and estimation for system-on-chip power delivery development. 388-391 - Yin-Tsung Hwang, Yi-Chih Chen, Cheng-Ru Hong, Yu-Ting Pei, Chi-Ho Chang, Jui-Chi Huang:
Design and FPGA implementation of a FMCW radar baseband processor. 392-395 - Chun-Ming Huang, Chih-Chyau Yang, Chien-Ming Wu, Chih-Hsing Lin, Chun-Chieh Chiu, Yi-Jun Liu, Chun-Chieh Chu, Nien-Hsiang Chang, Wen-Ching Chen:
A modularized 3D heterogeneous system integration platform. 396-399 - Hong Yang, Qingqing Yang, Yuanwei Fang, Xiaofang Zhou, Gerald E. Sobelman:
A novel hardware-oriented decoding algorithm for non-binary LDPC codes. 400-403 - Seungju Lee, Nozomu Togawa
A hybrid NoC architecture utilizing packet transmission priority control method. 404-407 - Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen:
Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. 408-411 - Aijiao Cui, Chip-Hong Chang
A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. 412-415 - Terence Chan:
A robust multithreaded HDL/ESL simulator for deep submicron integrated circuit designs. 416-419 - Yonggen Liu, Chenchang Zhan, Lin Cheng
A 10/30MHz PWM buck converter with an accuracy-improved ramp generator. 420-423 - Boy-Yiing Jaw, Hongchin Lin
An analysis of output ripples for PMOS charge pumps and design methodology. 424-427 - Qing Liu, Xiaobo Wu, Menglian Zhao, Mingyang Chen, Xiaoting Shen:
Monolithic quasi-sliding-mode controller for SIDO buck converter in PCCM. 428-431 - Qing Liu, Xiaobo Wu, Menglian Zhao, Lu Wang, Xiaoting Shen:
30-300mV input, ultra-low power, self-startup DC-DC boost converter for energy harvesting system. 432-435 - Yasunori Kobori, Qiulin Zhu, Murong Li, Feng Zhao, Zachary Nosker, Shu Wu, Shaiful N. Mohyar, Masanori Onozawa, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu
Single inductor dual output DC-DC converter design with exclusive control. 436-439 - Eric Shianda Yu, Chung-Ho Chen:
A SIMD-accelerated software rendering pipeline for 3D graphics processing. 440-443 - Yi-Hao Chang, Chi-Tsai Yeh, Ing-Jer Huang, Shau-Yin Tseng:
A performance monitoring tool suite for 3D graphics SoC application. 444-447 - Ching-Lung Su, Po-Yu Chen, Chun-Chieh Lan, Lung-Sheng Huang, Kuo-Hsuan Wu:
Overview and comparison of OpenCL and CUDA technology for GPGPU. 448-451 - Parkson Wong, Kuo-Tseng Tseng, Eric Lee, Harn Tarn:
Immerse™: An alternative approach to 3D graphics performance. 452-455 - Tung-Ying Lee, Chen-Hao Wei, Shang-Hong Lai
Real-time correction of wide-angle lens distortion for images with GPU computing. 456-459 - Juin J. Liou, Chang Jiang, Feng Chia:
Electrostatic discharge (ESD) protection of RF integrated circuits. 460-462 - Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. 463-466 - Shiang-Yu Tsai, Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker:
Design of ESD protection for RF CMOS power amplifier with inductor in matching network. 467-470 - Ming-Fu Tsai, Jen-Huan Tsai, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM. 471-474 - Chiu-Wing Sham
A layered QC-LDPC decoder architecture for high speed communication system. 475-478 - Yichao Lu, Nanfan Qiu, Zhixiang Chen, Satoshi Goto:
An efficient majority-logic based message-passing algorithm for non-binary LDPC decoding. 479-482 - Tuan Anh Vu, Shanthi Sudalaiyandi, Håkon A. Hjortland
A variable-gain single-bit ultra-wideband quantizer for baseband receiver front-end. 483-486 - Shanthi Sudalaiyandi, Tuan Anh Vu, Håkon A. Hjortland
Continuous-time symbol detector for IR-UWB rake receiver in 90 nm CMOS. 487-490 - Jungo Moriyasu, Ryota Kouzuki, Toshimichi Saito:
Dynamic binary neural networks and storage of control signals for switching circuits. 491-494 - Yoshihiro Kato, Yoko Uwate, Yoshifumi Nishio
Cellular neural networks with effect from friend having most different values and its friends. 495-498 - Tomoya Shima, Yoko Uwate, Thomas Ott, Yoshifumi Nishio
Investigation of synchronization for social network with local bridge via coupled Rulkov maps. 499-502 - Tomohiro Kato, Nur Atiqah Farahin Kamarul Zaman, Mikio Hasegawa
Application of multi-armed bandit algorithms for channel sensing in cognitive radio. 503-506 - Chao-Tsung Kuo, Tso-Bing Juang:
A lower error antilogarithmic converter using novel four-region piecewise-linear approximation. 507-510 - Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee:
Low-cost designs of rectangular to polar coordinate converters for digital communication. 511-514 - Tso-Bing Juang, Jian-Hao Huang:
Multifunction RNS modulo (2n±1) multipliers based on modified booth encoding. 515-518 - Petter Kallstrom, Mario Garrido
Low-complexity rotators for the FFT using base-3 signed stages. 519-522 - Yan-Haw Chen, R. S. Huang, S. L. Jhuang, W. Tian:
Robustness file copy up into cloud storage service. 523-526 - Jiaxin Liu, Yao Wang
Current reference with temperature compensation for low power applications. 527-530 - Guanglei Jin, Hao Chen, Chuan Gao, Yunpeng Zhang, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu
Digitally-controlled Gm-C bandpass filter. 531-534 - Ko-Chi Kuo, Shan-Yu Chen, Shih-Min Tseng:
High linear transconductor for multiband CMOS receiver. 535-538 - Abul Hasan Johari, Hiroki Ishikuro:
0.6 - 3.6 GHz wideband operation with high phase resolution On-Chip Network Analyzer. 539-542 - Der-Wei Yang, Chun-Wei Chen, Che-Hao Chang, Yun-Chen Chang, Ming-Der Shieh, Jonas Wang, Chia-Cheng Lo:
Face detection architecture design using hybrid skin color detection and cascade of classifiers. 543-546 - Guifen Tian, Satoshi Goto:
An optimization scheme for quadtree-structured prediction and residual encoding in HEVC. 547-550 - Chih-Lun Fang, Tsung-Han Tsai, Chih-Hao Chang:
Video stabilization with local rotational motion model. 551-554 - Chia-Lin Liu, Chang-Hung Tsai, Hsiuan-Ting Wang, Yao Li, Chen-Yi Lee:
A memory-efficient architecture for intra predictor and de-blocking filter in video coding system. 555-558 - Bo Yu, Suoming Pu:
Redesign modern IP router chips in a 3D technology. 559-562 - Matthias Lechtenberg, Kay Gorner, Jürgen Götze
Estimation of oscillation parameters for power grids. 563-566 - Meng-Kang Chiang, Katherine Shu-Min Li:
Intelligent home management in the smart grids. 567-570 - Dinh-Nhon Truong, Li Wang:
Power system stability enhancement with an integrated offshore wind farm and marine-current farm using a STATCOM. 571-574 - Mi Sa-Nguyen Thi, Li Wang:
Stability analysis of power transmission of offshore wind farms fed to onshore power grids using a multi-terminal VSC-HVDC system. 575-578 - Chuan-Ping Yan, Guangjun Li, Qiang Li:
A fast correlation based background digital calibration for pipelined ADCs. 579-582 - Hui Wang, Huawei Chen, Yu Bao, Linjian Li:
Robust farfield wideband beamformer design using worst-case performance optimization. 583-586 - Ali Telli, Izzet Kale:
A range of allowable number of input bits for tone free delta-sigma operation in digital MASH Delta-Sigma Fractional-N frequency synthesizers. 587-590 - Jian-Hua Wang, Jian-Jiun Ding, Yu Chen, Hsin-Hui Chen:
Real time accelerometer-based gait recognition using adaptive windowed wavelet transforms. 591-594 - Ching-Che Chung
A low-complexity high-performance wear-leveling algorithm for flash memory system design. 595-598 - Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
Scan-based attack against DES cryptosystems using scan signatures. 599-602 - Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa
Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. 603-606 - Yuta Atobe, Youhua Shi
State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. 607-610 - Mochamad Asri, Hsuan-Chun Liao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
A reconfigurable ASIP-based approach for high performance image signal processing. 611-614 - Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue:
Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool. 615-618 - Yi-Chun Yen, Jhih-Kai Yang, Wei-Kai Cheng:
Memory binding and layer assignment for high-level synthesis of 3D ICs. 619-622 - Bo-Chuan Cheng, Katherine Shu-Min Li, Sying-Jyan Wang
De Bruijn graph-based communication modeling for fault tolerance in smart grids. 623-626 - Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang:
Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. 627-630 - Nan Liu, Shiyu Liu, Takeshi Yoshimura:
Wirelength driven I/O buffer placement for flip-chip with timing-constrained. 631-634 - Keisuke Suzuki, Tadashi Tsubone:
Synchronization phenomena of picewise constant oscillators coupled by hysteresis element. 635-638 - Kosuke Niimi, Seiko Kunihiro, Masayuki Yamauchi:
Instantaneous electric power's behavior of phase waves and phase-inversion waves on coupled van der Pol oscillators as a ladder. 639-642 - Yoko Uwate, Yoshifumi Nishio
Chaos propagation in a ring of coupled circuits generating chaotic and three-periodic attractors. 643-646 - Yuji Takamaru, Yoko Uwate, Thomas Ott, Yoshifumi Nishio
Clustering phenomena considering the density of coupled chaotic circuits networks. 647-650 - Kuang-Hao Lin, Tai-Hsuan Yang, Ren-Hao Wu, Hou-Ming Chen, Jan-Dong Tseng:
A multimedia game development system with an intelligent mobile and embedded platform. 651-654 - Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. 655-658 - Hsin-Yi Wang, Li-Hung Wang, Chung-Bin Wu
An efficient background extraction and object segmentation algorithm for realtime applications. 659-662 - Juhi Bhadviya, Sunil Prasad Jaiswal
Exploitation of temporal redundancy for lossless video coding. 663-666 - Po-Ming Lee, Wei-Hsuan Tsui, Yun Teng, Tzu-Chien Hsiao:
Affective pattern analysis of image in frequency domain using the Hilbert-Huang Transform. 667-670 - Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu
Multi-bit sigma-delta TDC architecture with self-calibration. 671-674 - Seiya Nagatsuka, Yasuhiro Takashima:
Sub-path delay estimation for reconvergent path. 675-678 - Nonie Politi, Julian Jenkins, André van Schaik
A method for measuring switching frequency using complex asynchronous logic circuits. 679-682 - Tong-Yu Hsieh, Chia-Chi Ku, Chia-Hung Yeh:
A yield and reliability enhancement framework for image processing applications. 683-686
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