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Manh Anh Do
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2010 – 2019
- 2013
- [j21]Dandan Chen, Kiat Seng Yeo
, Xiaomeng Shi, Manh Anh Do, Chirn Chye Boon
Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1516-1525 (2013) - 2012
- [j20]Juan Xie, Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon
A low power low phase noise dual-band multiphase VCO. Microelectron. J. 43(12): 1016-1022 (2012) - [j19]Yung Sern Tan, Kiat Seng Yeo
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(6): 1156-1167 (2012) - [j18]Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon
A Low-Power Single-Phase Clock Multiband Flexible Divider. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 376-380 (2012) - [c13]Fanyi Meng
Design of quarter-wavelength resonator filters with coupling controllable paths. APCCAS 2012: 248-251 - 2011
- [c12]Ali Meaamar, Chirn Chye Boon
A 3.1-8 GHz CMOS UWB front-end receiver. ISCAS 2011: 1556-1559 - 2010
- [j17]Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 72-82 (2010) - [j16]Ali Meaamar, Chirn Chye Boon
A Wideband Low Power Low-Noise Amplifier in CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(4): 773-782 (2010) - [j15]Aaron V. T. Do, Chirn Chye Boon
An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2675-2684 (2010) - [j14]Zhenghao Lu, Kiat Seng Yeo
Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 461-472 (2010) - [c11]Aaron V. T. Do, Chirn Chye Boon, Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo:
A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole. VLSI-SoC (Selected Papers) 2010: 1-21 - [c10]Manthena Vamshi Krishna, Xuan Jie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do:
A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4. VLSI-SoC (Selected Papers) 2010: 69-99 - [c9]Aaron V. T. Do, Chirn Chye Boon
A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. VLSI-SoC 2010: 381-386 - [c8]Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. VLSI-SoC 2010: 387-391
2000 – 2009
- 2008
- [j13]Shan Jiang, Manh Anh Do, Kiat Seng Yeo
An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1430-1440 (2008) - [j12]Xiaomeng Shi, Kiat Seng Yeo
Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 922-926 (2008) - 2007
- [j11]Xiaomeng Shi, Kiat Seng Yeo
Distortion of pulsed signals in carbon nanotube interconnects. Microelectron. J. 38(3): 365-370 (2007) - [j10]Zhenghao Lu, Kiat Seng Yeo
Broad-Band Design Techniques for Transimpedance Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(3): 590-600 (2007) - 2006
- [j9]J. J. Liu, Manh Anh Do, Xiaopeng Yu
Cmos Even Harmonic Switching mixer for Direct Conversion Receivers. J. Circuits Syst. Comput. 15(2): 183-196 (2006) - [j8]Yang Lu, Kiat Seng Yeo
A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(8): 1683-1692 (2006) - [c7]Shan Jiang, Manh Anh Do, Kiat Seng Yeo
A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. VLSI-SoC (Selected Papers) 2006: 81-99 - [c6]Xiaopeng Yu
A New Phase Noise Model for TSPC based divider. VLSI-SoC 2006: 348-351 - [c5]Shan Jiang, Manh Anh Do, Kiat Seng Yeo
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. VLSI-SoC 2006: 352-356 - 2005
- [j7]Chirn Chye Boon
Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1042-1048 (2005) - [j6]Shouxian Mou, Jianguo Ma, Kiat Seng Yeo
A modified architecture used for input matching in CMOS low-noise amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 52-II(11): 784-788 (2005) - [j5]Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo
Equivalent circuit model of on-wafer CMOS interconnects for RFICs. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1060-1071 (2005) - [j4]Xiaopeng Yu
Design of a low power wide-band high resolution programmable frequency divider. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1098-1103 (2005) - [c4]Lin Jia, Jianguo Ma, Kiat Seng Yeo
A novel methodology for the design of LC tank VCO with low phase noise. ISCAS (1) 2005: 376-379 - [c3]Wei Meng Lim, Han Guo Ma, Manh Anh Do, Kiat Seng Yeo
A 5GHz to 6GHz integrated differential LNA. ISCAS (5) 2005: 4815-4818 - [c2]Xiaopeng Yu
A new 5 GHz CMOS dual-modulus prescaler. ISCAS (5) 2005: 5027-5030 - 2004
- [j3]Chirn Chye Boon
RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor. IEEE Trans. Circuits Syst. II Express Briefs 51-II(2): 85-90 (2004) - [c1]Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li:
Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. SLIP 2004: 31-38 - 2001
- [j2]Wanshi Chen
A New Improved First-Order Approximate Decorrelating Detector for DS-CDMA Communication Systems. Wirel. Pers. Commun. 16(3): 221-228 (2001) - 2000
- [j1]Wanshi Chen
Performance analysis of adaptive MMSE reception for DS-CDMA in flat Nakagami fading channels. IEEE Trans. Veh. Technol. 49(2): 561-564 (2000)
Coauthor Index
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