VERILOG HDL

Prof. GIRISH H ,
Associate Professor
Department of
Electronics & Communication Engineering

www.cambridge.edu.in
 Syllabus
Module 1
Overview of Digital Design with Verilog HDL: Evolution of CAD, emergence of HDLs, typical HDL-flow, why Verilog HDL?,
trends in HDLs.
Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences between modules and module
instances, parts of a simulation, design block, stimulus block.
Module 2
Basic Concepts: Lexical conventions, data types, system tasks, compiler directives.
Modules and Ports: Module definition, port declaration, connecting ports, hierarchical name referencing.
Module 3
Gate-Level Modeling: Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall
and turn-off delays, min, max, and typical delays.

Dataflow Modeling: Continuous assignments, delay specification, expressions, operators, operands,

operator types.

Module 4
Behavioral Modeling: Structured procedures, initial and always, blocking and non-blocking statements, delay control,
generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks.
Tasks and Functions: Differences between tasks and functions, declaration, invocation, automatic tasks and functions.

Module 5
Useful Modeling Techniques: Procedural continuous assignments, overriding parameters, conditional compilation and
execution, useful system tasks.
Logic Synthesis with Verilog: Logic Synthesis, Impact of logic synthesis, Verilog HDL Synthesis, Synthesis design flow,
Verification of Gate-Level Netlist.
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 Text Books

Text Book:
Samir Palnitkar, “Verilog HDL: A Guide to Digital Design
and Synthesis”, Pearson Education, Second Edition.
Reference Books:
1. Donald E. Thomas, Philip R. Moorby, “The Verilog Hardware Description Language”, Springer
Science Business Media, LLC, Fifth edition.
2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson (Prentice Hall), Second
edition.
3. Padmanabhan, Tripura Sundari, “Design through Verilog HDL”, Wiley, 2016 or earlier.

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 CONTENTS

Overview of Digital Design with Verilog HDL

• Evolution of CAD
• Emergence of HDLs
• Typical HDL-flow
• Why Verilog HDL?
• Trends in HDLs.

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 Evolution of Computer Aided Digital Design
• The earliest digital circuits were designed with vacuum tubes and
transistors.
• The first integrated circuit (IC) chips were SSI
• Computer Aided Design (CAD) techniques began to evolve.
• The circuits were still tested on the breadboard, and the layout was
done on paper or by hand on a graphic computer terminal.
• With the advent of VLSI (Very Large Scale Integration) technology,
designers could design single chips with more than 100,000 transistors.
• Computer-aided techniques became critical for verification and design
of VLSI digital circuits.
• Computer programs to do automatic placement and routing of circuit
layouts also became popular.

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 What is HDL?
—Hardware description language describes
the hardware of digital systems in textual
form.
—One can design any hardware at any level
—Simulation of designs before fabrication
—With the advent of VLSI, it is not possible to
verify complex design with millions of gates
on a breadboard, HDLs came into existence
to verify the functionality of these circuits.

Girish H, Associate Professor, Department of Electronics & Communication Engineering www.cambridge.edu.in

 Emergence of
HDL
• HDLs allowed the designers to model the concurrency of processes found in
hardware elements.
• HDL such as Verilog HDL and VHDL became popular
• Verilog HDL was originated in 1983 at Gateway Design Automation.
• VHDL was developed under contract from DARPA.
• HDL were popular for logic verification.
• The advent of logic synthesis changed the design methodology.
• HDLs began to be used for system level design.
• HDL were used for simulation of system boards, interconnect buses, FPGA
and PAL.
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 Typical Design Flow

• Design Specification
• Behavioral Description
• RTL Description
• Gate Level Netlist
• Physical Layout
• Layout verification
• Implementation

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 Importance of HDL
• HDL have many advantages compared to traditional schematic based design
• Designs can be described at a very abstract level by use of HDLs. Designers
can write their RTL description without choosing a specific fabrication
technology. Logic synthesis tools can automatically convert the design to any
fabrication technology.
• By describing designs in HDLs, functional verification of the design can be
done early in the design cycle. Since designers work at the RTL level, they can
optimize and modify the RTL description until it meets the desired
functionality.
• Designing with the HDL is analogous to computer programming. A textual
description with comments is an easier way to develop and debug circuits
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 Popularity of Verilog HDL
• Verilog HDL is a general purpose hardware description language that is easy to
learn and easy to use. It is similar in syntax to the C programming language.
Designers with C programming will find it easy.
• Verilog HDL allows different levels of abstraction to be mixed in the same model.
• Most popular logic synthesis tools support Verilog HDL. This makes it the language
of choice for designers.
• All fabrication vendors provide Verilog HDL libraries for postlogic synthesis
simulation. Thus, designing a chip in Verilog HDL allows the widest choice of
vendors.
• The Programming Language Interfae (PLI) is a powerful feature that allows the
user to write custom C code to interact with the internal data structures of Verilog.

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 Trends in HDLs
• The speed and complexity of digital circuits has increased rapidly. Designers have
responded by designing at higher levels of abstraction.
• The most popular trend currently is to design in HDL at an RTL Level because logic
synthesis tools can create gate level netlists from RTL level design.
• Formal Verification techniques are also appearing on the horizon. Formal verification
applies formal mathematical techniques to verify the correctness of Verilog HDL
descriptions.
• For very high speed and timing critical circuits like microprocesors, the gate level
netlist provided by logic synthesis tools is not optimal.
• A trend that is emerging for system level design is a mixed bottom up methodology
where the designers use either existing Verilog HDL modules, basic building blocks,
or vendor supplied core blocks to quickly bring up their system simulation.
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Quiz
• EDA
• CAD
• HDL
• VHDL
• Verilog HDL
• FPGA
• CPLD
• PLA
• PLD
 Hierarchical Modeling Concepts
• Top-down and bottom-up design methodology
• Differences between modules and module instances
• Parts of a simulation
• Design block
• Stimulus block.

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 Design Methodologies
• Top Down Methodology
• Bottom Up Methodology
Top Down Methodology

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 Bottom up Methodology

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 4-bit Ripple Carry Counter

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 T-flipflop and the Hierarchy

Girish H, Associate Professor, Department of Electronics & Communication Engineering www.cambridge.edu.in

 Design Hierarchy Example
4 bit ripple counter

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 Modules
module
<module_name>(<module_terminal_list>);
...
<module internals>
...
endmodule

• Example:
module T_ff(q, clock, reset);
...
<functionality of T_flipflop>
...
endmodule
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 Modules (cont’d)
• Verilog supported levels of abstraction
• Behavioral (algorithmic) level
• Describe the algorithm used
• Very similar to C programming
• Dataflow level
• Describe how data flows between registers and is processed
• Gate level
• Interconnect logic gates
• Switch level
• Interconnect transistors (MOS transistors)
• Register-Transfer Level (RTL)
• Generally known as a combination of
behavioral+dataflow that is synthesizable by EDA tools
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 Instances
module ripple_carry_counter(q, clk, reset);

output [3:0] q;
input clk, reset;

//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);

endmodule

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 // module DFF with asynchronous reset
module DFF(q, d, clk, reset);
module TFF(q, clk, reset); output q;
output q; input d, clk, reset;
input clk, reset; reg q;
wire d; always @(posedge reset or negedge clk)
DFF dff0(q, d, clk, reset); if (reset)
not n1(d, q); q = 1'b0;
endmodule else
q = d;
endmodule

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 • Illegal instantiation example:
• Nested module definition not allowed
• Note the difference between module definition and module instantiation
// Define the top level module called ripple carry
// counter.It is illegal to define the module T_FF inside
// this module.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING
:
<module T_FF internals>
:
endmodule // END OF ILLEGAL MODULE NESTING
endmodule
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 Simulation- Test Bench Styles

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 Simulation- Test Bench Styles

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 module stimulus;
reg clk; reg reset; wire[3:0] q;
ripple_carry_counter r1(q, clk, reset);
initial clk = 1'b0;
always #5 clk = ~clk;
initial

Stimulus
begin
reset = 1'b1;

Block #15 reset = 1'b0;

#180 reset = 1'b1;

for 4 bit #10 reset = 1'b0;

#20 $stop;
counter end
initial // Monitor the outputs
$monitor($time, " Output q = %d", q);
endmodule

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 Simulation output waveform Output

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Prof. GIRISH H ,
Associate Professor
Department of
Electronics & Communication Engineering
Cambridge Institute of Technology
Mobile: 9741122667
Email: girish.ece@cambridge.edu.in

Department of Electronics & Communicationwww.cambridge.edu.in

Engineering www.cambridge.edu.in