EN3542 Digital System Design

Hardware Description
Languages - I
Ajith Pasqual
pasqual@ent.mrt.ac.lk
Dept. of Electronic & Telecommunication Engineering
B.Sc. Engineering
Semester 5 module
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References
Verilog for Digital Design Frank Vahid
Verilog HDL A Guide to Digital Design and
Synthesis Samir Palnitkar
Examples taken from Digital Design by Morris
Mano

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Section 1 : Contents

Introduction to HDL
Verilog
Combinational Logic Design
Digital Design with Verilog

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HDL - Introduction

Could be an
ASIC, FPGA or
CPLD.

HDL is a language that describes the hardware

of digital systems in a textual form. It is a device
independent representation.
It resembles a programming language, but is
specifically oriented to describing hardware
structures and behaviours.
The main difference with the traditional
programming languages is HDLs representation
of extensive parallel operations whereas
traditional ones represents mostly serial
operations.
The most common use of a HDL is to provide an
alternative to schematics.
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HDL Introduction (2)

When a language is used for the above purpose

(i.e. to provide an alternative to schematics), it is
referred to as a structural description in which
the language describes an interconnection of
components.
Such a structural description can be used as
input to logic simulation just as a schematic is
used.
Models for each of the primitive components are
required.
If an HDL is used, then these models can also be
written in the HDL providing a more uniform,
portable representation for simulation input.
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HDL Introduction (3)

HDL can be used to represent logic diagrams,
Boolean expressions, and other more
complex digital circuits.
Thus, in top down design, a very high-level
description of a entire system can be
precisely specified using an HDL.
This high-level description can then be refined
and partitioned into lower-level descriptions
as a part of the design process.

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HDL Introduction (4)

A major reason for the growth of the use of
HDLs is logic synthesis. (more later ..)
As a documentation language, HDL is used to
represent and document digital systems in a
form that can be read by both humans and
computers and is suitable as an exchange
language between designers.
The language content can be stored and
retrieved easily and processed by computer
software in an efficient manner.
There are two applications of HDL
processing: Simulation and Synthesis
HDL started as a Simulation

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Advantages of HDL
Allows designers to talk about what the
hardware should do without actually designing
the hardware itself, or in other words HDLs
allow designers to separate behavior from
implementation at various levels of
abstraction
Designers can develop an executable functional
specification that documents the exact behavior of
all the components and their interfaces
Designers can make decisions about cost,
performance, power, and area earlier in the design
process
Designers can create tools which automatically
manipulate the design for verification, synthesis,
optimization, etc.

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HDL Abstraction Levels

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Which one to choose ?

Designers usually use a mix of all three!
Early on in the design process they might use
mostly behavioral models. As the design is
refined, the behavioral models begin to be
replaced by dataflow models.
Finally, the designers use automatic tools to
synthesize a low-level gate-level model.

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Logic Simulation
This is the representation of the structure and
behaviour of digital logic system through the
use of a computer.
A simulator interprets the HDL description and
produces a readable output, such as a timing
diagram, that predicts how the hardware will
behave before its is actually fabricated.
Simulation allows the detection of functional
errors in a design without having to physically
create the circuit.
Errors detected during simulation can be
corrected by modifying the appropriate HDL
statements.
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Logic Simulation (2)

The stimulus that tests the functionality of the
design is called a testbench.
To simulate a digital system
Design is first described in HDL
Verified by simulating the design and checking it
with a testbench which is also written in HDL.

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Logic Synthesis
The process of automatically generating a
gate-level model from either a dataflow or a
behavioral model is called Logic Synthesis
This is the process of deriving a list of
components and their interconnections
(called a netlist) from the model of a digital
system described in HDL.
The gate-level netlist can be used to fabricate
an integrated circuit or to layout a printed
circuit board (PCB).
Logic Synthesis is similar to compiling a
program in a conventional high-level
language.
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Logic Synthesis (2)

The difference is that, instead of producing object
code, logic synthesis produces a database with
instructions on how to fabricate a physical piece of
digital hardware that implements the statements
described by the HDL code.
An HDL description of a system can be written at an
intermediate level referred to as a register transfer
language (RTL) level.
Using RTL, a designer can show how the data flows
between registers and how the design processes the
data.
Details of gates and their interconnections to
implement the circuit can be automatically extracted
by logic synthesis tools from RTL description.
Caveat: Not all HDL code is synthesizable!
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Logic Synthesis (3)

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Logic Synthesis (4)

Logic synthesis tool transforms an RTL
description of a circuit in an HDL into an
optimized netlist representing storage elements
and combinational logic circuits.
Subsequently, this netlist may be transformed
by using physical design tools into an actual
integrated circuit layout, which serves as the
basis for integrated circuit manufacture.
The logic synthesis tool takes care of the large
part of the details of doing a design and allows
the exploration of the cost/performance
trade-offs essential to advanced design.
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Logic Synthesis (5)

The user provides an HDL description of the circuit
to be designed as well as various constraints or
bounds on the design.
Electronic constraints provided include allowable
gate fanouts and output loading restrictions.
Area constraints typically give the maximum
permissible area that a circuit is allowed to occupy
within the IC.
Speed constraints are typically maximum
allowable values for the propagation delay on
various paths in the circuit.
Area and speed both translate into the cost of
a circuit.
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Logic Synthesis (6)

The first major step in the synthesis process
is a translation of the HDL description into an
intermediate form.
The information in this representation may be
an interconnection of generic gates and
storage elements. It may also be in an
alternate form that represents clusters logic
and interconnections between clusters.
The second major step in the synthesis
process is optimization.
Optimization can be very complex, time
consuming process for large circuits.
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Typical
Design Flow
for
Designing
VLSI IC

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Types of HDL
There are two standard HDLs that are supported
by IEEE.

VHDL (Very-High-Speed Integrated Circuits Hardware

Description Language). Sometimes referred to as
VHSIC HDL, this was developed from an initiative by
US. Dept. of Defense. (IEEE 1076)
Verilog HDL developed by Cadence Data systems
and later transferred to a consortium called Open
Verilog International (OVI). (IEEE 1364)
SystemC developed by Open SystemC Initiative
(OSCI) Open Source Standard for System Level
Design
Follows C++ syntax
Language reference available as IEEE 1666.
Conversion tools available. (E.g. Verilog to SystemC)

SystemVerilog - IEEE 1800

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A comparison of HDLs

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Verilog
Verilog HDL has a syntax that describes
precisely the legal constructs that can be used
in the language.
It uses about 100 keywords pre-defined,
lowercase, identifiers that define the language
constructs.
Example of keywords: module, endmodule,
input, output, wire, and, or, not , etc.,
Any text between two slashes (//) and the end
of line is interpreted as a comment.
Blank spaces are ignored and names are case
sensitive.
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Verilog - Module
A module is the building block in Verilog.
It is declared by the keyword module and is
always terminated by the keyword
endmodule.
Each statement is terminated with a
semicolon, but there is no semi-colon after
endmodule.

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Verilog Module (2)

HDL Example

Note the order of

module smpl_circuit(A,B,C,x,y); parameters for the
internally defined
input A,B,C;
primitives.
output x,y;
All instances are executed
wire
e;
concurrently.
and
g1(e,A,B);
not
g2(y,C);
All ports have an implicit
or
g3(x,e,y);
declaration as wire
(compare with reg later)
endmodule

Keyword wire:
Nets represent connections between hardware elements.
They are continuously driven by output of connected
devices. They are declared using the keyword wire.
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Verilog Module (3)

Gate Delays:

Sometimes it is necessary to specify the amount of

delay from the input to the output of gates.
In Verilog, the delay is specified in terms of time units
and the symbol #.
The association of a time unit with physical time is
made using timescale compiler directive.
Compiler directive starts with the backquote (`)
symbol.
`timescale 1ns/100ps

The first number specifies the unit of measurement

for time delays.
The second number specifies the precision for which
the delays are rounded off, in this case to 0.1ns.
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Verilog Module (4)

//HDL Example 3-2
//-------------------------------- //Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
What happens if
you try to
wire e;
synthesize this
and #(30) g1(e,A,B);
code?
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule
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Verilog Module (5)

In order to simulate a circuit with HDL, it is
necessary to apply inputs to the circuit for the
simulator to generate an output response.
An HDL description that provides the stimulus
to a design is called a testbench.
Inputs are specified with reg keyword and
outputs are specified with wire.
The initial statement specifies inputs between
the keyword begin and end.
Initially ABC=000 (A,B and C are each set to
1b0 (one binary digit with a value 0).
$finish is a system task.
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Verilog Module (6)

/HDL Example 3-3
//--------------------- //Stimulus for simple circuit
module stimcrct;
reg A,B,C;
wire x,y;
circuit_with_delay cwd(A,B,C,x,y);
initial
Test Vector
begin
A = 1'b0; B = 1'b0; C = 1'b0;
#100
A = 1'b1; B = 1'b1; C = 1'b1;
#100 $finish;
end
endmodule
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module circuit_with_delay (A,B,C,x,y);

input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule
Sized Numbers:

<size><base_format><number>
Size : Number of bits (always in
bits irrespective of Base Format)

4b1111

12HABC
6Hx [ x Uknown]
8bz [z High Impedance]

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Verilog Module (6)

In the above example, cwd is declared as one instance

circuit_with_delay. (similar in concept to object<->class
relationship)

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Verilog testbench

A setup for applying test vectors to test a design.

Why should testbench input values declared as reg type?

Data items for the inputs will be written by the testbench
and should hold their values between assignments.
In contrast, the outputs will simply derive their values from
the module outputs and thus require wire nets.
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More about modules ..

E.g. 1 : Module for a 4-bit adder
module adder (A,B,sum,Cout);
input [3:0] A,B;
output Cout;
output [3:0] sum;
// Adder code
assign sum = A+B;
endmodule
E.g. 2: ANSI C-style
module adder ( input [3:0] A,B,
output [3:0] sum,
output Cout);
//Adder Code
endmodule

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E.g. 3: 4 bit adder with

Carry In and Carry Out
module
adder_cin_cout(A,B,sum,ci,
cout);
input [3:0] A,B;
input cin;
output [3:0] sum;
output cout;
assign {cout, sum} = A + B +
cin;
endmodule

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Verilog Module (7)

Bitwise Verilog Operators

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Verilog Module (8)

Boolean Expressions:
These are specified in Verilog HDL with a
continuous assignment statement consisting
of the keyword assign followed by a Boolean
Expression.
The earlier circuit can be specified using the
statement:
assign x = (A & B) | ~C)
E.g. x = A + BC + BD
y = BC + BCD

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Verilog Module (9)

//HDL Example 3-4
//----------------------------- //Circuit specified with Boolean equations
module circuit_bln (x,y,A,B,C,D);
input A,B,C,D;
output x,y;
assign x = A | (B & C) | (~B & C);
assign y = (~B & C) | (B & ~C & ~D);
endmodule
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Verilog Module (10)

User Defined Primitives (UDP):
The logic gates used in HDL descriptions with
keywords and, or,etc., are defined by the system
and are referred to as system primitives.
The user can create additional primitives by
defining them in tabular form.
These type of circuits are referred to as userdefined primitives.
UDPs do not use the keyword module. Instead
they are declared with the keyword primitive.
There can be only one output and it must be
listed first in the port list and declared with with
an output keyword.

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Verilog Module (12)

UDP features .
There can be any number of inputs. The order
in which they are listed in the input
declaration must conform to the order in which
they are given values in the table that follows.
The truth table is enclosed within the
keywords table and endtable.
The values of the inputs are listed with a colon
(:). The output is always the last entry in a row
followed by a semicolon (;).
It ends with the keyword endprimitive.
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Verilog Module (13)

//HDL Example 3-5

//----------------------------------//User defined primitive(UDP)
primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms (0,2,4,6,7)
table
// A B C : x (Note that this is only a comment)
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
// Instantiate primitive
0 1 1 : 0;
Module declare_crctp;
1 0 0 : 1;
1 0 1 : 0;
reg
x,y,z;
1 1 0 : 1;
1 1 1 : 1;
wire
w;
endtable
endprimitive
crctp testcct(w,x,y,z);

endmodule
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Verilog Module (14)

A module can be described in any one (or a
combination) of the following modeling
techniques.
Gate-level modeling using instantiation of
primitive gates and user defined modules.

This describes the circuit by specifying the gates and how

they are connected with each other.

Dataflow modeling using continuous assignment

statements with the keyword assign.
This is mostly used for describing combinational circuits.

Behavioral modeling using procedural

assignment statements with keyword always.

This is used to describe digital systems at a higher level

of abstraction.

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Gate-Level Modeling
Here a circuit is specified by its logic gates
and their interconnections.
It provides a textual description of a
schematic diagram.
Verilog recognizes 12 basic gates as
predefined primitives.

4 primitive gates of 3-state type.

Other 8 are : and, nand, or, nor, xor, xnor, not,
buf

When the gates are simulated, the system

assigns a four-valued logic set to each gate
0,1,unknown (x) and high impedance (z)
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Gate-level modeling (2)

When a primitive gate is incorporated into a
module, we say it is instantiated in the
module.
In general, component instantiations are
statements that reference lower-level
components in the design, essentially
creating unique copies (or instances) of those
components in the higher-level module.
Thus, a module that uses a gate in its
description is said to instantiate the gate.

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Gate-level Modeling (3)

Modeling with vector data (multiple bit
widths):

A vector is specified within square brackets and

two numbers separated with a colon.
E.g. output
[3:0]D; - This declares an output
vector D with 4 bits 0 through 3.
wire
[7:0]SUM This declares a wire
vector SUM with 8 bits numbered 7 through 0.
The first number listed is the most significant bit of
the vector.

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Gate-level Modeling

Two or more modules can be combined to build a

hierarchical description of a design.
There are two basic types of design methodologies.
Top down : In top-down design, the top level block is
defined and then sub-blocks necessary to build the top
level block are identified.
Bottom up : Here the building blocks are first identified
and then combine to build the top level block.

In a top-down design, a 4-bit binary adder is

defined as top-level block with 4 full adder blocks.
Then we describe two half-adders that are required
to create the full adder.
In a bottom-up design, the half-adder is defined,
then the full adder is constructed and the 4-bit
adder is built from the full adders.

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Gate-level Modeling
A bottom-up hierarchical description of a 4-bit
adder is described in Verilog as

Half adder is defined by instantiating primitive

gates.
Then define the full adder by instantiating two halfadders.
Finally the third module describes 4 bit adder by
instantiating 4 full adders.

Note: In Verilog, one module definition cannot

be placed within another module description.

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4 bit Full Adder

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4 bit Full Adder

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//HDL Example 4-2

//----------------------------------------------//Gate-level hierarchical description of 4-bit adder
// Description of half adder (see Fig 4-5b)
module halfadder (S,C,x,y);
input x,y;
output S,C;
//Instantiate primitive gates
xor (S,x,y);
and (C,x,y);
endmodule

4 bit Full
Adder

//Description of full adder (see Fig 4-8)

module fulladder (S,C,x,y,z);
input x,y,z;
output S,C;
wire S1,D1,D2; //Outputs of first XOR and two AND gates
//Instantiate the halfadder
halfadder HA1 (S1,D1,x,y),
HA2 (S,D2,S1,z);
or g1(C,D2,D1);
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//Description of 4-bit adder (see Fig 4-9)

module _4bit_adder (S,C4,A,B,C0);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3; //Intermediate carries
//Instantiate the fulladder
fulladder FA0 (S[0],C1,A[0],B[0],C0),
FA1 (S[1],C2,A[1],B[1],C1),
FA2 (S[2],C3,A[2],B[2],C2),
FA3 (S[3],C4,A[3],B[3],C3);
endmodule

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Three-State Gates

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Three-State Gates

Three-state gates have a control input that can

place the gate into a high-impedance state.
(symbolized by z in HDL).
The bufif1 gate behaves like a normal buffer if
control=1. The output goes to a high-impedance
state z when control=0.
bufif0 gate behaves in a similar way except that
the high-impedance state occurs when control=1
Two not gates operate in a similar manner except
that the o/p is the complement of the input when
the gate is not in a high impedance state.
The gates are instantiated with the statement
gate name (output, input, control);

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Three-State Gates
The output of 3-state
gates can be connected
together to form a
common output line. To
identify such connections,
HDL uses the keyword tri
(for tristate) to indicate
that the output has
multiple drivers.

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module muxtri (A,B,select,out);

input
A,B,select;
output
OUT;
tri
OUT;
bufif1 (OUT,A,select);
bufif0 (OUT,B,select);
endmodule
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Three-State Gates

Keywords wire and tri are examples of net data type.

Nets represent connections between hardware elements.
Their value is continuously driven by the output of the
device that they represent.
The word net is not a keyword, but represents a class of
data types such as wire, wor, wand, tri, supply1, and
supply0.
The wire declaration is used most frequently.
The net wor models the hardware implementation of the
wired-OR configuration.
The wand models the wired-AND configuration.
The nets supply1 and supply0 represent power supply
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and
ground.
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Combination System Design

1. From the specifications of the circuit,
determine the required number of inputs and
outputs, and assign a letter symbol to each.
2. Derive the truth table that defines the
required relationship between inputs and
outputs.
3. Obtain the simplified Boolean functions for
each output as a function of the input
variables.
4. Draw the logic diagram.
5. Verify the correctness of the design.
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Data Flow Modelling

Dataflow modeling enables the designer to
focus on where the state is in the design and
how the data flows between these state
elements without going into gate-level details
Continuous assignments are used to connect
combinational logic to nets and ports

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Dataflow Modeling
Dataflow modeling uses a number of
operators that act on operands to produce
desired results.
Verilog HDL provides about 30 operator types.
Dataflow modeling uses continuous
assignments and the keyword assign.
A continuous assignment is a statement that
assigns a value to a net.
The value assigned to the net is specified by
an expression that uses operands and
operators.
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Dataflow Modeling (2)

//Dataflow description of a 2-to-4-line decoder
//See Fig.4-19
module decoder_df (A,B,E,D);
input A,B,E;
output [0:3] D;
assign D[0] = ~(~A & ~B & ~E),
D[1] = ~(~A & B & ~E),
D[2] = ~(A & ~B & ~E),
D[3] = ~(A & B & ~E);
endmodule

A 2-to-1 line multiplexer with data inputs A and

B, select input S, and output Y is described
with the continuous assignment
assign Y = (A & S) | (B & ~S)
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Dataflow Modeling (3)

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//Dataflow description of 4-bit adder

module binary_adder (A,B,Cin,SUM,Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout,SUM} = A + B + Cin;
endmodule
//Dataflow description of a 4-bit comparator.
module magcomp (A,B,ALTB,AGTB,AEQB);
input [3:0] A,B;
output ALTB,AGTB,AEQB;
assign ALTB = (A < B),
AGTB = (A > B),
AEQB = (A == B);
endmodule

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Dataflow Modeling (4)

The addition logic of 4 bit adder is described
by a single statement using the operators of
addition and concatenation.
The plus symbol (+) specifies the binary
addition of the 4 bits of A with the 4 bits of B
and the one bit of Cin.
The target output is the concatenation of the
output carry Cout and the four bits of SUM.
Concatenation of operands is expressed
within braces and a comma separating the
operands. Thus, {Cout,SUM} represents the
5-bit result of the addition operation.
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Dataflow Modeling (5)

Dataflow Modeling provides the means of

describing combinational circuits by their
function rather than by their gate structure.
Conditional operator (?:)
condition ? true-expression : false-expression;

A 2-to-1 line multiplexer

assign OUT = select ? A : B;

//Dataflow description of 2-to-1-line multiplexer
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule

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Dataflow Modelling (6)

Continuous assignments are used to connect
combinational logic to nets and ports
Concatenation:
Using { }
E.g.

assign signal [3:0] = { a, b, 2b00 }

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Writing a testbench
A testbench is an HDL program used for
applying stimulus to an HDL design in order to
test it and observe its response during
simulation.
In addition to the always statement, testbenches
use the initial statement to provide a stimulus to
the circuit under test.
The always statement executes repeatedly in a
loop. The initial statement executes only once
starting from simulation time=0 and may
continue with any operations that are delayed by
a given number of units as specified by the
symbol #.
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Writing a testbench (2)

initial
begin
A=0; B=0;
#10
A=1;
#20
A=0;
end

B=1;

The block is enclosed between begin and end. At time=0,

A and B are set to 0. 10 time units later, A is changed to 1.
20 time units later (at t=30) a is changed to 0 and B to 1.
Inputs to a 3-bit truth table can be generated with the
initial block
initial

begin
D = 3b000;
repeat (7);
#10
D = D + 3b001;
end

The 3-bit vector D is initialized to 000 at time=0. The keyword repeat

specifies looping statement: one is added to D seven times, once
every 10 time units.
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Writing a Testbench (3)

A stimulus module is an HDL program that has the

following form.

module testname
Declare local reg and wire identifiers
Instantiate the design module under test.
Generate stimulus using initial and always statements
Display the output response.
endmodule

A test module typically has no inputs or outputs.

The signals that are applied as inputs to the design
module for simulation are declared in the stimulus
module as local reg data type.
The outputs of the design module that are displayed for
testing are declared in the stimulus model as local wire
data type.
The module under test is then instantiated using the
local identifiers.
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Writing a Testbench (4)

The stimulus model generates inputs for the design module

by declaring identifiers TA and TB as reg data type, and
checks the output of the design unit with the wire identifier
TC. The local identifiers are then used to instantiate the
design module under test.
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Writing a Test-Bench (5)

The response to the stimulus generated by the initial and

always blocks will appear at the output of the simulator as
timing diagrams.
It is also possible to display numerical outputs using
Verilog system tasks.

$display display one-time value of variables or strings with

end-of-line return,
$write same $display but without going to next line.
$monitor display variables whenever a value changes
during simulation run.
$time displays simulation time
$finish terminates the simulation

The syntax for $display,$write and $monitor is of the form

Task-name (format-specification, argument list);
E.g. $display(%d %b %b, C,A,B);
$display(time = %0d A = %b B=%b,$time,A,B);
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Writing a Test-Bench (6)

//Stimulus for mux2x1_df.

module testmux;
reg TA,TB,TS; //inputs for mux
wire Y;
//output from mux
mux2x1_df mx (TA,TB,TS,Y); // instantiate mux
initial
begin
TS = 1; TA = 0; TB = 1;
#10 TA = 1; TB = 0;
#10 TS = 0;
#10 TA = 0; TB = 1;
end
initial
$monitor("select = %b A = %b B = %b OUT = %b time = %0d",
TS, TA, TB, Y, $time);
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endmodule
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//Dataflow description of 2-to-1-line multiplexer
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule

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Descriptions of Circuits
Structural Description This is directly
equivalent to the schematic of a circuit and is
specifically oriented to describing hardware
structures using the components of a circuit.
Dataflow Description This describes a
circuit in terms of function rather than
structure and is made up of concurrent
assignment statements or their equivalent.
Concurrent assignments statements are
executed concurrently, i.e. in parallel
whenever one of the values on the right hand
side of the statement changes.
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Descriptions of Circuits (2)

Hierarchical Description Descriptions that
represent circuits using hierarchy have
multiple entities, one for each element of the
Hierarchy.
Behavioural Description This refers to a
description of a circuit at a level higher than
the logic level. This type of description is also
referred to as the register transfer level.

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4-to-1 Multiplexer

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4-to-1 Multiplexer

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4-to-1 Multiplexer Data Flow

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4-to-1 Multiplexer

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Hierarchical Modelling
A module can contain other modules through
module instantiation creating a module
hierarchy
Modules are connected together with nets
Ports are attached to nets either by position or by
name

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Adder

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4-bit Adder

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4-bit-Adder

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