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    Lectures On Central Processing Unit

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    viihaanghtrivedi
    The document discusses the major components of the central processing unit (CPU). It covers topics like general register set organization, stack organization using PUSH and POP operations, reverse polish notation for expression evaluation, different instruction formats like one, two, and three address instructions, addressing modes, data transfer and manipulation instructions, program control instructions like conditional branches and interrupts. It also compares the characteristics of RISC and CISC architectures.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Lectures On Central Processing Unit

    Uploaded by

    viihaanghtrivedi
    24 views40 pages
    The document discusses the major components of the central processing unit (CPU). It covers topics like general register set organization, stack organization using PUSH and POP operations, reverse polish notation for expression evaluation, different instruction formats like one, two, and three address instructions, addressing modes, data transfer and manipulation instructions, program control instructions like conditional branches and interrupts. It also compares the characteristics of RISC and CISC architectures.

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    Original Title

    COA_UNIT 5

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    The document discusses the major components of the central processing unit (CPU). It covers topics like general register set organization, stack organization using PUSH and POP operations, reverse polish notation for expression evaluation, different instruction formats like one, two, and three address instructions, addressing modes, data transfer and manipulation instructions, program control instructions like conditional branches and interrupts. It also compares the characteristics of RISC and CISC architectures.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    24 views40 pages

    Lectures On Central Processing Unit

    Uploaded by

    viihaanghtrivedi
    The document discusses the major components of the central processing unit (CPU). It covers topics like general register set organization, stack organization using PUSH and POP operations, reverse polish notation for expression evaluation, different instruction formats like one, two, and three address instructions, addressing modes, data transfer and manipulation instructions, program control instructions like conditional branches and interrupts. It also compares the characteristics of RISC and CISC architectures.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 40

    Lectures on

    Central Processing Unit


    UNIT 5
    Major Components of CPU
    General Register Set Organization
    General Register Set Organization (contd…)
    General Register Set Organization
    For Example:
    General Register Set Organization
    Register Selection Fields
    Stack organization
    PUSH & POP
     PUSH:
    Initially SP is 0(Zero), EMTY 1 and FULL 0.
    Micro operations:

    SP SP+1 Increment Stack Pointer


    M[SP] DR Write data on Top of the stack
    If(SP==0) then FULL 1 If stack is full then make
    FULL 1
    EMTY 0 Mark the stack not Empty
    PUSH & POP (Contd..)

     POP:
    Memory Stack
    Memory Stack (Contd..)

     A new Data insertion using PUSH:


    Memory Stack (Contd..)

     A new data deletion from stack using POP:


    Reverse Polish Notation (RPN)

    For Example:

    A*B + C*D is written as AB * CD * +


    Reverse Polish Notation (RPN)

     Expression Evaluation example with stack operations: (3*4) + (5*6)


     34 * 56 * +
    Instruction Formats

    Most Computers fall into three types of CPU organizations:


    1. Single Accumulator Organization.
    2. General register Organization
    3. Stack Organization
    Example:

     To understand different types of organization instruction formats we


    consider following example:

    X=(A+B) * (C+D)
    Three Address Instructions:
    Two Address Instructions
    One Address Instructions
    Zero Address Instructions
    RISC Instructions:
    Addressing Modes:

     Implied Mode
     Immediate Mode
     Register Mode
     Register Indirect Mode
     Auto increment or Auto decrement mode
     Direct Address Mode
     Indirect Address mode
     Relative Address Mode
     Index Addressing Mode
     Base Register Addressing Mode
    Addressing Modes Example WRT instructions
    Data Transfer and Manipulation

     Data Transfer
     Data Manipulation
     Program Control
    Data Transfer Instructions
    Data Manipulation Instructions

     Arithmetic Instructions
     Logic Instructions
     Shift Operations
    Arithmetic Instructions
    Logic and bit manipulation Instructions
    Shift Operations
    Program Control
    Program Control

     Status bit Conditions (PSW)


    C Carry bit
    S Sign Bit
    Z  Zero Flag
    V  Overflow Flag
    Conditional Branch Instructions
    Subroutine call & Return

    CALL:

    RET:
    Interrupt

     Is it similar to subroutine?
    3 basic differences:
    1. Initiated by internal or External Signal rather than an instruction
    from program
    2. Address of Interrupt Service Routine is determined by Hardware
    3. An Interrupt procedure usually stores all the information
    necessary to define the state of CPU
    Types of Interrupt:

    1. External Interrupt : come from I/o devices, timing


    devices, monitoring circuits or External devices.
    2. Internal Interrupt : illegal or erroneous use of instruction
    or data (also known as traps) Ex: divide by Zero
    Types of Interrupt:

    3. Software Interrupt: initiated by executing an


    Instruction.
     It is a special call instruction that behaves like
    interrupt.
    The most common example is supervisor call
    instruction used to enter Supervisor mode.
    RISC VS CISC (Comparison using
    Characteristics)
    RISC CISC
    Few Instructions A large number of Instructions
    Few Addressing Modes More Addressing modes are possible
    Memory access is limited to LOAD and Some instructions are for specialized task
    STORE instructions only.

    All operations done within the registers of Instructions are available that manipulate
    the CPU operands in memory

    Fixed length easily decoded instruction Variable length Instruction Format


    format

    Single cycle instruction execution Variable cycle Instruction execution


    Hardwired rather than micro programmed Micro programmed control preferable
    control
    Other Characteristics of RISC:

     Large number of Registers.


     Efficient Instruction Pipeline
     Overlapped Register Windows
     CompilerSupport for efficient translation of High level
    Language Programming into Machine language.

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