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    Modelling of SOI-LDMOS Transistor

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    chaitudsc
    The document describes the modeling of an SOI-LDMOS transistor. It builds on the MM20 MOSFET model by including a drift region to model the transistor's high voltage characteristics. The model divides the transistor into three regions - the channel, drift, and high voltage regions. It models the drift region using the MM40 model and represents the overall LDMOS structure as a MOSFET in conjunction with a resistor and diode. Simulation results are presented showing the effects of varying oxide material, channel length, and gate voltages on the transistor's V-I characteristics.

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    Modelling of SOI-LDMOS Transistor

    Uploaded by

    chaitudsc
    129 views13 pages
    The document describes the modeling of an SOI-LDMOS transistor. It builds on the MM20 MOSFET model by including a drift region to model the transistor's high voltage characteristics. The model divides the transistor into three regions - the channel, drift, and high voltage regions. It models the drift region using the MM40 model and represents the overall LDMOS structure as a MOSFET in conjunction with a resistor and diode. Simulation results are presented showing the effects of varying oxide material, channel length, and gate voltages on the transistor's V-I characteristics.

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    ldmos model

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    The document describes the modeling of an SOI-LDMOS transistor. It builds on the MM20 MOSFET model by including a drift region to model the transistor's high voltage characteristics. The model divides the transistor into three regions - the channel, drift, and high voltage regions. It models the drift region using the MM40 model and represents the overall LDMOS structure as a MOSFET in conjunction with a resistor and diode. Simulation results are presented showing the effects of varying oxide material, channel length, and gate voltages on the transistor's V-I characteristics.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    129 views13 pages

    Modelling of SOI-LDMOS Transistor

    Uploaded by

    chaitudsc
    The document describes the modeling of an SOI-LDMOS transistor. It builds on the MM20 MOSFET model by including a drift region to model the transistor's high voltage characteristics. The model divides the transistor into three regions - the channel, drift, and high voltage regions. It models the drift region using the MM40 model and represents the overall LDMOS structure as a MOSFET in conjunction with a resistor and diode. Simulation results are presented showing the effects of varying oxide material, channel length, and gate voltages on the transistor's V-I characteristics.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 13

    Modelling of SOI-LDMOS Transistor

    D.Sai.Chaitanya
    14311D6823
    VLSI and Embedded Systems
    The LDMOS model is build on the basis of MM20 MOSFET model.

    This model describes the characteristics of the MOSFET where the drain and source of the device are
    at longer distance than the conventional MOSFET.

    Next step in this model is to extend this structure by including the drift region through which the
    high voltage performance characteristics are obtained.

    MM20 model includes the channel region and the drift region which is the basic structure of
    LDMOS region 1 and region 2.
    Now in order to include the high voltage operation region that is the drift region which is under no
    gate control is modeled by using the MM40 MOSFET model which includes the required region.

    Thus the three regions are now model and the LDMOS basic model is obtained.
    Basic High voltage MOSFET strategy is shown below

    The LDMOS model thus can be modeled as a mosfet in conjunction with the resistor which is to
    model the drift region and the diode part which is formed between base and channel region, these are
    shown in the below figure.
    The design that was modelled to study the characteristics of LDMOS is shown below

    The LDMOS has a channel length of 1.8um and it is Silicon on insulator LDMOS with insulator as
    silicon dioxide
    The V-I characteristics of the shown ldmos are obtained and by changing parameters like the channel
    length , oxide and gate length.
    The graphs of Vds vs Id and Vgs vs Id for two oxides and two different channel lengths are obtained.
    The two oxides used are halfnioum oxide and silicon dioxide.
    The two channel lengths are 1.8um and 2.2 um.
    Results
    The below graph show the Vds vs Id graph with channel length of 1.8um and two different oxide
    materials i.e. SiO2 and HfO2. Vgs voltages are 5v and 10v.
    The below graph show the Vds vs Id graph with channel length of 2.2 um and two different oxide
    materials i.e. SiO2 and HfO2, Vgs voltages are 5v and 10v.
    The below graph show the Vgs vs Id graph with channel length of 1.8 um and two different oxide
    materials i.e. SiO2 and HfO2, Vds voltages are 5v and 10v.
    The below graph show the Vgs vs Id graph with channel length of 2.2um and two different oxide
    materials i.e. SiO2 and HfO2, Vds voltages are 5v and 10v.
    The circuit level model of the LDMOS is shown below

    Thus the LDMOS is modelled by considering the charge equations and including the quasi-saturation effect
    REFERENCE
    Title: Modelling of LDMOS Transistor
    Name: D.S.Chaitanya
    Roll. No.: 14311D6823
    Specialization: VLSI & Embedded System
    [1] Nitin Prasad, Prasad Sarangapani ,Amitava DasGupta and Anjan Chakravorty, An Improved Quasi-
    Saturation and Charge Model for SOI-LDMOS Transistors. IEEE Transactions on Electon Devices, Vol. 62, No.
    3, March 2015.
    [2] P. M. Holland and P. M. Igic, An alternative process architecture for CMOS based high side RESURF LDMOS
    transistors, in International Conf. Microelectron., 2006.
    [3] A. Aarts, N. DHalleweyn, and R. van Langevelde, A surfacepotential-based high-voltage compact LDMOS
    transistor model, IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 9991007, May 2005.
    [4] A. C. T. Aarts and A. Tajic, MM20 HVMOS model: A surface-potential-based LDMOS model for circuit
    simulation, in POWER/HVMOS Devices Compact Modeling. Amsterdam, The Netherlands: Springer-Verlag,
    2010.
    [5] T. Lekshmi, A. K. Mittal, A. DasGupta, A. Chakravorty, and N. DasGupta, Compact modeling of SOI-LDMOS
    including quasisaturation effect, in Proc. 2nd Int. Workshop Electron Devices Semiconductor. Technol. (IEDST),
    Jun. 2009.
    [6] U. Radhakrishna, A. DasGupta, N. DasGupta, and A. Chakravorty, Modeling of SOI-LDMOS transistor
    including impact ionization, snapback, and self-heating, IEEE Trans. Electron Devices, vol. 58, no. 11, Nov.
    2011.
    [7] Y. Oritsuki et al., HiSIM-HV: A compact model for simulation of high-voltage MOSFET circuits, IEEE Trans.
    Electron Devices, vol. 57, Oct. 2010.
    [8] A. Tanaka et al., Quasi-2-dimensional compact resistor model for the drift region in high-voltage LDMOS
    devices, IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 20722080, Jul. 2011.

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