Vlsi Technology PDF
Vlsi Technology PDF
Vlsi Technology PDF
TECHNOLOGY
VLSI
TECHNOLOGY
Editor-in-Chief
Wai-Kai Chen
C RC P R E S S
Boca Raton London New York Washington, D.C.
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The purpose of VLSI Technology is to provide, in a single volume, a comprehensive reference work covering
the broad spectrum of VLSI processes, semiconductor technology, micromachining, microelectronics
packaging, compound semiconductor digital integrated circuit technology, and multichip module tech-
nologies. The book has been written and developed for practicing electrical engineers in industry,
government, and academia. The goal is to provide the most up-to-date information in the field.
Over the years, the fundamentals of the field have evolved to include a wide range of topics and a
broad range of practice. To encompass such a wide range of knowledge, the book focuses on the key
concepts, models, and equations that enable the design engineer to analyze, design, and predict the
behavior of large-scale systems. While design formulas and tables are listed, emphasis is placed on the
key concepts and the theories underlying the processes.
The book stresses fundamental theory behind professional applications. In order to do so, the text is
reinforced with frequent examples. Extensive development of theory and details of proofs have been
omitted. The reader is assumed to have a certain degree of sophistication and experience. However, brief
reviews of theories, principles, and mathematics of some subject areas are given.
The compilation of this book would not have been possible without the dedication and efforts of
Krishna Shenai and Stephen I. Long, and, most of all, the contributing authors. I wish to thank them all.
Wai-Kai Chen
Editor-in-Chief
v
Editor-in-Chief
vii
Contributors
ix
Stephen I. Long Philip G. Neudeck
University of California NASA Glenn Research Center
Santa Barbara, California Cleveland, Ohio
x
Contents
xi
5 SiGe Technology John D. Cressler
5.1 Introduction ..........................................................................................................................5-1
5.2 SiGe Strained Layer Epitaxy ..................................................................................................5-1
5.3 The SiGe Heterojunction Bipolar Transistor (HBT)............................................................5-3
5.4 The SiGe Heterojunction Field Effect Transistor (HFET) ...................................................5-8
5.5 Future Directions.................................................................................................................5-10
Acknowledgments..........................................................................................................................5-11
References ......................................................................................................................................5-11
xii
9.4 Chip Noise ...........................................................................................................................9-10
9.5 Future Trends ......................................................................................................................9-17
9.6 Conclusions .........................................................................................................................9-19
References ......................................................................................................................................9-19
xiii
12.11 Assembly Techniques .........................................................................................................12-9
12.12 Summary ...........................................................................................................................12-12
References ....................................................................................................................................12-12
17 Logic Design Examples Charles E. Chang, Meera Venkataraman, and Stephen I. Long
17.1 Design of MESFET and HEMT Logic Circuits ...................................................................17-1
17.2 HBT Logic Design Examples.............................................................................................17-10
References ....................................................................................................................................17-25
Index................................................................................................................ I-1
xiv
1
VLSI Technology: A
System Perspective
1.1 Introduction
The development of VLSI systems has historically progressed hand-in-hand with technology innova-
tions. Often, fresh achievements in lithography, or semiconductor devices, or metallization have led
to the introduction of new products. Conversely, market demand for particular products or specifi-
cations has greatly influenced focused research into the technology capabilities necessary to deliver
the product. Many conventional VLSI systems as a result have engendered highly specialized technol-
ogies for their support.
In contrast, a characteristic of emerging VLSI products is the integration of diverse systems, each of
which previously required a unique technology, into a single technology platform. The driving force
behind this trend is the demand in consumer and noncommercial sectors for compact, portable, wireless
electronics products — the nascent “system-on-a-chip” era.1–4 Figure 1.1 illustrates some of the system
components playing a role in this development.
Most of the achievements in dense systems integration have derived from scaling in silicon VLSI
processes.5 As manufacturing has improved, it has become more cost-effective in many applications to
replace a chip set with a monolithic IC: packaging costs are decreased, interconnect paths shrink, and
power loss in I/O drivers is reduced. Further scaling to deep submicron dimensions will continue to
widen the applications of VLSI system integration, but also will lead to additional complexities in
reliability, interconnect, and lithography.6 This evolution is raising questions over the optimal level of
integration: package level or chip level. Each has distinct advantages and some critical deficiencies for
cost, reliability, and performance.
Board-level interconnection of chip sets, although a mainstay of low-cost, high-volume manufacturing,
cannot provide a suitably dense integration of high-performance, core VLSI systems. Package- and chip-
level integration are more practical contenders for VLSI systems implementation because of their compact
dimensions and short signal interconnects. They also offer a tradeoff between dense monolithic integra-
tion and application-specific technology optimization. It is unclear at this time of the pace in the further
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 1-1
1-2 VLSI Technology
FIGURE 1.1 These system components are representative of the essential building blocks in VLSI “systems-on-a-chip.”
evolution of VLSI systems, although systems integration will continue to influence and be influenced by
technology development.
The remainder of this chapter will trace the inter-relationship of technology and systems to date and
then outline emerging and future VLSI systems and their technology requisites. Alternative technologies
will also be introduced with a presentation of their potential impact on VLSI systems. Focused discussion
of the specific VLSI technologies introduced will follow in later chapters.
Given the level of systems integration afforded by available technology and the diverse signal-
processing capabilities and applications supported, in this chapter a “VLSI system” is loosely defined
as any complex system, primarily electronic in nature, based on semiconductor manufacturing with
an extremely dense integration of minimal processing elements (e.g., transistors) and packaged as a
single- or multi-chip module.
design methodology and their sensitivity to frequency-dependent characteristics in biasing and operation.
Digital systems consist of logic circuits and memory, although it should be noted that most “digital”
systems now also contain significant analog subsystems for data conversion and signal integrity. Power
semiconductor devices have previously afforded only very low levels of integration considering their
extreme current- and voltage-handling requirements (up to 1000 A and 10 kV) and resulting high
temperatures. However, with the advent of hybrid technologies (integrating different materials on a single
silicon substrate), partial insulating substrates (with dielectrically isolated regions for power semicon-
ductor devices), and MCM packaging, integrated “smart” power electronics are appearing for medium
power (up to 1 kW) applications. A relative newcomer to the VLSI arena is microelectromechanical
systems (MEMS). As the name states, MEMS is not purely electronic in nature and is now frequently
extended to also label systems that are based on optoelectronics, biochemistry, and electromagnetics.
Digital Systems
Introduction
The digital systems category comprises microprocessors, microcontrollers, specialized digital signal pro-
cessors, and solid-state memory. As mentioned previously, these systems may also contain analog, power,
RF, and MEMS subsystems; but in this section, discussion is restricted to digital electronics.
Beginning with the introduction in 1971 of the first true microprocessor — the Intel 4004 — digital logic
ICs have offered increasing functionality afforded by a number of technology factors. Transistor miniatur-
ization from the 10-micron dimensions common 30 years ago to state-of-the-art 0.25-micron lithography
has boosted IC device counts to over 10 million transistors. To support subsystem interconnection, multi-
level metallization stacks have evolved. And, to reduce static and switching power losses, low-power/low-
voltage technologies have become standard. The following discussion of VLSI technology pertains to the key
metrics in digital systems: power dissipation, signal delay, signal integrity, and memory integration.
Power Dissipation
The premier technology today for digital systems is CMOS, owing to its inherent low-power attributes
and excellent scaling to deep submicron dimensions. Total power dissipation is expressed as
P = P dynamic + P static
= ( P switching + P short-circuit + P leakage )
(1.1)
∑a c ∑i ∑ ( 1 – a )i
2
= V f DD n n + V DD sc n + V DD n leak n
n n n
where VDD is the operating supply; f is the clock frequency; per node an is the switching activity; cn is the
switching capacitance; iscn is the short-circuit current; and ileakn is the leakage current (subthreshold
conduction and junction leakage). From this expression it is apparent that the most significant reduction
in power dissipation can be accomplished by scaling the operating supply. However, as VDD is reduced
to 1 V, the contribution of leakage current to overall power dissipation increases if transistor VT is scaled
proportionally to VDD . Subthreshold current in bulk CMOS, neglecting junction leakage and body effects,
can be expressed as7
V GS – V T – V DS
W
-----------------------
nφ t ⎛ φt ⎞
-------------
I sub = ----- I 0 e ⎜1 – e ⎟ (1.2)
L ⎝ ⎠
where
2
I 0 = k′ ( n – 1 )φ t (1.3)
1-4 VLSI Technology
γ
n = 1 + ----------- (1.4)
2 φt
k′ = µC ox′ (1.5)
2qε S N B
γ = ---------------------
- (1.6)
C ox′
ε ox
C ox′ = -----
- (1.7)
t ox
W and L are channel width and length, respectively; φt is thermal voltage (approximately 0.259 V at 300
K); µ is carrier mobility in the channel; εox is gate dielectric permittivity (3.45 × 10–13 F/cm for SiO2); εS
is semiconductor permittivity (1.04 × 10–12 F/cm for Si); NB is bulk doping; and tox is gate dielectric
thickness. This trend is exacerbated if minimal-switching circuit techniques are employed or if sleep
modes place the logic into idle states for long periods. Device scaling thus must consider the architecture
and performance requirements.
Figures 1.2 and 1.3 show the inverse normalized energy-delay product (EDP) contours for a hypo-
thetical 0.25-micron device.8 The energy required per operation is
P
E = --- (1.8)
f
Normalization is performed relative to the best obtained EDP for this technology. Fig. 1.2 shows data
for an ideal device and Fig. 1.3 adds non-idealities by considering velocity saturation effects and uncer-
tainty in VDD , VT , and temperature T. In the ideal device, the dashed lines indicate vectors of normalized
constant performance relative to the performance obtained at the optimal EDP point. The switching
frequency can be approximated by
1 1
f = ------- = -------
t rise t fall
(1.9)
I Dsat
= ------------
-
CV DD
FIGURE 1.2 Inverse normalized EDP contours for an ideal device (after Ref. 8). Dashed lines indicate vectors of
constant performance. Arrow F shows direction of increasing performance.
VLSI Technology: A System Perspective 1-5
FIGURE 1.3 Inverse normalized EDP contours for a non-ideal device considering velocity saturation and uncer-
tainty in VDD , VT , and temperature T (after Ref. 8).
2
( V DD – V T )
f = α ---------------------------
- (1.10)
V DD
where scaling factor α is applied to normalize performance. These plots illustrate the tradeoffs in
optimizing system performance for low-power requirements and highest performance. Frequency can
also be scaled to reduce power dissipation, but this is not considered here as it generally also degrades
performance.
Considering purely dynamic power losses (CV2f), scaling the operating supply again yields the most
significant reduction; but this scaling also affects the subthreshold leakage since VT must be scaled
similarly to maintain comparable performance levels (see Eq. 1.10). In this respect, fully depleted SOI
CMOS offers improved low-voltage, low-power characteristics as it has a steeper subthreshold slope than
bulk CMOS. Subthreshold slope, S, is defined as
dV G
S = --------------------
- (1.11)
d ( log I D )
S = ------ ln ( 10 ) ⎛ 1 + ------D-⎞
k̂T C
(1.12)
q ⎝ C ox⎠
and for fully depleted SOI CMOS (assuming negligible interface states and buried-oxide capacitance) as
k̂T
S = ------ ln ( 10 ) (1.13)
q
where k̂ is Boltzmann’s constant (1.38 × 10–23 V·C/K), CD is depletion capacitance, and Cox is gate dielectric
capacitance. Hence, for the same weak inversion gate bias, SOI CMOS can yield a leakage current several
orders of magnitude less than in bulk CMOS.
Additional power dissipation occurs in the extrinsic parasitics of the active devices and the intercon-
nect. This contribution can be minimized by salicide (self-aligned silicide) processes that deposit a low
sheet resistance layer on the source, drain, and gate surfaces.
1-6 VLSI Technology
I Dsat
f = ------------
-
CV DD
k′ W 2
---- ----- ( V GS – V T )
2 L (1.14)
= ---------------------------------------
CV DD
2
( V DD – V T )
∝ ---------------------------
-
CV DD
Voltage scaling and its effects on power dissipation have already been discussed. Considering the capacitive
contribution, a linear improvement to switching speed can be obtained by scaling node capacitance.
Referring to Fig. 1.4 and neglecting interconnect capacitance, the node capacitance of a MOSFET can
be expressed as
FIGURE 1.4 A MOSFET isometric cross-sectional view with critical dimensions identified.
VLSI Technology: A System Perspective 1-7
1
C GD = x jl C ox W + --- C ox WL eff (1.16)
2
C db = C j0 WY + 2C jsw ( W + Y ) (1.17)
qε Si
C j0 = ------------------------------------ (1.18)
1 1
2 ⎛ ------- + ---------⎞ φ
⎝ N sd N sub⎠
C jsw ≈ C j0 x j (1.19)
The drain-to-body junction capacitance Cdb is bias dependent, and the scaling factor κ is included to
determine an average value of output voltage level. Source/drain diffusion capacitance has two components:
the bottom areal capacitance Cj0 and the sidewall perimeter capacitance Cjsw. Although Cjsw is a complex
function of doping profile and should account for high-concentration channel-stop implants, an approxi-
mation is made to equate Cjsw and Cj0. From Fig. 1.5, it is clear that SOI CMOS has greatly reduced device
capacitances compared to bulk CMOS by the elimination junction areal and perimeter capacitances. Another
technique in SOI CMOS for improving switching delay involves dynamic threshold voltage control
(DTMOS) by taking advantage of the parasitic lateral bipolar transistor inherent in the device structure.10
To reduce interconnect resistance, copper interconnect has been introduced to replace traditional
aluminum wires.11 Table 1.1 compares two critical parameters. The higher melting point of copper also
reduces long-term interconnect degradation from electromigration, in which energetic carriers dislodge
metal atoms creating voids or nonuniformities. Interconnect capacitance relative to the substrate is
determined by the dielectric constant, εr , and the signal velocity can be defined as
c
v = -------- (1.20)
εr
Memory Scaling
The two most critical factors determining the commercial viability of RAM products are the total power
dissipation and the chip area. For implementations in battery-operated portable electronics, the goal is
a 0.9-V operating supply — the minimum voltage of a NiCd cell. RAM designs are addressing these
objectives architecturally and technologically. SRAMs and DRAMs share many architectural features,
including memory array partitioning, reduced voltage internal logic, and dynamic threshold voltage
control. DRAM, with its higher memory density, is more attractive for embedded memory applications
despite its higher power dissipation.
Figure 1.6 shows a RAM block diagram that identifies the sources of power dissipation. The power
equation as given by Itoh et al.12 is
P = I DD V DD (1.21)
where iact is the effective current in active cells, ihld is the holding current in inactive cells, CDE is the
decoder output capacitance, CPT is the peripheral circuit capacitance, VINT is the internal voltage level,
IDCP is the static current in the peripheral circuits, and n and m define the memory array dimensions.
In present DRAMs, power loss is dominated by iact, the charging current of an active subarray; but
as VT is scaled along with the operating voltage, the subthreshold current begins to dominate. The
trend in DRAM ICs (see Fig. 1.7) shows that the dc current will begin to dominate the total active
current at about the 1-Gb range. Limiting this and other short-channel effects is necessary then to
improve power efficiency.
Figure 1.8 shows trends in device parameters. A substrate doping of over 1018 cm–3 is necessary to
reduce SCE, but this has the disadvantage of also increasing junction leakage currents. To achieve reduced
SCE at lower substrate dopings, shallow junctions (as thin as 15 nm) are formed.13
Bit storage capacitors must also be scaled to match device miniaturization but still retain adequate
noise tolerance. Alpha-particle irradiation becomes less significant as devices are scaled, due to the
reduced depletion region; but leakage currents still place a minimum requirement on bit charge.
FIGURE 1.6 RAM block diagram indicating effective currents within each subsystem.
VLSI Technology: A System Perspective 1-9
Figure 1.9 shows that required signal charge, QS, has reduced only slightly with increased memory
capacity, but cell areas have shrunk considerably. High-permittivity (high-εr) dielectrics such as Ta2O5
and BST (BaxSr1–xTiO3) are required to provide these greater areal capacitances at. reduced dimen-
sions.14 Table 1.2 lists material properties for some of the common and emerging dielectrics. In
addition to scaling the cell area, the capacitor aspect ratio also affects manufacturing: larger aspect
ratios result in non-planar interlevel dielectric and large step height variation between memory arrays
and peripheral circuitry.
1-10 VLSI Technology
Analog Systems
Introduction
An analog system is any system that processes a signal’s magnitude and phase information by a linearized
response of an active device to a small-signal input. Unlike digital signals, which exhibit a large output
signal swing, analog systems rely on a sufficiently small signal gain that the linear approximation holds
true across the entire spectrum of expected input signal frequencies. Errors in the linear model are
introduced by random process variation, intrinsic device noise, ambient noise, and non-idealities in
active and passive electronics. Minimizing the cumulative effects of these “noise” contributions is the
fundamental objective of analog and RF design.
Reflecting the multitude of permutations in input/output specifications and operating conditions, ana-
log/RF design is supported by numerous VLSI technologies. Key among these are silicon MOST, BJT, and
BiCMOS for low-frequency applications; silicon BJT for high-frequency, low-noise applications; and GaAs
MESFET for high-frequency, high-efficiency amplifiers. Newcomers to the field include GaAs and SiGe
heterojunction bipolar junction transistors (HBTs). The bandgap engineering employed in their fabrication
results in devices with significantly higher fT and fmax than in conventional devices, often at lower voltages.15–17
Finally, MEMS resonators and mechanical switches offer an alternative to active device implementations.
The most familiar application of a high-frequency system is in wireless communications, in which a
translation is performed between the high-frequency modulated carrier (RF signal) used for broadcasting
and the low-frequency demodulated signal (baseband) suitable for audio or machine interpretation.
VLSI Technology: A System Perspective 1-11
Wireless ICs long relied on package-level integration and scaling to deliver compact size and improved
efficiency. Also, low-cost commercial IC technologies previously could not deliver the necessary frequency
range and noise characteristics. This capability is now changing with several candidate technologies at
hand for monolithic IC integration. CMOS has the attractive advantage of being optimal for integration
of low-power baseband processing.
Amplifiers
Amplifiers boost the amplitude or power of an analog signal to suppress noise or overcome losses and
enable further processing. Typical characteristics include a low noise figure (NF), large (selectable) gain
(G), good linearity, and high power-added efficiency (PAE). To accommodate the variety of signal
frequencies and performance requirements, several amplifier categories have evolved. These include
conventional single-ended, differential, and operational amplifiers at lower frequencies and, at higher
frequencies, low-noise and RF power amplifiers.
A challenge in technology scaling is providing a suitable signal-to-noise ratio and adequate biasing at
a reduced operating supply. For a fixed gain, reducing the operating supply implies a similar scaling of
the input signal level, ultimately approaching the noise floor of the system and leading to greater
susceptibility to internal and external noise sources. Large-signal amplifiers (e.g., RF power amplifiers)
that exhibit a wide output swing face similar problems with linearity at a lower operating supply.
A low-noise amplifier (LNA) is the first active circuit in a receiver. A common-source configuration
of a MOSFET LNA is shown in Fig. 1.10. The input network is typically matched for lowest NF, and the
output network is matched for maximum power transfer. Input impedance is matched to the source
resistance, Rs, when18
2
ω 0 ( L 1 + L 2 )C gs = 1 (1.23)
gm L1
----------- = R s (1.24)
C gs
The gain from the input matching network to the transistor gate-source voltage is equal to Q, the quality factor
1
Q = ----------------- (1.25)
gm ω0 L1
where ω0 is the RF frequency. If only the device current noise is considered, then the LNA noise figure
can be expressed as
2 ω0 L1
NF = 1 + --- ----------
- (1.26)
3 QR s
It is observed that a larger quality factor yields a lower noise figure, but current industry practice
selects an LNA Q of 2 to 3 since increasing Q also increases the sensitivity of the LNA gain to
tolerances in the passive components. By combining Eqs. 1.24 and 1.25, the device input capacitance
Cgs can be defined
1
C gs = ---------------- (1.27)
R S Qω 0
1-12 VLSI Technology
Assuming that the transistor is in the saturation region and that Miller feedback gain is –1, the
contributions to the input capacitance are
2
C = ⎛ --- C ox
′ L eff + C gso + 2C gdo⎞ W (1.28)
⎝3 ⎠
where Cgso and Cgdo are, respectively, the gate-source and gate-drain overlap capacitances. The bias current
(assuming a reasonable value for gm) can then be obtained from
2
I Dsat = ⎛ --------
g m ⎞ L eff
------- (1.29)
⎝ 2W⎠ k′
As device dimensions are reduced, the required biasing current drops. Since cutoff frequency, fT , also improves
with smaller device dimensions, MOSFET performance in RF applications will continue to improve.
Power amplifiers, the last active circuit in a transmitter, have less stringent noise figure requirements
than an LNA since the input signal is generated locally in the transmitter chain. Instead, linearity and
PAE are more critical, particularly for variable-envelope communications protocols. RF amplifiers typi-
cally operate in class AB mode to compromise between efficiency and linearity.19 Power-added efficiency
is defined as
η
PAE = ------------- (1.30)
1
1 – ----
G
where η is the drain (collector) efficiency (usually about 40 to 75%) and G is the amplifier power gain.
This balance is highly sensitive to the precision of matching networks. Technologies such as GaAs, with
its high-resistivity substrate, and SOI, with its insulating buried oxide, are best suited for integrated RF
power amplifiers since they permit fabrication of low-loss, on-chip matching networks.
Interconnects and Passive Components
Passive components in analog and RF design have the essential role of providing biasing, energy storage,
and signal level translation. As device technology has permitted a greater monolithic integration of active
devices, a similar trend has appeared in passive components. The quality of on-chip passives, however,
has lagged behind that of high-precision discrete components. Two characteristics are required of VLSI
interconnects for RFICs: low-loss and integration of high-quality factor passives (capacitors and induc-
tors). As discussed previously, resistive losses increase the overall noise figure, lead to decreased efficiency,
and degrade the performance of on-chip passive components. Interconnect and device resistance are
VLSI Technology: A System Perspective 1-13
minimized by saliciding the gate and source/drain surfaces and appropriately scaling the metallization
dimensions. Substrate coupling losses, which also degrade quality factors of integrated passives and can
introduce substrate noise, are controlled by selecting a high-resistivity substrate such as GaAs or shielding
the substrate with an insulating layer such as in SOI.
In forming capacitors on-chip, two structures are available, using either interconnect layers or the
MOS gate capacitance. Metal-insulator-metal (MIM) and dual-poly capacitors both derive a capacitance
from a thin interlevel dielectric (ILD) layer deposited between the conducting plates. MIM capacitors
offer a higher Q than dual-poly capacitors since, even with silicidation, resistance of poly layers is higher
than in metal. Both types can suffer from imprecision caused by non-planarity in the ILD thickness
caused by process non-uniformity across the wafer.
MOS gate capacitance is less subject to variation caused by dielectric non-uniformity since the gate
oxide formation is tightly controlled and occurs before any back-end processing. MOS capacitors, how-
ever, are usually dismissed for high-Q applications out of concern for the highly resistive well forming
the bottom plate electrode. Recent work, however, has shown that salicided MOS capacitors biased into
strong inversion will achieve a Q of over 100 for applications in the range 900 MHz to 2 GHz.20
Inductors are essential elements of RFICs for biasing and matching, and on-chip integration translates
to lower system cost and reduced effects from package parasitics. However, inductors also require a large
die area and exhibit significant coupling losses with the substrate. In addition to degrading the inductor
Q, substrate coupling results in the inductor becoming a source of substrate noise. The Q of an inductor
can be defined21 as
ωL
Q = --------s . Substrate loss factor ⋅ Self-resonance factor (1.31)
Rs
where Ls is the nominal inductance and Rs is the series resistance. The substrate loss factor approaches
unity as the substrate resistance goes to either zero or infinity. This implies that the Q factor is improved
if the substrate is either short- or open-circuited. Suspended inductors achieve an open-circuited substrate
by etching the bulk silicon from under the inductor structure.22 Another approach has been to short-
circuit the substrate by inserting grounding planes (ground shields).21
Power Systems
Introduction
Power processing systems are those devoted to the conditioning, regulation, conversion, and distribution
of electrical power. Voltage and current are considered the inputs, and the system transforms the input
characteristics to the form required by the load. The distinguishing feature of these systems is the
specialized active device structure (e.g., rectifier, thyristor, power bipolar or MOS transistor, IGBT)
required to withstand the electrothermal stresses imposed by the system. The label power integrated
circuits (PICs) refers to the monolithic fabrication of a power semiconductor device along with standard
VLSI electronics. At the system level, this integration has been made possible by digital control techniques
and the development of mixed-signal ICs comprising analog sensing and digital logic. On the technology
side, development of the power MOSFET and IGBT led to greatly simplified drive circuits and decreased
complexity in the on-chip electronics.
Three types of PIC are identified: smart power, high-voltage ICs (HVICs), and discrete modules.
Discrete modules are those in which individual ICs for power devices and control are packaged in a
single carrier. Integration is at the package level rather than at the IC. Smart power adds a monolithic
integration of analog protection circuitry to a standard power semiconductor device. The level of inte-
gration is quite low, but the power semiconductor device ratings are not disturbed by the other electronics.
HVICs are different in that they begin from a standard VLSI process and accommodate the power
semiconductor device by manufacturing changes. HVICs are singled out for further discussion as they
are the most suitable for VLSI integration. Although the power semiconductor device ratings cannot
1-14 VLSI Technology
achieve the levels of a discrete device, HVICs are available for ratings with currents of 50 to 100 A and
voltages up to 1000 V.
Two critical technical issues faced in developing HVICs are the electrical isolation of high-power and
low-voltage electronics, and the development of high-Q passive components (e.g., capacitors, inductors,
transformers). In the following discussion, the characteristics of power semiconductor devices will not
be considered, only the issues relating to HVIC integration.
Electrical Isolation
Three types of electrical isolation are available as illustrated in Fig. 1.11.23 In junction isolation, a p+ implant
is added to form protective diodes with the n– epitaxial regions. The diodes are reverse-biased by applying
a large negative voltage (~ –1000 V) to the substrate. Problems with this isolation include temperature-
dependent diode leakage currents and the possibility of a dynamic turn-on of the diode. Additional stress
to the isolation regions and interlevel dielectric is introduced when high-voltage interconnect crosses the
isolation implants. The applied electric field in this situation can result in premature failure of the device.
A self-isolation technique can be chosen if all the devices are MOSFETs. When all devices are placed
in individual wells (a twin-tub process), all channel regions are naturally isolated since current flow is
near the oxide–semiconductor interface. The power semiconductor device and signal transistors are
fabricated simultaneously in junction and self-isolation, resulting in a compromise in performance.24 In
practice, bulk isolation techniques are a combination of junction and self-isolation since many HVICs
exhibit dynamic surges in substrate carriers, corresponding to power device switching, that may result
in latchup of low-voltage devices.25
Dielectric isolation decouples the fabrication of power and signal devices by reserving the bulk semi-
conductor for high-voltage transistors and introducing an epitaxial semiconductor layer for low-voltage
devices on a dielectric surface. Formation of the buried oxide can be accomplished either by partially
etching an SOI wafer to yield an intermittent SOI substrate or by selectively growing oxide on regions
intended for low-voltage devices, followed by epitaxial deposition of a silicon film. In addition to pro-
viding improved isolation of power semiconductor devices, the buried oxide enhances the performance
of signal transistors by reducing parasitic capacitances and chip area.26
FIGURE 1.12 Cross-sectional view of a VLSI process showing integration of magnetic layers for coil transformers.
1-16 VLSI Technology
Embedded Memory
Computer processors today are bandwidth limited with the memory interface between high-capacity
external storage and the processing units unable to meet access rates. Multimedia applications such as
3-D graphics rendering and broadcast rate video will demand bandwidths from 1 to 10 GB/s. A conven-
tional 4-Mb DRAM with 4096 sense amplifiers, a 150-ns cycle time, and a configuration of 1-M × 4-b
achieves an internal bandwidth of 3.4 GB/s; however, as this data can be accessed at the I/O pins only in
4-bit segments, external bandwidth is reduced to 0.1% of available bandwidth.
Although complex cache (SRAM) hierarchies have been devised to mask this latency, each additional
cache level introduces additional complexity and has an asymptotic performance limit. Since the band-
width bottleneck is introduced by off-chip (multiplexed) routing of signals, embedded memories are
appearing to provide full-bandwidth memory accesses by eliminating I/O multiplexing.
Integration of DRAM and logic is non-trivial as the technology optimization of the former favors
minimal bit area, a compact capacitor structure, and low leakage, but in the latter favors device perfor-
mance. Embedded DRAM therefore permits two implementations: logic fabricated in a DRAM process
or DRAM fabricated as a macro in an ASIC process.
Monolithic RFICs
Technologies for monolithic RFICs are proceeding in two directions: all-CMOS and silicon bipolar. All-
CMOS has the attractive advantages of ready integration of baseband analog and digital signal processing,
compatibility with standard analog/RF CMOS processes, and better characteristics for low-power/low-
voltage operation.31 CMOS is predicted to continue to offer suitable RF performance at operating supplies
below 1 V as long as the threshold voltage is scaled accordingly. Silicon bipolar implementations, however,
outperform CMOS in several key areas, particularly that of the receiver LNA.
A frequency-hopped spread-spectrum transceiver has been designed in a 1-micron CMOS process
with applications to low-power microcell communications.32,33 A microcell application was chosen since
the maximum output power of 20 mW limits the transmission range.
RFICs in bipolar and BiCMOS typically focus on the specific receiver components most improved by
non-CMOS implementations. A common RFIC architecture is an LNA front-end followed by a down-
mixer. Interstage filtering and matching, if required, are provided off-chip. In CMOS, a 1-GHz RFIC
achieved a conversion gain of 20 dB, an NF of 3.2 dB, an IP3 of 8 dBm, with a current drain of 9 mA
from a 3-V supply.34 A similar architecture in BiCMOS at 1 GHz achieved a conversion gain of 16 dB,
an NF of 2.2 dB, an IP3 of –10 dBm, with a current drain of 13 mA from a 5-V supply.35
VLSI Technology: A System Perspective 1-17
MEMS
Electrothermal properties of MEMS suspended or cantilevered layers are finding applications in a variety
of electromechanical systems. For example, suspended layers have been developed for a number of
purposes, including microphones,38 accelerometers, and pressure sensors. By sealing a fluid within a
MEMS cavity, pressure sensors can also serve as infrared detectors and temperature sensors. Analog
feedback electronics monitor the deflection of a MEMS layer caused by the influence of external stresses.
The applied control voltage provides an analog readout of the relative magnitude of the external stresses.
MEMS micropumps have been developed which have potential applications in medical products
(e.g., drug delivery) and automotive systems (e.g., fuel injection).39 Flow rates of about 50 µl/min at
1-Hz cycling have been achieved, but the overall area required is still large (approximately 1 cm2),
presently limiting integration. Beyond macro applications, microfluidics has been proposed as a
technique for integrated cooling of high-power and high-temperature ICs in which coolant is circulated
within the substrate mass.
Quantum Computing
Quantum computing (QC) is concerned with the probabilistic nature of quantum states, by which
a single atom can be used to “store” and “compare” multiple values simultaneously. QC has two
distinct implementations: an electronic one based on the wave-function interaction of fixed adjacent
atoms40 and a biochemical one based on mobile molecular interactions within a fluid medium.41 In
1-18 VLSI Technology
fixed systems, atom placement and stimulation are accomplished with atomic force microscopy (AFM)
and nuclear magnetic resonance (NMR), but performance as a system also requires the ability to
individually select and operate on an atom.42 Molecular systems avoid this issue by using a fluid
medium as a method of introducing initial conditions and isolating the computation from the
measurement. Computational redundancy then statistically removes measurement error and incorrect
results generated at the fluid boundaries.
Recent work in algorithms has demonstrated that QC can solve two categories of problems more
efficiently than with a classical computer science method by taking advantage of wave function indeter-
minate states. In search and factorization problems (involving a random search of N items), a classical
solution requires O(N) steps, but a QC algorithm requires only O(√N); and binary parity computations
can be improved from O(N) to O(N/2) in a QC algorithm.43
Practical implementation of QC algorithms to very large data sets is currently limited by instru-
mentation. For example, a biochemical QC system using NMR to change spin polarity has signal
frequencies of less than 1 kHz. Despite this low frequency, the available parallelism is expected to
factor (with the O(√N) algorithm) a 400-digit number in one year: greater than 3 × 10186 MOPS (mega-
operations per second).44
DNA Computing
In DNA computing, a problem set is encoded into DNA strands which then, by nucleotide matching
properties, perform MP search and comparison operations. Most comparison techniques to date rely
on conformal mapping, but some reports appearing in the literature indicate that more powerful DNA
algorithms are possible with non-conformal mapping and secondary protein interaction.45 The chal-
lenge is in developing a formal language to describe DNA computing compounded by accounting for
these secondary and tertiary effects, including protein structure and amino acid chemical properties.46
Initial work in formal language theory has shown that DNA computers can be made equivalent to a
Turing machine.47
DNA can also provide extremely dense data storage, requiring about a trillionth of the volume required
for an equivalent electronic memory: 1012 DNA strands, each 1000 units long, is equal to 1000 T bits.48
DNA computations employ up to 1020 DNA strands (over 11 million TB), well beyond the capacity of
any conventional data storage.
Molecular Computing
Molecular computers are a mixed-signal system for performing logic functions (with possible subpico-
second switching) and signal detection with an ability to evolve and adapt to new conditions. Possible
implementations include modulation of electron, proton, or photon mobility; electronic-conformation
interactions; and tissue membrane interactions.49 Table 1.3 lists some of the architectures and applications.
“Digital” cell interactions, such as found in quantum or DNA computing, provide the logic imple-
mentation. Analog processing is introduced by the non-linear characteristics of the cell interaction with
respect to light, electricity, magnetism, chemistry, or other external stimulus. Molecular systems are also
thought to emulate a neural network that can be capable of signal enhancement and noise removal.50
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2
CMOS/BiCMOS
Yasuhiro Katsumata
Tatsuya Ohguro Technology
Kazumi Inoh
Eiji Morifuji
Takashi Yoshitomi
Hideki Kimijima 2.1 Introduction ........................................................................2-1
Hideaki Nii 2.2 CMOS Technology ..............................................................2-1
Toyota Morimoto Device Structure and Basic Fabrication Process Steps • Key
Hisayo S. Momose Process Steps in Device Fabrication • Passive Device for
Analog Operation • Embedded Memory Technology
Kuniyoshi Yoshikawa
2.3 BiCMOS Technology.........................................................2-17
Hidemi Ishiuchi
2.4 Future Technology.............................................................2-18
Toshiba Corporation
Ultra-Thin Gate Oxide MOSFET • Epitaxial Channel
Hiroshi Iwai MOSFET • Raised Gate/Source/Drain Structure
Tokyo Institute of Technology 2.5 Summary............................................................................2-22
2.1 Introduction
Silicon LSIs (large-scale integrated circuits) have progressed remarkably in the past 25 years. In particular,
complementary metal-oxide-semiconductor (CMOS) technology has played a great role in the progress
of LSIs. By downsizing2 MOS field-effect-transistors (FETs), the number of transistors in a chip increases,
and the functionality of LSIs is improved. At the same time, the switching speed of MOSFETs and circuits
increases and operation speed of LSIs is improved.
On the other hand, system-on-chip technology has come into widespread use and, as a result, the LSI
system requires several functions, such as logic, memory, and analog functions. Moreover, the LSI system
sometimes needs an ultra-high-speed logic or an ultra-high-frequency analog function. In some cases,
bipolar-CMOS (BiCMOS) technology is very useful.
The first part of this chapter focuses on CMOS technology as the major LSI process technology,
including embedded memory technology. The second part, describes BiCMOS technology; and finally,
future process technology is introduced.
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 2-1
2-2 VLSI Technology
FIGURE 2.1 Structure of CMOS device: (a) cross-sectional view of CMOS, (b) plain view of CMOS.
Figure 2.2 shows the basic fabrication process flow. The first process step is the formation of p tub
and n tub (twin tub) in silicon substrate. Because CMOS has two types of FETs, NMOS is formed in p
tub and PMOS in n tub.
The isolation process is the formation of field oxide in order to separate each MOSFET active area in
the same tub. After that, impurity is doped into channel region in order to adjust the threshold voltage,
Vth, for each type of FET. The gate insulator layer, usually silicon dioxide (SiO2), is grown by thermal
oxidation, because the interstate density between SiO2 and silicon substrate is small. Polysilicon is
deposited as gate electrode material and gate electrode is patterned by reactive ion etching (RIE).
The gate length, Lg, is the critical dimension because Lg determines the performance of MOSFETs and it
should be small in order to improve device performance. Impurity is doped in the source and drain regions
of MOSFETs by ion implantation. In this process step, gate electrodes act as a self-aligned mask to cover
channel layers. After that, thermal annealing is carried out in order to activate the impurity of diffused layers.
In the case of high-speed LSI, the self-aligned silicide (salicide) process is applied for the gate electrode
and source and drain diffused layers in order to reduce parasitic resistance. Finally, the metallization
process is carried out in order to form interconnect layers.
capacitance between silicon substrate and tub region. As a starting material, lightly doped (~1015
atoms/cm3) p-type substrate is generally used.
Tub Formation
Figure 2.3 shows the tub structures, which are classified into 6 types: p tub, n tub, twin tub,4 triple tub,
twin tub with buried p+ and n+ layers, and twin tub on p-epi/p+ substrate. In the case of the p tub process,
NMOS is formed in p diffusion (p tub) in the n substrate, as shown in Fig. 2.3(a). The p tub is formed
by implantation and diffusion into the n substrate at a concentration that is high enough to over-
compensate the n substrate.
The other approach is to use an n tub.5 As shown in Fig. 2.3(b), NMOS is formed in the p substrate.
Figure 2.3(c) shows the twin-tub structure4 that uses two separate tubs implanted into silicon substrate.
In this case, doping profiles in each tub region can be controlled independently, and thus neither type
of device suffers from excess doping effect.
FIGURE 2.3 Tub structures of CMOS: (a) p tub; (b) n tub; (c) twin tub; (d) triple tub; (e) twin tub with buried
p+ and n+ layers; and (f) twin tub on p-epi/p+ substrate.
2-4 VLSI Technology
In some cases, such as mixed signal LSIs, a deep n tub layer is sometimes formed optionally, as shown
in Fig. 2.3(d), in order to prevent the crosstalk noise between digital and analog circuits. In this structure,
both n and p tubs are electrically isolated from the substrate or other tubs on the substrate.
In order to realize high packing density, the tub design rule should be shrunk; however, an undesirable
mechanism, the well-known latch-up, might occur.
Latch-up (i.e., the flow of high current between VDD and VSS) is caused by parasitic lateral pnp
bipolar (L-BJT) and vertical npn bipolar (V-BJT) transistor actions6 as shown in Fig. 2.3(a), and it
sometimes destroys the functions of LSIs. The collectors of each of these bipolar transistors feed each
others’ bases and together make up a pnpn thyristor structure. In order to prevent latch-up, it is
important to reduce the current gain, hFE, of these parasitic bipolar transistors, and the doping
concentration of the tub region should be higher. As a result, device performance might be suppressed
because of large junction capacitances.
In order to solve this problem, several techniques have been proposed, such as p+ or n+ buried layer
under p tub7 as shown in Fig. 2.3(e), the use of high-dose, high-energy boron p tub implants,8,9 and
the shunt resistance for emitter-base junctions of parasitic bipolar transistors.7,10,11 It is also effective
to provide many well contacts to stabilize the well potential and hence to suppress the latch-up.
Recently, substrate with p epitaxial silicon on p+ substrate can also be used to stabilize the potential
for high-speed logic LSIs.12
Isolation
Local oxidation of silicon (LOCOS)13 is a widely used isolation process, because this technique can allow
channel-stop layers to be formed self-aligned to the active transistor area. It also has the advantage of
recessing about half of the field oxide below the silicon surface, which makes the surface more planar.
Figure 2.4 shows the LOCOS isolation process. First, silicon nitride and pad oxide are etched for the
definition of active transistor area. After channel implantation as shown in Fig. 2.4(a), the field oxide is
selectively grown, typically to a thickness of several hundred nanometers.
A disadvantage of LOCOS is that involvement of nitrogen in the masking of silicon nitride layer
sometimes causes the formation of a very thin nitride layer in the active region, and this often impedes
the subsequent growth of gate oxide, thereby causing low gate breakdown voltage of the oxides. In order
to prevent this problem, after stripping the masking silicon nitride, a sacrificial oxide is grown and then
removed before the gate oxidation process.14,15
In addition, the lateral spread of field oxide (bird's beak)14 poses a problem regarding reduction of the
distance between active transistor areas in order to realize high packing density. This lateral spread is
suppressed by increasing the thickness of silicon nitride and/or decreasing the thickness of pad oxide.
However, there is a tradeoff with the generation of dislocation of silicon.
FIGURE 2.4 Process for local oxidation of silicon: (a) after silicon nitride/pad oxide etch and channel-stop implant;
(b) after field oxidation, which produces an oxynitride film on nitride.
CMOS/BiCMOS Technology 2-5
FIGURE 2.5 Process flow of STI: (a) trenches are formed by RIE; (b) filling by deposition of SiO2; and (c)
planarization by CMP.
Recently, shallow trench isolation (STI)16 has become a major isolation process for advanced CMOS
devices. Figure 2.5 shows the process flow of STI. After digging the trench into the substrate by RIE as
shown in Fig. 2.5(a), the trench is filled with insulator such as silicon dioxide as shown in Fig. 2.5(b).
Finally, by planarization with chemical mechanical polishing (CMP),17 filling material on the active
transistor area is removed, as shown in Fig. 2.5(c).
STI is a useful technique for downsizing not only the distance between active areas, but also the active
region itself. However, a mechanical stress problem18 still remains, and several methods have been
proposed19 to deal with it.
Channel Doping
In order to adjust the threshold voltage of MOSFETs, Vth, to that required by a circuit design, the channel
doping process is usually required. The doping is carried out by ion implantation, usually through a thin
dummy oxide film (10 to 30 nm) thermally grown on the substrate in order to protect the surface from
contamination, as shown in Fig. 2.6. This dummy oxide film is removed prior to the gate oxidation.
Figure 2.7 shows a typical CMOS structure with channel doping. In this case, n+ polysilicon gate electrodes
are used for both n- and p-MOSFETs and, thus, this type of CMOS is called single-gate CMOS. The role
of the channel doping is to enhance or raise the threshold voltage of n-MOSFETs. It is desirable to keep
the concentration of p tub lower in order to reduce the junction capacitance of source and drain. Thus,
channel doping of p-type impurity — boron — is required. Drain-to-source leakage current in short-
channel MOSFETs flows in a deeper path, as shown in Fig. 2.8; this is called the short-channel effect.
Thus, heavy doping of the deeper region is effective in suppressing the short-channel effect. This doping
is called deep ion implantation.
In the case of p-MOSFET with an n+ polysilicon gate electrode, the threshold voltage becomes too
high in the negative direction if there is no channel doping. In order to adjust the threshold voltage, an
ultra-shallow p-doped region is formed by the channel implantation of boron. This p-doped layer is
often called a counter-doped layer or buried-channel layer, and p-MOSFETs with this structure are called
buried-channel MOSFETs. (On the other hand, MOSFETs without a buried-channel layer are called
2-6 VLSI Technology
surface-channel MOSFETs. n-MOSFETs in this case are the surface-channel MOSFETs.) In the buried-
channel case, the short-channel effect is more severe, and, thus, deep implantation of an n-type impurity
such as arsenic or phosphorus is necessary to suppress them.
In deep submicron gate length CMOS, it is difficult to suppress the short-channel effect,20 and thus,
a p+-polysilicon electrode is used for p-MOSFETs, as shown in Fig. 2.9. For n-MOSFETs, an n+-polysilicon
electrode is used. Thus, this type of CMOS is called dual-gate CMOS. In the case of p+-polysilicon p-
MOSFET, the threshold voltage becomes close to 0 V because of the difference in work function between
n- and p-polysilicon gate electrode,21–23 and thus, buried layer is not required. Instead, n-type impurity
channel doping such as arsenic is required to raise the threshold voltage slightly in the negative direction.
Impurity redistribution during high-temperature LSI manufacturing processes sometimes makes channel
profile broader, which causes the short-channel effect. In order to suppress the redistribution, a dopant
with a lower diffusion constant, such as indium, is used instead of boron.
For the purpose of realizing a high-performance transistor, it is important to reduce junction capac-
itance. In order to realize lower junction capacitance, a localized diffused channel structure,24,25 as shown
in Fig. 2.10, is proposed. Since the channel layer exists only around the gate electrode, the junction
capacitance of source and drain is reduced significantly.
Gate Insulator
The gate dielectric determines several important properties of MOSFETs and thus uniformity in its
thickness, low defect density of the film, low fixed charge and interface state density at the dielectric and
silicon interface, small roughness at the interface, high reliability of time-dependent dielectric breakdown
(TDDB) and hot-carrier induced degradation, and high resistivity to boron penetration (explained in
this section) are required. As a consequence of downsizing of MOSFET, the thickness of the gate dielectric
has become thinner. Generally, the thickness of the gate oxide is 7 to 8 nm for 0.4-µm gate length
MOSFETs, and 5 to 6 nm for 0.25-µm gate length MOSFETs.
Silicon dioxide (SiO2) is commonly used for gate dielectrics, and can be formed by several methods,
such as dry O2 oxidation,26 and wet or steam (H2O) oxidation.26 The steam is produced by the reaction
of H2 and O2 ambient in the furnace. Recently, H2O oxidation has been widely used for gate oxidation
because of good controllability of oxide thickness and high reliability.
In the case of the dual-gate CMOS structure shown in Fig. 2.9, boron penetration from the p+ gate
electrode to the channel region through the gate silicon dioxide, which is described in the following
section, is a problem. In order to prevent this problem, oxynitride has been used as the gate dielectric
material.27,28 In general, the oxynitride gate dielectric is formed by the annealing process in NH3, NO (or
N2O) after silicon oxidation, or by direct oxynitridation of silicon in NO (or N2O) ambient. Figure 2.11
shows the typical nitrogen profile of the oxynitride gate dielectric. Recently, remote plasma nitridation29,30
has been much studied, and it is reported that the oxynitride gate dielectric grown by the remote plasma
method showed better quality and reliability than that grown by the silicon nitridation method.
FIGURE 2.11 Oxygen, nitrogen, and silicon concentration profile of oxynitride gate dielectrics measured by AES.
2-8 VLSI Technology
In the regime of a sub-quarter-micron CMOS device, gate oxide thickness is close to the limitation of
tunneling current flow, around 3 nm thickness. In order to prevent tunneling current, high κ materials,
such as Si3N431 and Ta2O5,32 are proposed instead of silicon dioxide. In these cases, the thickness of the
gate insulator can be kept relatively thick because high κ insulator realizes high gate capacitance, and
thus better driving capability.
Gate Electrode
Heavily doped polysilicon has been widely used for gate electrodes because of its resistance to high-
temperature LSI fabrication processing. In order to reduce the resistance of the gate electrode, which
contributes significantly to RC delay time, silicides of refractory metals have been put on the polysilicon
electrode.33,34 Polycide,34 the technique of combining a refractory metal silicide on top of doped
polysilicon, has the advantage of preserving good electrical and physical properties at the interface
between polysilicon and the gate oxide while, at the same time, the sheet resistance of gate electrode
is reduced significantly.
For doping the gate polysilicon, ion implantation is usually employed. In the case of heavy doping,
dopant penetration from boron-doped polysilicon to the Si substrate channel region through the gate
oxide occurs in the high-temperature LSI fabrication process, as shown in Fig. 2.12. (On the other hand,
usually, penetration of an n-type dopant [such as phosphorus or arsenic] does not occur.) When the
doping of impurities in the polysilicon is not sufficient, the depletion of the gate electrode occurs as
shown in Fig. 2.13, resulting in a significant decrease of the drive capability of the transistor, as shown
in Fig. 2.14.35 There is a tradeoff between the boron penetration and the gate electrode depletion, and
so thermal process optimization is required.36
FIGURE 2.12 Dopant penetration from boron-doped polysilicon to silicon substrate channel region.
FIGURE 2.13 Depletion of gate electrode in the case that the doping of impurities in the gate electrode is not
sufficient.
CMOS/BiCMOS Technology 2-9
FIGURE 2.14 ID , gm – VG characteristics for various thermal conditions. In the case of 800°C/30 min, a significant
decrease in drive capability of transistor occurs because of the depletion of the gate electrode.
Gate length is one of most important dimensions defining MOSFET performance; thus, the lithography
process for gate electrode patterning requires high-resolution technology.
In the case of a light-wave source, the g-line (wavelength 436 nm) and the i-line (365 nm) of a mercury
lamp were popular methods. Recently, a higher-resolution process, excimer laser lithography, has been
used. In the excimer laser process, KrF (248 nm)37 and ArF (193 nm)38 have been proposed and developed.
For a 0.25-µm gate length electrode, the KrF excimer laser process is widely used in the production of
devices. In addition, electron-beam39–41 and X-ray42 lithography techniques are being studied for sub-
0.1 µm gate electrodes.
For the etching of gate polysilicon, a high-selectivity RIE process is required for selecting polysilicon
from SiO2 because a gate dielectric beneath polysilicon is a very thin film in the case of recent devices.
Source/Drain Formation
Source and drain diffused layers are formed by the ion implantation process. As a consequence of
transistor downsizing, at the drain edge (interface of channel region and drain) where reverse biased pn
junctions exist, a higher electrical field has been observed. As a result, carriers across these junctions are
suddenly accelerated and become hot carriers, which creates a serious reliability problem for MOSFET.43
In order to prevent the hot carrier problem, the lightly doped drain (LDD) structure is proposed.44 The
LDD process flow is shown in Fig. 2.15. After gate electrode formation, ion implantation is carried out to
make extension layers, and the gate electrode plays the role of a self-aligned mask that covers the channel
layer, as shown in Fig. 2.15(b). In general, arsenic is doped for n-type extension of NMOS, and BF2 for p-
type extension of PMOS. To prevent the short-channel effect, the impurity profile of extension layers must
be very shallow. Although shallow extension can be realized by ion implantation with low dose, the resistivity
of extension layers becomes higher and, thus, MOSFET characteristics degrade. Hence, it is very difficult
to meet these two requirements. Also, impurities diffusion in this extension affects the short-channel effect
significantly. Thus, it is necessary to minimize the thermal process after forming the extension.
Insulating film, such as Si3N4 or SiO2, is deposited by a chemical vapor deposition method. Then,
etching back RIE treatment is performed on the whole wafer; as a result, the insulating film remains only
at the gate electrode side, as shown in Fig. 2.15(c). This remaining film is called a sidewall spacer. This
spacer works as a self-aligned mask for deep source/drain n+ and p+ doping, as shown in Fig. 2.15(d).
In general, arsenic is doped for deep source/drain of n-MOSFET, and BF2 for p-MOSFET. In the dual-
gate CMOS process, gate polysilicon is also doped in this process step to prevent gate electrode depletion.
After that, in order to make doped impurities activate electrically and recover from implantation
damage, an annealing process, such as rapid thermal annealing (RTA), is carried out.
According to the MOSFET scaling law, when gate length and other dimensions are shrunk by factor
k, the diffusion depth also needs to be shrunk by 1/k. Hence, the diffusion depth of the extension part
is required to be especially shallow.
2-10 VLSI Technology
FIGURE 2.15 Process flow of LDD structure: (a) after gate electrode patterning; (b) extension implantation; (c)
sidewall spacer formation; and (d) source/drain implantation.
Several methods have been proposed for forming an ultra-shallow junction. For example, very low
accelerating voltage implantation, the plasma doping method,45 and implantation of heavy molecules,
such as B10H14 for p-type extension,46 are being studied.
Salicide Technique
As the vertical dimension of transistors is reduced with device downscaling, an increase is seen in sheet
resistance — both of the diffused layers, such as source and drain, and the polysilicon films, such as the
gate electrode. This is becoming a serious problem in the high-speed operation of integrated circuits.
Figure 2.16 shows the dependence of the propagation delay (tpd) of CMOS inverters on the scaling
factor, k, or gate length.47 These results were obtained by simulations in which two cases were considered.
First is the case in which source and drain contacts with the metal line were made at the edge of the
diffused layers, as illustrated in the figure inset. In an actual LSI layout, it often happens that the metal
contact to the source or drain can be made only to a portion of the diffused layers, since many other
signal or power lines cross the diffused layers. The other case is that in which the source and drain
contacts cover the entire area of the source and drain layers, thus reducing diffused line resistance. It is
clear that without a technique to reduce the diffused line resistance, tpd values cannot keep falling as
transistor size is reduced; they will saturate at gate lengths of around 0.25 microns.
In order to solve this problem — the high resistance of shallow diffused layers and thin polysilicon
films — self-aligned silicide (salicide) structures for the source, drain, and gate have been proposed, as
shown in Fig. 2.17.48–50
First, a metal film such as Ti or Co is deposited on the surface of the MOSFET after formation of the
polysilicon gate electrode, gate sidewall, and source and drain diffused layers, as shown in Fig. 2.17(b).
The film is then annealed by rapid thermal annealing (RTA) in an inert ambient. During the annealing
process, the areas of metal film in direct contact with the silicon layer — that is, the source, drain, and
gate electrodes — are selectively converted to the silicide, and other areas remain metal, as shown in Fig.
2.17(c). The remaining metal can be etched off with an acid solution such as H2O2 + H2SO4, leaving the
silicide self-aligned with the source, drain, and gate electrode, as shown in Fig. 2.17(d).
CMOS/BiCMOS Technology 2-11
FIGURE 2.16 Dependence of the propagation delay (tpd) of CMOS inverters on the scaling factor, k, or gate length.
FIGURE 2.17 A typical process flow and schematic cross-section of salicide process: (a) MOSFET formation; (b)
metal deposition; (c) silicidation by thermal annealing; and (d) removal of non-reactive metal.
When the salicide process first came into use, furnace annealing was the most popular heat-
treatment process48–50; however, RTA51–53 replaced furnace annealing early on, because it is difficult
to prevent small amounts of oxidant from entering through the furnace opening, and these degrade
the silicide film significantly since silicide metals are easily oxidized. On the other hand, RTA reduces
this oxidation problem significantly, resulting in reduced deterioration of the film and consequently
of its resistance.
2-12 VLSI Technology
At present, TiSi251–53 is widely used as a silicide in LSI applications. However, in the case of ultra-small
geometry MOSFETs for VLSIs, use of TiSi2 is subject to several problems. When the TiSi2 is made thick,
a large amount of silicon is consumed during silicidation, and this results in problems of junction leakage
at the source or drain. On the contrary, if a thin layer of TiSi2 is chosen, agglomeration of the film occurs54
at higher silicidation temperatures.
On the other hand, CoSi255 has a large silicidation temperature window for low sheet resistance; hence,
it is expected to be widely used as silicidation material for advanced VLSI applications.47
Interconnect and Metallization
Aluminum is widely used as a wiring metal. However, in the case of downsized CMOS, electromigration
(EM)56 and stress migration (SM)57 become serious problems. In order to prevent these problems, Al-
Cu (typically ~0.5 wt % Cu)58 is a useful wiring material. In addition, ultra-shallow junction for down-
sized CMOS sometimes needs barrier metal,58 such as TiN, between the metal and silicon, in order to
prevent junction leakage current.
Figure 2.18 shows a cross-sectional view of a multi-layer metallization structure. As a consequence of
CMOS downscaling, contact or via aspect ratio becomes larger; and, as a result, filling of contact or via
is not sufficient. Hence, new filling techniques, such as W-plug,59,60 are widely used.
In addition, considering both reliability and low resistivity, Cu is a useful wiring material.61 In the
case when Cu is used, metal thickness can be reduced in order to realize the same interconnect
resistance. The reduction of the metal thickness is useful for reducing the capacitance between the
dense interconnect wires, resulting in the high-speed operation of the circuit. In order to reduce RC
delay of wire in CMOS LSI, not only wiring material but also interlayer material is important. In
particular, low-κ material62 is widely studied.
In the case of Cu wiring, the dual damascene process63 is being widely studied because it is difficult
to realize fine Cu pattern by reactive ion etching. Figure 2.19 shows the process flow of Cu dual
damascene metallization. After formation of transistors and contact holes as shown in Fig. 2.19(a),
barrier metal, such as TiN, and Cu are deposited as shown in Fig. 2.19(b). By using the CMP
planarization process, Cu and barrier metal remains in the contact holes, as shown in Fig. 2.19(c).
Insulator, such as silicon dioxide, is deposited and the grooves for first metal wires are formed by
reactive ion etching, as shown in Fig. 2.19(d). After the deposition of barrier metal and Cu as shown
in Fig. 2.19(e), Cu and barrier metal remain only in the wiring grooves due to use of a planarization
process such as CMP, as shown in Fig. 2.19(f).
Resistors and capacitors already have good performance, even for high-frequency applications. On the
other hand, it is difficult to realize a high-quality inductor on a silicon chip because of inductance loss
in Si substrate, in which the resistivity is lower than that in the compound semiconductor, such as GaAs,
substrate. The relatively higher sheet resistance of aluminum wire used for high-density LSI is another
problem. Recently, quality of inductor has been improved by using thicker Al or Cu wire65 and by
optimizing the substrate structure.66
FIGURE 2.21 Schematic cross-section of the embedded DRAM, including DRAM cells and logic MOSFETs.
CMOS/BiCMOS Technology 2-15
FIGURE 2.22 Typical MOSFET structures for DRAM, embedded DRAM, and logic.
2-16 VLSI Technology
could be a technology driver because the embedded DRAM contains most of the key process steps for
DRAM and logic ULSIs.
Embedded Flash Memory Technology84
Recently, the importance of embedded flash technology has been increasing and logic chips with non-
volatile functions have become indispensable for meeting various market requirements.
Key issues in the selection of an embedded flash cell85 are (1) tunnel-oxide reliability (damage-less
program/erase(P/E) mechanism), (2) process and transistor compatibility with CMOS logic, (3) fast read
with low Vcc, (4) low power (especially in P/E), (5) simple control circuits, (6) fast program speed, and
(7) cell size. This ordering greatly depends on target device specification and memory density, and, in
general, is different from that of high-density stand-alone memories. NOR-type flash is essential and
EEPROM functionality is also required on the same chip. Figure 2.23 shows the typical device structure
of a NOR-type flash memory with logic device.86
Process Technology87
To realize high-performance embedded flash chips, at least three kinds of gate insulators are required
beyond the 0.25-µm regime in order to form flash tunnel oxide, CMOS gate oxide, high voltage transistor
gate oxide, and I/O transistor gate oxide. Flash cells are usually made by a stacked gate process. Therefore,
it is difficult to achieve less than 150% of the cost of pure logic devices.
The two different approaches to realize embedded flash chips are memory-based and logic-based, as
shown in Fig. 2.24.
Memory-based approach is advantageous in that it exploits established flash reliability and yield
guaranteed by memory mass production lines, but is disadvantageous for realizing high-performance
CMOS transistors due to the additional flash process thermal budget. On the contrary, logic-based
approach can use fully CMOS-compatible transistors as they are; but, due to the lack of dedicated mass
production lines, great effort is required in order to establish flash cell reliability and performance.
Historically, memory-based embedded flash chips have been adopted, but the logic-based chips have
FIGURE 2.23 Device structure schematic view of the NOR flash memories with dual-gate Ti-salicide.
become more important recently. In general, the number of additional masks required to embed a flash
cell into logic chips ranges from 4 to 9.
For high-density embedded flash chips, one transistor stack gate cell using channel hot electron
programming and channel FN tunneling erasing will be mainstream. For medium- or low-density, high-
speed embedded flash chips, two transistors will be important in the case of using the low power P/E
method. From the reliability point of view, a p-channel cell using band-to-band tunneling-induced
electron injection88 and channel FN tunneling ejection is promising since page-programmable EEPROM
can also be realized by this mechanism.85
Figure 2.26 shows typical process flow for BiCMOS. This is the simplest arrangement for incorporating
bipolar devices and a kind of low-cost BiCMOS. Here, the BiCMOS process is completed with minimum
additional process steps required to form the npn bipolar device, transforming the CMOS baseline process
into a full BiCMOS technology. For this purpose, many processes are merged. The p tub of n-MOSFET
shares an isolation of bipolar devices, the n tub of p-MOSFET device is used for the collector, the n+
source and drain are used for the emitter regions and collector contacts, and also extrinsic base contacts
have the p+ source and drain of PMOS device for common use.
Recently, there have been two significant uses of BiCMOS technology. One is high-performance MPU90
by using the high driving capability of bipolar transistor; the other is mixed signal products that utilize
the excellent analog performance of the bipolar transistor, as shown in Table 2.1.
For the high-performance MPU, merged processes were commonly used, and the mature version of
the MPU product has been replaced by CMOS LSI. However, this application has become less popular
now with reduction in the supply voltage. Mixed-signal BiCMOS requires high performance, especially
with respect to fT , fmax, and low noise figure. Hence, a double polysilicon structure with a silicon91 or
SiGe92 base with trench isolation technology is used.
The fabrication cost of BiCMOS is a serious problem and, thus, a low-cost mixed-signal BiCMOS
process93 has also been proposed.
FIGURE 2.27 TEM cross-section of a 1.5-nm gate oxide film. Uniform oxide of 1.5-nm thickness is observed.
However, the characteristics become normal as the gate length is reduced because the gate leakage current
decreases in proportion to the gate length and the drain current increases in inverse proportion to the
gate length.95,96 Recently, very high drive currents of 1.8 mA/mm and very high transconductances of
more than 1.1 S/mm have been reported using a 1.3-nm gate oxide at a supply voltage of 1.5 V.97 They
also operate well at low power and high speed with a low supply voltage in the 0.5-V range.98
Figure 2.29 shows the dependence of cutoff frequency, fT , of 1.5-nm gate oxide MOSFETs on gate
length.99 Very high cutoff frequencies of more than 150 GHz were obtained at gate lengths in the sub-
0.1-µm regime due to the high transconductance. Further, it was confirmed that the high transconduc-
tance offers promise of a good noise figure.
Therefore, the MOSFETs with ultra-thin gate oxides beyond the direct-tunneling limit have the poten-
tial to enable extremely high-speed digital circuit operation as well as high RF performance in analog
applications. Fortunately, the hot-carrier and TDDB reliability of these ultra-thin gate oxides seem to be
good.95,96,100 Thus, ultra-thin gate oxides are likely to be used for such LSIs, for certain application.
In actual applications, even though the leakage current of a single transistor may be very small, the
combined leakage of the huge number of transistors in a ULSI circuit poses problems, particularly for
battery backup operation.101,102 There is, however, the possibility of using these direct-tunneling gate oxide
MOSFETs only for the smaller number of switches in the critical path determining operation speed. Also,
use of a slightly thicker oxide of 2.0 or 2.5 nm would significantly reduce leakage current. The use of these
direct-tunneling gate oxide MOSFETs in LSI devices with smaller integration is another possibility.
FIGURE 2.28 Id-Vd characteristics of 1.5-nm gate oxide MOSFETs with several gate lengths: (a) Lg = 10 µm; (b)
Lg = 5 µm; (c) Lg = 1.0 µm; and (d) Lg = 0.1 µm.
FIGURE 2.29 Dependence of cutoff frequency (fT) on gate length (Lg) of 1.5-nm gate oxide MOSFETs.
CMOS/BiCMOS Technology 2-21
FIGURE 2.30 The process flow of MOSFETs with epitaxial Si channel, n channel, and p channel.
FIGURE 2.31 Structure of raised source/drain/gate FET: (a) schematic cross-section; (b) TEM photograph.
2-22 VLSI Technology
2.5 Summary
This chapter has described CMOS and BiCMOS technology. CMOS is the most important device struc-
ture for realizing the future higher-performance devices required for multimedia and other demanding
applications. However, certain problems are preventing the downsizing of device dimensions. The chapter
described not only conventional technology but also advanced technology that has been proposed with
a view to overcoming these problems.
BiCMOS technology is also important, especially for mixed-signal applications. However, CMOS
device performance has already been demonstrated for RF applications and, thus, analog CMOS circuit
technology will be very important for realizing the production of analog CMOS.
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63. Wada, J., Oikawa, Y., Katata, T., Nakamura, N., and Anand, M. B., “Low Resistance Dual Damascene
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66. Yoshitomi, T., Sugawara, Y., Morifuji, E., Ohguro, T., Kimijima, H., Morimoto, T., Momose, H. S.,
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68. Tsukamoto, M., Kuroda, H., and Okamoto, Y., “0.25mm W-polycide Dual Gate and Buried Metal
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70. Kim, K. N., Lee, J. Y., Lee, K. H., Noh, B. H., Nam, S. W., Park, Y. S., Kim, Y. H., Kim, H. S., Kim, J. S.,
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72. Drynan, J. M., Nakajima, K., Akimoto, T., Saito, K., Suzuki, M., Kamiyama, S., and Takaishi, Y.,
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74. Nesbit, L., Alsmeier, J., Chen, B., DeBrosse, J., Fahey, P., Gall, M., Gambino, J., Gerhard, S., Ishiuchi,
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75. Bronner, G., Aochi, H., Gall, M., Gambino, J., Gernhardt, S., Hammerl, E., Ho, H., Iba, J., Ishiuchi,
H., Jaso, M., Kleinhenz, R., Mii, T., Narita, M., Nesbit, L., Neumueller, W., Nitayama, A., Ohiwa,
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76. Ishiuchi, H., Yoshida, Y., Takato, H., Tomioka, K., Matsuo, K., Momose, H., Sawada, S., Yamazaki,
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77. Togo, M., Iwao, S., Nobusawa, H., Hamada, M., Yoshida, K., Yasuzato, N., and Tanigawa, T., “A Salicide-
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78. Crowder, S., Stiffler, S., Parries, P., Bronner, G., Nesbit, L., Wille, W., Powell, M., Ray, A., Chen, B.,
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79. Crowder, S., Hannon, R., Ho, H., Sinitsky, D., Wu, S., Winstel, K., Khan, B., Stiffler, S. R., and Iyer,
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80. Yoshida, M., Kumauchi, T., Kawakita, K., Ohashi, N., Enomoto, H., Umezawa, T., Yamamoto, N.,
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and Embedded DRAMs,” IEEE International Electron Device Meeting, p. 41, Washington, D.C., 1997.
81. Nakamura, S., Kosugi, M., Shido, H., Kosemura, K., Satoh, A., Minakata, H., Tsunoda, H., Koba-
yashi, M., Kurahashi, T., Hatada, A., Suzuki, R., Fukuda, M., Kimura, T., Nakabayashi, M., Kojima,
M., Nara, Y., Fukano, T., and Sasaki, N., “Embedded DRAM Technology Compatible to the 0.13
µm High-Speed Logics by Using Ru Pillars in Cell Capacitors and Peripheral Vias,” IEEE Interna-
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82. Drynan, J. M., Fukui, K., Hamada, M., Inoue, K., Ishigami, T., Kamiyama, S., Matsumoto, A.,
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83. Togo, M., Noda, K., and Tanigawa, T., “Multiple-Thickness Gate Oxide and Dual-Gate Technologies
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86. Watanabe, H., Yamada, S., Tanimoto, M., Mitsui, M., Kitamura, S., Amemiya, K., Tanzawa, T.,
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88. Ohnakado, T., Mitsunaga, K., Nunoshita, M., Onoda, H., Sakakibara, K., Tsuji, N., Ajika, N.,
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89. Iwai, H., Sasaki, G., Unno, Y., Niitsu, Y., Norishima, M., Sugimoto, Y., and Kannzaki, K., “0.8µm
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92. Johnson, R. A., Zierak, M. J., Outama, K. B., Bahn, T. C., Joseph, A. J.,Cordero, C. N.,
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93. Chyan, Y.-F., Ivanov, T. G., Carroll, M. S., Nagy, W. J., Chen, A. S., and Lee, K. H., “A 50-GHz 0.25-
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3
Bipolar Technology
3.1 Introduction
The development of a bipolar technology for integrated circuits goes hand in hand with the steady
improvement in semiconductor materials and discrete components during the 1950s and 1960s. Conse-
quently, silicon bipolar technology formed the basis for the IC market during the 1970s. As circuit
dimensions shrink, the MOSFET (or MOS) has gradually taken over as the major technological platform
for silicon integrated circuits. The main reasons are the ease of miniaturization and high yield for MOS
compared to bipolar technology. However, during the same period of MOS growth, much progress was
simultaneously achieved in bipolar technology.1,2 This is illustrated in Fig. 3.1 where the reported gate
delay time for emitter-coupled logic (ECL) is plotted versus year. 2,3 In 1984, the 100 ps/gate limit was
broken and, since then, the speed performance has been improved by a factor of ten. The high speed
and large versatility of the silicon bipolar transistor still make it an attractive choice for a variety of digital
and analog applications.4
Apart from high-speed performance, the bipolar transistor is recognized by its excellent analog
properties. It features high linearity, superior low- and high-frequency noise behavior, and a very large
transconductance.5 Such properties are highly desirable for many RF applications, both for narrow-
band as well as broad-band circuits.6 The high current drive capability per unit silicon area makes the
bipolar transistor suitable for input/output stages in many IC designs (e.g., in fast SRAMs). The
disadvantage of bipolar technology is the low transistor density, combined with a large power dissi-
pation. High-performance bipolar circuits are therefore normally fabricated at a modest integration
level (MSI/LSI). By using BiCMOS design, the benefits of both MOS and bipolar technology are
utilized.7 One example is mixed analog/digital systems where a high-performance bipolar process is
integrated with high-density CMOS. This technology forms a vital part in several system-on-a-chip
designs (e.g., for telecommunication circuits).
In this chapter, a brief overview of bipolar technology is given with an emphasis on the integrated
silicon bipolar transistor. The information presented here is based on the assumption that the reader is
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 3-1
3-2 VLSI Technology
FIGURE 3.1 Reported gate delay time for bipolar ECL circuits vs. year.
familiar with bipolar device fundamentals and basic VLSI process technology. Bipolar transistors are
treated in detail in the well-known textbooks by Ashburn8 and Roulston.9 The first part of this chapter
will outline the general concepts in bipolar process design and optimization (Section 3.2). The second
part will present the three generations of integrated devices representing state-of-the-art bipolar tech-
nologies for the 1970s, 1980s, and 1990s (Sections 3.3, 3.4, and 3.5, respectively). Finally, some future
trends in bipolar technology are outlined.
Figures-of-Merit
In the digital bipolar process, the cutoff frequency (fT) is a well-known figure-of-merit for speed. The fT
is defined for a common-emitter configuration with its output short-circuit when extrapolating the small
signal current gain to unity. From a circuit perspective, a more adequate figure-of-merit is the gate delay
time (τd) measured for a ring-oscillator circuit containing an odd number of inverters.10 The τd can be
expressed as a linear combination of the incoming time constants weighted by a factor determined by
the circuit topology (e.g., ECL).10,11 Alternative expressions for τd calculations have been proposed.12
Besides speed, power dissipation can also be a critical issue in densely packed bipolar digital circuits,
resulting in the power-delay product as a figure-of-merit.4
In the analog bipolar process, the dc properties of the transistor are of utmost importance. This involves
minimum values on common-emitter current gain (β), Gummel plot linearity (βmax/β) breakdown voltage
(BVCEO), and Early voltage (VA). The product β × VA is often introduced as a figure-of-merit for the device
dc characteristics.13 Rather than fT , the maximum oscillation frequency, f max = f T ⁄ ( 8πR B C BC ) is pre-
ferred as a figure-of-merit in high-speed analog design, where RB and CBC denote the total base resistance
Bipolar Technology 3-3
and the base-collector capacitance, respectively.14 Alternative figures-of-merit for speed have been proposed
in the literature.15,16 Analog bipolar circuits are often crucially dependent on a certain noise immunity,
leading to the introduction of the corner frequency and noise figure as figures-of-merit for low-frequency
and high-frequency noise properties, respectively.17
Process Optimization
The optimization of the bipolar process is divided between the intrinsic and extrinsic device design. This
corresponds to the vertical impurity profile and the horizontal layout of the transistor, respectively.10 See
example in Fig. 3.2, where the device cross-section is also included. It is clear that the vertical profile and
horizontal layout are primarily dictated by the given process and lithography constraints, respectively.
Figure 3.3 shows a simple flowchart of the bipolar design procedure. Starting from the specified dc
parameters at a given operation point, the doping profiles can be derived. The horizontal layout must
be adjusted for minimization of the parasitics. A (speed) figure-of-merit can then be calculated. An
implicit relation is thus obtained between the figure-of-merit and the processing parameters.11,18 In
practice, several iterations must be performed in the optimization loop in order to find an acceptable
compromise between the device parameters. This procedure is substantially alleviated by two-dimensional
process simulations of the device fabrication19 as well as device simulations of the bipolar transistor.20,21
For optimization of a large number of device parameters, the strategy is based on screening out the
unimportant factors, combined with a statistical approach (e.g., response surface methodology).22
Vertical Structure
The engineering of the vertical structure involves the design of the collector, base, and emitter impurity
profiles. In this respect, fT is an adequate parameter to optimize. For a modern bipolar transistor with
suppressed parasitics, the maximum fT is usually determined by the forward transit time of minority
carriers through the intrinsic component. The most important fT tradeoff is against BVCEO , as stated by
the Johnson limit for silicon transistors:23 the product fT × BVCEO cannot exceed 200 GHz-V (recently
updated to 500 GHz-V).24
Collector Region
The vertical n-type collector of the bipolar device in Fig. 3.2 consists of two regions below the p-type
base diffusion: a lowly or moderately doped n-type epitaxial (epi) layer, followed by a highly doped
n+-subcollector. The thickness and doping level of the subcollector are non-critical parameters; a high
arsenic or antimony doping density between 1019 and 1020 cm–3 is representative, resulting in a sheet
resistance of 20 to 40 Ω/sq. In contrast, the design of the epi-layer constitutes a fundamental topic in
bipolar process optimization.
To first order, the collector doping in the epi-layer is determined by the operation point (more
specifically, the collector current density) of the component (see Fig. 3.3). A normal condition is to have
the operation point corresponding to maximum fT , which typically means a collector current density on
the order of 2–4 × 104 A/cm2. As will be recognized later, bipolar scaling results in increased collector
current densities. Above a certain current, there will be a rapid roll-off in current gain as well as cutoff
frequency. This is due to high-current effects, primarily the base push-out or Kirk effect, leading to a
steep increase in the forward transit time.25 Since the critical current value is proportional to the collector
doping,26 a minimum impurity concentration for the epi-layer is required, thus avoiding fT degradation
(typically around 1017 cm–3 for a high-speed device). Usually, the epi-layer is doped only in the intrinsic
structure by a selectively implanted collector (SIC) procedure.27 An example of such a doping profile is
seen in Fig. 3.4. Such a collector design permits an improved control over the base-collector junction;
that is, shorter base width as well as suppressed Kirk effect. The high collector doping concentration,
however, may be a concern for both CBC and BVCEO . The latter value will therefore often set a higher limit
on the collector doping value. One way to reduce the electrical field in the junction is to implement a
3-4 VLSI Technology
FIGURE 3.2 (a) Layout, (b) cross-section, and (c) simulated impurity profile through emitter window for an
integrated bipolar transistor (E = emitter, B = base, C = collector).
Bipolar Technology 3-5
lightly doped collector spacer layer between the heavily doped base and collector regions.28,29 A retrograde
collector profile with a low impurity concentration near the base-collector junction and then increasing
toward the subcollector has also been reported to enhance fT .30,31
The thickness of the epi-layer exhibits large variations between different device designs, extending
several micrometers in depth for analog bipolar components, whereas a high-speed digital design typically
has an epi-layer thickness around 1 µm or below, thus reducing total collector resistance. As a result, the
transistor breakdown voltage is sometimes determined by reach-through breakdown (i.e., full depletion
penetration of the epi-collector). The thickness of the collector layer can therefore be used as a parameter
in determining BVCEO , which in turn is traded off vs. fT .32
In cases where fmax is of interest, the collector design must be carefully taken into account. Compared
to fT , the optimum fmax is found for thicker and lower doped collector epi-layers.33,34 The vertical collector
design will therefore, to a large extent, determine the tradeoff between fT and fmax.
3-6 VLSI Technology
FIGURE 3.4 Simulated vertical impurity profile with and without SIC.
Base Region
The width and peak concentration of the base profile are two of the most fundamental parameters in
vertical profile design. The base width WB is normally in the range 0.1 to 1 µm, whereas a typical base
peak concentration lies between 1017 and 1018 cm–3. The current gain of the transistor is determined by
the ratio of the Gummel number in the emitter and base. Usually, a current gain of at least 100 is required
for analog bipolar transistors, whereas in digital applications, β around 20 is often acceptable. A normal
base sheet resistance (or pinch resistance) for conventional bipolar processes is of the order of 100 Ω/sq.,
whereas the number for high-speed devices typically is in the interval 1 to 10 kΩ/sq. This is due to the
2
small WB < 0.1 µm necessary for a short base transit time ( ∝ W B ). On the other hand, a too narrow
base will have a negative impact on fmax because of its RB dependence. As a result, fmax exhibits a maximum
when plotted against WB.35
The base impurity concentration must be kept high enough to avoid punch-through at low collector
voltages; that is, the base-collector depletion layer penetrates across the neutral base. In other words, the
base doping level is also dictated by the collector impurity concentration. Punch-through is the ultimate
consequence of base width modulation or the Early effect manifested by a finite output resistance in the
IC-VCE transistor characteristic.36 The associated VA or the product β × VA serves as an indicator of the
linear properties for the bipolar transistor. The VA is typically at a relatively high level (>30 V) for analog
applications, whereas digital designs often accept relatively low VA < 15 V.
Figure 3.5 demonstrates simulations of current gain versus the base doping for various WB .37 It is
clearly seen that the base doping interval permitting a high current gain while avoiding punch-through
will be pushed to high impurity concentrations for narrow base widths. In addition, Fig. 3.5 points to
another limiting factor for high base doping numbers above 5 × 1018 cm–3, namely, the onset of forward-
biased tunneling currents in the emitter-base junction38 leading to non-ideal base current characteristics.39
It is concluded that the allowable base doping interval will be very narrow for WB < 0.1 µm.
The shape of the base profile has some influence over the device performance. The final base profile
is the result of an implantation and diffusion process and, normally, only the peak base concentration
is given along with the base width. Nonetheless, there will be an impurity grading along the base profile
(see Figs. 3.2 and 3.4), creating a built-in electrical field and thereby adding a drift component for the
minority carrier transport.40 Recent research has shown that for very narrow base transistors, the uniform
doping profile is preferable when maximizing fT .41,42 This is also valid under high injection conditions in
the base.43 Uniformly doped base profiles are common in advanced bipolar processes using epitaxial
techniques for growing the intrinsic base.
Bipolar Technology 3-7
FIGURE 3.5 Simulated current gain vs. base doping density for different base widths (NC = 6 × 1016 cm–3, NE =
1020 cm–3, and emitter depth 0.20 µm) (after Ref. 37, copyright© 1990, IEEE).
During recent years, base profile design has largely been devoted to implementation of narrow bandgap
SiGe in the base. The resulting emitter-base heterojunction allows a considerable enhancement in current
gain, which can be traded off against increased base doping, thus substantially alleviating the problem
with elevated base sheet resistances typical of high-speed devices.44 Excellent dc as well as high-frequency
properties can be achieved. The position of the Ge profile with respect to the boron profile has been
discussed extensively in the literature.45–47 More details about SiGe heterojunction engineering are found
in Chapter 5 by Cressler.
Emitter Region
The conventional metal-contacted emitter is characterized by an abrupt arsenic or phosphorus profile
fabricated by direct diffusion or implantation into the base area (see Fig. 3.2).48 In keeping emitter
efficiency close to unity (and thus high current gain), the emitter junction cannot be made too shallow
(~1 µm). The emitter doping level lies typically between 1020 and 1021 cm–3 close to the solid solubility
limit at the silicon surface, hence providing a low emitter resistance as well as a large emitter Gummel
number required for keeping current gain high. Bandgap narrowing, however, will be present in the
emitter, causing a reduction in the efficient emitter doping.49
When scaling bipolar devices, the emitter junction must be made more shallow to ensure a low emitter-
base capacitance. When the emitter depth becomes less than the minority carrier recombination length,
the current gain will inevitably degrade. This precludes the use of conventional emitters in a high-
performance bipolar technology. Instead, polycrystalline (poly) silicon emitter technology is utilized. By
diffusing impurity species from the polysilicon contact into the monocrystalline (mono) silicon, a very
shallow junction (< 0.2 µm) is formed; yet gain can be kept at a high level and even traded off against
a higher base doping.50 A gain enhancement factor between 3 and 30 for the polysilicon compared to the
monosilicon emitter has been reported (see also Section 3.4).51,52
Scaling Rules
The principles for vertical design can be summarized in the bipolar scaling rules formulated by Solomon
and Tang;53,54 see Table 3.1. Since the bipolar transistor is scaled under constant voltage, the current
3-8 VLSI Technology
density increases with reduced device dimensions. At medium or high current densities, the vertical
structure determines the speed. At low current densities, performance is normally limited by device
parasitics. Eventually, tunnel currents or contact resistances constitute a final limit to further speed
improvement based on the scaling rules. A solution is to use SiGe bandgap engineering to further enhance
device performance without scaling.
Horizontal Layout
The horizontal layout is carried out in order to minimize the device parasitics. Figure 3.6 shows the
essential parasitic resistances and capacitances for a schematic bipolar structure containing two base
contacts. The various RC constants in Fig. 3.6 introduce time delays. For conventional bipolar transistors,
such parasitics often limit device speed. In contrast, the self-alignment technology applied in advanced
bipolar transistor fabrication allows for efficient suppression of the parasitics.
In horizontal layout, fmax serves as a first-order indicator in the extrinsic optimization procedure
because of its dependence on CBC and (total) RB. These two parasitics are strongly connected to the
geometrical layout of the device. The more advanced τd calculation takes all major parasitics into account
under given load conditions, thus providing good insight into the various time delay contributions of a
bipolar logic gate.55
From Fig. 3.6, it is seen that the collector resistance is divided into three parts. Apart from the epi-
layer and buried layer previously discussed, the collector contact also adds a series resistance. Provided
the epi-layer is not too thick, the transistor is equipped with a deep phosphorus plug from the collector
contact down to the buried layer, thus reducing the total RC.
As illustrated in Fig. 3.6, the base resistance is divided into intrinsic (RBi) and extrinsic (RBx) compo-
nents. The former is the pinched base resistance situated directly under the emitter diffusion, whereas
the latter constitutes the base regions contacting the intrinsic base. The intrinsic part decreases with the
current due to the lateral voltage drop in the base region.56 At high current densities, this causes current
crowding effects at the emitter diffusion edges. This results in a reduced onset for high-current effects
in the transistor. The extrinsic base resistance is bias independent and must be kept as small as possible
(e.g., by utilizing self-alignment architectures). By designing a device layout with two or more base
contacts surrounding the emitter, the final RB is further reduced at the expense of chip area. Apart from
enhancing fmax, the RB reduction is also beneficial for device noise performance.
The layout of the emitter is crucial since the effective emitter area defines the intrinsic device cross-
section.57 The minimum emitter area, within the lithography constraints, is determined by the operational
collector current and the critical current density where high-current effects start to occur.58 Eventually,
a tradeoff must be made between the base resistance and device capacitances as a function of emitter
geometry; this choice is largely dictated by the device application. Long, narrow emitter stripes, meaning
a reduction in the base resistance, are frequently used. The emitter resistance is usually non-critical for
conventional devices; however, for polysilicon emitters, the emitter resistance may become a concern in
very small-geometry layouts.3
Bipolar Technology 3-9
FIGURE 3.6 Schematic view of the parasitic elements in a bipolar transistor equipped with two base contacts. RE
= emitter resistance, RBi = intrinsic base resistance, RBx = extrinsic base resistance, RC = collector resistance, CEB =
emitter-base capacitance, CBCi = intrinsic base-collector capacitance, CBCx = extrinsic base-collector capacitance, and
CCS = collector-substrate capacitance. Gray areas denote depletion regions. Contact resistances are not shown.
Of the various junction capacitances in Fig. 3.6, the collector-base capacitance is the most significant.
This parasitic is also divided into intrinsic (CBCi) and extrinsic (CBCx) contributions. Similar to RBx, the
CBCx is kept low by using self-aligned schemes. For example, the fabrication of a SIC causes an increase
only in CBCi , whereas CBCx stays virtually unaffected. The collector-substrate capacitance CCS is one of the
minor contributors to fT ; the CCS originates from the depletion regions created in the epi-layer and under
the buried layer. CCS will become significant at very high frequencies due to substrate coupling effects.59
Junction-Isolated Transistors
The early planar transistor technology took advantage of a reverse-biased pn junction in providing the
necessary isolation between components. One of the earliest junction-isolated transistors, the so-called
triple-diffused process, is simply based on three ion implantations and subsequent diffusion.60 This device
has been integrated into a standard CMOS process using one extra masking step.61 The triple-diffused
bipolar process, however, suffers from a large collector resistance due to the absence of a subcollector,
and the npn performance will be low.
3-10 VLSI Technology
FIGURE 3.7 Cross-section of the buried-collector transistor with junction isolation and collector plug.
By far, the most common junction-isolated transistor is represented by the device cross-section of Fig.
3.7, the so-called buried-collector process.60 This device is based on the concept previously shown in Fig.
3.2 but with the addition of an n+-collector plug and isolation. This is provided by the diffused p+-regions
surrounding the transistor. The diffusion of the base and emitter impurities into the epi-layer allows
relatively good control of the base width (more details of the fabrication is given in the next section on
oxide-isolated transistors).
A somewhat different approach of the buried-collector process is the so-called collector-isolation
diffusion.62 This process requires a p-type epi-layer after formation of the subcollector. An n+- diffusion
serves both as isolation and the collector plug to the buried layer. After an emitter diffusion, the p-type
epi-layer will constitute the base of the final device. Compared to the buried-layer collector process, the
collector-isolated device concept does not result in very accurate control over the final base width.
The main disadvantage of the junction-isolated transistor is the relatively large chip area occupied by
the isolation region, thus precluding the use of such a device in any VLSI application. Furthermore, high-
speed operation is ruled out because of the large parasitic capacitances associated with the junction
isolation and the relatively deep diffusions involved. Indeed, many of the conventional junction-isolated
processes were designed for doping from the gas phase at high temperatures.
Oxide-Isolated Transistors
Oxide isolation permits a considerable reduction in the lateral and vertical dimensions of the buried-
layer collector process. The reason is that the base and collector contacts can be extended to the edge of
the isolation region. More chip area can be saved by having the emitter walled against the oxide edge.
The principal difference between scaling of junction- and oxide-isolated transistors is visualized in Fig.
3.8.63 The device layouts are Schottky clamped; that is, the base contact extends over the collector region.
This hinders the transistor to enter saturation mode under device operation. In Fig. 3.8(b), the effective
surface area of the emitter contact has been reduced by a so-called washed emitter approach: since the
oxide formed on the emitter window during emitter diffusion has a much higher doping concentration
than its surroundings, this particular oxide can be removed by a mask-less wet etching. Hence, the emitter
contact becomes self-aligned to the emitter diffusion area.
The process flow including mask layouts for an oxide-isolated bipolar transistor of the buried-layer
collector type is shown in Fig. 3.9.64 After formation of the subcollector by arsenic implantation through
an oxide mask in the p–-substrate, the upper collector layer is grown epitaxially on top (Fig. 3.9(a)). The
device isolation is fabricated by local oxidation of silicon (LOCOS) or recessed oxide (ROX) process
(Figs. 3.9(b) to (d)). The isolation mask in Fig. 3.9(b) is aligned to the buried layer using the step in the
silicon (Fig. 3.9(a)) originating from the enhanced oxidation rate for highly doped n+-silicon compared
to the p—-substrate during activation of the buried layer. The ROX is thermally grown (Fig. 3.9(d)) after
the boron field implantation (or chan-stop) (Fig. 3.9(c)). This p+-implant is necessary for suppressing a
conducting channel otherwise present under the ROX. The base is then formed by ion implantation of
boron or BF2 through a screen oxide (Fig. 3.9(d)); in the simple device of Fig. 3.9, a single base
Bipolar Technology 3-11
FIGURE 3.8 Device layout and cross-section demonstrating scaling of (a)-(b) junction-isolated and (c)-(d)
oxide-isolated bipolar transistors (after Ref. 63, copyright© 1986, Wiley).
implantation is used; in a more advanced bipolar process, the fabrication of the intrinsic and extrinsic
base must be divided into one low dose and one high dose implantation, respectively, adding one more
mask to the total flow. After base formation, an emitter/base contact mask is patterned in a thermally
grown oxide (Fig. 3.9(e)). The emitter is then implanted using a heavy dose arsenic implant (Fig. 3.9(f)).
An n+ contact is simultaneously formed in the collector window. After annealing, the device is ready for
metallization and passivation.
Apart from the strong reduction in isolation capacitances, the replacement of a junction-isolated process
with an oxide-isolated process also adds other high-speed features such as thinner epitaxial layer and
shallower emitter/base diffusions. A typical base width is a few 1000 Å and the resulting fT typically lies in
the range of 1 to 10 GHz. The doping of the epitaxial layer is determined by the required breakdown voltage.
Further speed enhancement of the oxide-isolated transistor is difficult due to the parasitic capacitances and
resistances originating from contact areas and design-rule tolerances related to alignment accuracy.
FIGURE 3.9 Layout and cross-section of the fabrication sequence for an oxide-isolated buried-collector transistor
(after Ref. 64, copyright© 1983, McGraw-Hill).
Bipolar Technology 3-13
FIGURE 3.11 A double-poly self-aligned bipolar transistor with deep-trench isolation, polysilicon emitter and
SIC. Metallization is not shown.
Self-Aligned Structures
Advanced bipolar transistors are based on self-aligned structures made possible by polysilicon emitter
technology. As a result, the emitter-base alignment is not dependent on the overlay accuracy of the
lithography tool. The device contacts can be separated without affecting the active device area. It is also
possible to create structures where the base is self-aligned both to the collector and emitter, the so-called
sidewall-based contact structure (SICOS).68 This process, however, has not been able to compete suc-
cessfully with the self-aligned schemes discussed below.
The self-aligned structures are divided into single-polysilicon (single-poly) and double-polysilicon
(double-poly) architectures, as visualized in Fig. 3.12.69 The double-poly structure refers to the emitter
polysilicon and base polysilicon electrode, whereas the single-poly only refers to the emitter polysilicon.
From Fig. 3.12, it is seen that the double-poly approach benefits from a smaller active area than the
single-poly, manifested in a reduced base-collector capacitance. Moreover, the double-poly transistor in
general exhibits a lower base resistance. The double-poly transistor, however, is more complex to fabricate
than the single-poly device. On the other hand, by applying inside spacer technology for the double-poly
emitter structure, the lithography requirements are not as strict as in the single-poly case where more
conventional MOS design rules are used for definition of the emitter electrode.
Single-Poly Structure
The fabrication of a single-poly transistor has been presented in several versions, more or less similar to
the traditional MOS flow. An example of a standard single-poly process is shown in Fig. 3.13.70 After
arsenic emitter implantation (Fig. 3.13(a)) and polysilicon patterning, a so-called base-link is implanted
using boron ions (Fig. 3.13(b)). Oxide is then deposited and anisotropically etched to form outside
spacers, followed by the heavy extrinsic base implantation (Fig. 3.13(c)). Shallow junctions (including
emitter diffusion) are formed by rapid thermal annealing (RTA). A salicide or polycide metallization
completes the structure (Fig. 3.13(d)).
The intrinsic base does not necessarily need to be formed prior to the extrinsic part. Li et al.71 have
presented a reverse extrinsic-intrinsic base scheme based on a disposable emitter pedestal with spacers.
This leads to improved control over the intrinsic base width and a lower surface topography compared
to the process represented in Fig. 3.13.
Bipolar Technology 3-15
FIGURE 3.12 (a) Double-poly structure and (b) single-poly structure. Buried layer and collector contact are not
shown (after Ref. 69, copyright© 1989, IEEE).
Another variation of the single-poly architecture is the so-called quasi-self-aligned process (see
Fig. 3.14).72 A base oxide is formed by thermal oxidation in the active area and an emitter window is
opened (Fig. 13.14(a)). Following intrinsic base implantation, the emitter polysilicon is deposited,
implanted, and annealed. The polysilicon emitter pedestal is then etched out (Fig. 3.14(b)). The extrinsic
base process, junction formation, and metallization are essentially the same as in the single-poly process
shown in Fig. 3.13. Note that in Fig. 13.4, the emitter-base formation is self-aligned to the emitter window
in the oxide, not to the emitter itself, hence explaining the term quasi-self-aligned. As a result, a higher
total base resistance is obtained compared to the standard single-poly process.
The boron implantation illustrated in Fig. 3.13(b) is an example of so-called base-link engineering
aimed at securing the electrical contact between the heavily doped p+-extrinsic base and the much lower
doped intrinsic base. Too weak a base link will result in high total base resistance, whereas too strong a
base link may create a lateral emitter-base tunnel junction leading to non-ideal base current character-
istics.73 Furthermore, a poorly designed base link jeopardizes matching between individual transistors
since the final current gain may vary substantially with the emitter width.
Double-Poly Structure
The double-poly structure originates from the classical IBM structure presented in 1981.74 Most high-
performance commercial processes today are based on double-poly technology. The number of vari-
ations are less than for the single-poly, mainly with different aspects on base-link engineering, spacer
technology, and SIC formation. One example of a double-poly fabrication is presented in Fig. 3.15.
After deposition of the base polysilicon and oxide stack, the emitter window is opened (Fig. 3.15(a))
and thermally oxidized. During this step, p+-impurities from the base polysilicon diffuse into the
monosilicon, thus forming the extrinsic base. In addition, the oxidation repairs the crystal damage
caused by the dry etch when opening the emitter window. A thin silicon nitride layer is then deposited,
the intrinsic base is implanted using boron, followed by the fabrication of amorphous silicon spacers
inside the emitter window (Fig. 3.15(b)). The nitride is exposed to a short dry etch, the spacers are
3-16 VLSI Technology
FIGURE 3.13 The single-poly, self-aligned process: (a) polyemitter implantation, (b) emitter etch and base link
implantation, (c) oxide spacer formation and extrinsic base implantation, and (d) final device after junction formation
and metallization.
Bipolar Technology 3-17
FIGURE 3.14 The single-poly, quasi-self-aligned process: (a) polyemitter implantation, (b) final device.
removed, and the thin oxide is opened up by an HF dip. Deposition and implantation of the polysilicon
emitter film is carried out (Fig. 3.15(c)). The structure is patterned and completed by RTA emitter
drive-in and metallization (Fig. 3.15(d)). The emitter will thus be fully self-aligned with respect to the
base. Note that the inside spacer technology implies that the actual emitter width will be significantly
less than the drawn emitter width.
The definition of the polyemitter in the single- and double-poly process inevitably leads to some
overetching into the epi-layer, see Figs. 3.13(b) and 3.15(a), respectively. The final recessed region will
make control over base-link formation more awkward.75,76 In fact, the base link will depend both on the
degree of overetch as well as the implantation parameters.77 This situation is of no concern for the quasi-
self-aligned process where the etch of the polysilicon emitter stops on the base oxide.
In a modification of the double-poly process, a more advanced base-link technology is proposed.78
After extrinsic base drive-in and emitter window opening, BF2-implanted poly-spacers are formed inside
the emitter window. The boron is out-diffused through the emitter oxide, thus forming the base link.
The intrinsic base is subsequently formed by conventional implantation through the emitter window.
New dielectric inside spacers are formed prior to polysilicon emitter deposition, followed by arsenic
implantation and emitter drive-in.
Also, vertical pnp bipolar transistors based on the double-poly concept have been demonstrated.79
Either boron or BF2 is used for the polyemitter implantation. A pnp device with fT of 35 GHz has been
presented in a classical double-poly structure.80
FIGURE 3.15 The double-poly, self-aligned process: (a) emitter window etch, (b) intrinsic base implantation
through thin oxide/nitride stack followed by inside spacer formation, (c) polyemitter implantation, (d) final device
after emitter drive-in and metallization.
Bipolar Technology 3-19
Implanted Base
Today’s most advanced commercial processes are specified with an fT around 30 GHz. The major developments
are being carried out using double-poly technology, although new improvements have also been reported for
single-poly architectures.72,81 For double-poly transistors, it was demonstrated relatively early that by optimizing
a very low intrinsic base implant energy below 10 keV, devices with an fT around 50 GHz are possible to
fabricate.82 The emitter out-diffusion is performed by a combined furnace anneal and RTA. In this way, the
intrinsic base width is controlled below 1000 Å, whereas the emitter depth is only around 250 Å.
Since ion implantation is associated with a number of drawbacks such as channeling, shadowing effects,
and crystal defects, it may be difficult to reach an fT above 50 to 60 GHz based on such a technology.
The intrinsic base implantation has been replaced by rapid vapor deposition using B2H6 gas around
900°C.83 The in-diffused boron profile will form a thin and low-resistive base. Also, the emitter implan-
tation can be removed by utilizing in situ doped emitter technology (e.g., AsH3 gas during polysilicon
deposition).84 Two detrimental effects are then avoided; namely, emitter perimeter depletion and the
emitter plug effect.85 The former effect causes a reduced doping concentration close to the emitter
perimeter, whereas the latter implies the plugging of doping atoms in narrow emitter windows causing
shallower junctions compared to larger openings on the same chip.
Arsenic came to replace phosphorus as the emitter impurity during the 1970s, mainly because of the
emitter push-effect plaguing phosphorus monosilicon emitters. The phosphorus emitter has, however,
experienced a renaissance in advanced bipolar transistors by introducing the so-called in situ phosphorus
doped polysilicon (IDP) emitter.86 One motivation for using IDP technology is the reduction in final
emitter resistance compared to the traditional As polyemitter, in particular for aggressively down-scaled
devices with very narrow emitter windows. In addition, the emitter drive-in for an IDP emitter is carried
out at a lower thermal budget than the corresponding arsenic emitter due to the difference in diffusivity
between the impurity atoms. Using IDP and RVD, very high fT values (above 60 GHz) have been realized.83
It has been suggested that the residual stress of the IDP emitter and the interfacial oxide between the
poly- and the monosilicon creates a heteroemitter action for the device, thus explaining the high current
gains of IDP bipolar transistors.87
Base electrode engineering in advanced devices has become an important field in reducing the total
base resistance, thus improving fmax of the transistor. One straightforward method in lowering the base
sheet resistance is by shunting the base polysilicon with an extended silicide across the total base electrode.
This has recently been demonstrated in an fmax = 60 GHz double-poly process.88 A still more effective
concept is to integrate metal base electrodes.89 This approach is combined with in situ doped boron
polysilicon base electrodes as well as an IDP emitter in a double-poly process (see Fig. 3.16). The tungsten
electrodes are fully self-aligned using WF6-selective deposition. The technology, denoted SMI (self-aligned
metal IDP), has been applied together with RVD base formation. The bipolar process was shown to
produce fT and fmax figures of 100 GHz at a breakdown voltage of 2.5 V.90
Epitaxial Base
By introducing epitaxial film growth techniques for intrinsic base formation, the base width is readily
controlled on the order of some hundred angstroms. Both selective and non-selective epitaxial growth
(SEG and NSEG, respectively) have been reported. One example of a SEG transistor flow is illustrated
in Fig. 3.17.91 Not only the epitaxial base, but also the n–-collector is grown using SEG. The p+-poly
overhangs warrant a strong base link between the SEG intrinsic base and the base electrode. This
fT = 44 GHz process was capable of delivering divider circuits working at 25 GHz.
A natural extension of the Si epitaxy is to apply the previously mentioned SiGe epitaxy, thus creating
a heterojunction bipolar transistor (HBT). For example, the transistor process in Fig. 3.17 was later
extended to a SiGe process with fT = 61 GHz and fmax = 74 GHz.92 Apart from high speed, low base
resistance is a trademark for many SiGe bipolar processes. For details of the SiGe HBT, the reader is
referred to Chapter 5. Here, only some process integration points of view are given of this very important
technology for advanced silicon-based bipolar devices during the 1990s.
3-20 VLSI Technology
FIGURE 3.16 The self-aligned metal IDP process using selective deposition of tungsten base electrodes (after Ref.
89, copyright© 1997, IEEE).
While the first world records in terms of fT and fmax were broken for non-self-aligned structures or
mesa HBTs, planar self-aligned process schemes taking advantage of the benefits using SiGe have
subsequently been demonstrated. In recent years, both single-poly and double-poly SiGe transistors
exhibiting excellent dc and ac properties have been presented. This also includes the quasi-self-aligned
approach where a fully CMOS compatible process featuring an fmax of 71 GHz has been shown.93 A
similar concept featuring NSEG, so-called differential epitaxy, has been applied in the design of an HBT
with a single-crystalline emitter rather than a polysilicon emitter.94 This process, however, requires a
very low thermal budget because of the high boron and germanium content in the intrinsic base of the
transistor. Excellent properties for RF applications are made possible by this approach, such as high fT
and fmax around 50 GHz, combined with good dc properties and low noise figures.95
In double-poly structures, the extrinsic base is usually deposited prior to SiGe base epitaxy, which is
then carried out by SEG (as shown in Fig. 3.17). Several groups report τd below 20 ps using this approach.
One example of the most advanced bipolar technologies is the SiGe double-poly structure shown in Fig.
3.18.96 This technology features the SMI base electrode technology, together with SEG of SiGe. The device
is isolated by oxide-filled trenches. The reported τd was 7.7 ps and the fmax was 108 GHz, thus approaching
the SiGe HBT mesa record of 160 GHz.97 A device similar to the one in Fig. 3.18 was also reported to
yield an fT of 130 GHz.98
Bipolar Technology 3-21
FIGURE 3.17 Process demonstrating selective epitaxial growth: (a) self-aligned formation of p+-poly overhangs,
(b) selective epitaxial growth of the intrinsic base, (c) emitter fabrication (after Ref. 91, copyright© 1992, IEEE).
FIGURE 3.18 A state-of-the-art bipolar device featuring SMI electrodes, selectively grown epitaxial SiGe base, in
situ doped polysilicon emitter/base and oxide-filled trenches (after Ref. 96, copyright© 1998, IEEE).
3-22 VLSI Technology
Future Trends
The shrinking of dimensions in bipolar devices, in particular for digital applications, will proceed
one or two generations behind the MOS frontier, leading to a further reduction in τd. Several of the
concepts reviewed above for advanced bipolar components are expected to be introduced in the next
commercial high-performance processes; for example, in situ doped emitter and low-resistivity base
electrodes. Similar to CMOS, the overall temperature budget must be reduced in processing. Evidently,
bipolar technology in the future also continues to benefit from the progress made in CMOS tech-
nology; for example, in isolation and back-end processing. CMOS compatibility will be a general
requirement for the majority of bipolar process development because of the strong interest in mixed-
signal BiCMOS processes.
Advanced isolation technology combining deep and shallow trenches, perhaps on silicon-on-insu-
lator (SOI) or high-resistivity substrates, marks one key trend in future bipolar transistors. Bipolar
technology based on SOI substrates may well be accelerated by the current introduction of SOI into
CMOS production. However, thermal effects for high current drive bipolar devices must be solved
when using SOI. An interesting low-cost alternative insulating substrate for RF-bipolar technology is
the silicon-on-anything concept recently presented.99 In addition, copper metallization will be intro-
duced for advanced bipolars provided that intermetal dielectrics as well as passive components are
developed to meet this additional advantage.100
The epitaxial base constitutes another important trend where both Si and SiGe are expected to enhance
performance in the high-frequency domain, although the introduction may be delayed due to progress
in ion-implanted technology. In this respect, SEG technology has yet to prove its manufacturability.
Future Si-based bipolar technology with fT and fmax greater than 100 GHz will continue to play an
important role in small-density, high-performance designs. The most important applications are found
in communication systems in the range 1 to 10 GHz (wireless telephony and local area networks) and
10 to 70 GHz (microwave and optical-fiber communication systems) where Si and/or SiGe bipolar
technologies are expected to seriously challenge existing III-V technologies.101
Acknowledgments
We are grateful to G. Malm and M. Linder for carrying out the process simulations. The support from
the Swedish High-Frequency Bipolar Technology Consortium is greatly acknowledged.
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Bipolar Technology 3-27
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4
Silicon on Insulator
Technology
4.1 Introduction
Silicon on insulator (SOI) technology (more specifically, silicon on sapphire) was originally invented for
the niche of radiation-hard circuits. In the last 20 years, a variety of SOI structures have been conceived
with the aim of dielectrically separating, using a buried oxide (Fig. 4.1(b)), the active device volume from
the silicon substrate.1 Indeed, in an MOS transistor, only the very top region (0.1–0.2 µm thick, i.e., less
than 0.1% of the total thickness) of the silicon wafer is useful for electron transport and device operation,
whereas the substrate is responsible for detrimental, parasitic effects (Fig. 4.1(a)).
More recently, the advent of new SOI materials (Unibond, ITOX) and the explosive growth of portable
microelectronic devices have attracted considerable attention on SOI for the fabrication of low-power
(LP), low-voltage (LV), and high-frequency (HF) CMOS circuits.
The aim of this chapter is to overview the state-of-the-art of SOI technologies, including the material
synthesis (Section 4.2), the key advantages of SOI circuits (Section 4.3), the structure and performance
of typical devices (Section 4.4), and the operation modes of fully depleted (Section 4.5) and partially
depleted SOI MOSFETs (Section 4.6). Section 4.7 is dedicated to short-channel effects. The main chal-
lenges that SOI is facing, in order to successfully compete with bulk-Si in the commercial arena, are
critically discussed in Section 4.8.
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 4-1
4-2 VLSI Technology
FIGURE 4.1 Basic architecture of MOS transistors in (a) bulk silicon and (b) SOI.
Silicon on Sapphire
Silicon on sapphire (SOS, Fig. 4.2(a1)) is the initial member of SOI family. The epitaxial growth of Si
films on Al2O3 gives rise to small silicon islands that eventually coalesce. The interface transition region
contains crystallographic defects due to the lattice mismatch and Al contamination from the substrate.
The electrical properties suffer from lateral stress, in-depth inhomogeneity of SOS films, and defective
transition layer.2
SOS has recently undergone a significant lifting: larger wafers and thinner films with higher crystal
quality. This improvement is achieved by solid-phase epitaxial regrowth. Silicon ions are implanted to
amorphise the film and erase the memory of damaged lattice and interface. Annealing allows the epitaxial
regrowth of the film, starting from the “seeding” surface towards the Si–Al2O3 interface. The result is
FIGURE 4.2 SOI family: (a) SOS, ZMR, FIPOS, and wafer bonding, (b) SIMOX variants, (c) UNIBOND
processing sequence.
Silicon on Insulator Technology 4-3
visible in terms of higher carrier mobility and lifetime; 100-nm thick SOS films with good quality have
recently been grown on 6-in. wafers.3
Thanks to the “infinite” thickness of the insulator, SOS looks promising for the integration of RF and
radiation-hard circuits.
FIPOS
The FIPOS method (full isolation by porous oxidized silicon) makes use of the very large surface-to-volume
ratio (103 cm2 per cm3) of porous silicon which is, thereafter, subject to selective oxidation (Fig. 4.2(a3)).
The critical step is the conversion of selected p-type regions of the Si wafer into porous silicon, via anodic
reaction. FIPOS may enlighten Si technology because there are prospects, at least from a conceptual
viewpoint, for combining electroluminescent porous Si devices with fast SOI–CMOS circuits.
SIMOX
In the last decade, the dominant SOI technology was SIMOX (separation by implantation of oxygen). The
buried oxide (BOX) is synthesized by internal oxidation during the deep implantation of oxygen ions
into a Si wafer. Annealing at high temperature (1320°C, for 6 h) is necessary to recover a suitable crystalline
quality of the film. High current implanters (100 mA) have been conceived to produce 8-in. wafers with
good thickness uniformity, low defect density (except threading dislocations: 104–106 cm–2), sharp Si–SiO2
interface, robust BOX, and high carrier mobility.4
The family of SOI structures is presented in Figure 4.2(b):
• Thin and thick Si films fabricated by adjusting the implant energy.
• Low-dose SIMOX: a dose of 4 × 1017 O+/cm2 and an additional oxygen-rich anneal for enhanced
BOX integrity (ITOX process) yield a 0.1-µm thick BOX (Fig. 4.2(b1)).
• Standard SIMOX obtained with 1.8 × 1018 O+/cm2 implant dose, at 190 keV and 650°C; the
thicknesses of the Si film and BOX are roughly 0.2 µm and 0.4 µm, respectively (Fig. 4.2(b2)).
• Double SIMOX (Fig. 4.2(b3)), where the Si layer sandwiched between the two oxides can serve
for interconnects, wave guiding, additional gates, or electric shielding.
• Laterally-isolated single-transistor islands (Fig. 4.2(b4)), formed by implantation through a pat-
terned oxide.
• Interrupted oxides (Fig. 4.2(b5)) which can be viewed as SOI regions integrated into a bulk Si wafer.
Wafer Bonding
Wafer bonding (WB) and etch-back stands as a rather mature SOI technology. An oxidized wafer is mated
to another SOI wafer (Fig. 4.2(a4)). The challenge is to drastically thin down one side of the bonded
structure in order to reach the targeted thickness of the silicon film. Etch-stop layers can be achieved by
doping steps (P+/P-, P/N) or porous silicon (Eltran process).5 The advantage of wafer bonding is to
4-4 VLSI Technology
provide unlimited combinations of BOX and film thicknesses, whereas its weakness comes from the
difficulty to produce ultra-thin films with good uniformity.
UNIBOND
A recent, revolutionary bonding-related process (UNIBOND) uses the deep implantation of hydrogen
into an oxidized Si wafer (Fig. 4.2(c1)) to generate microcavities and thus circumvent the thinning
problem.6 After bonding wafer A to a second wafer B and subsequent annealing to enhance the bonding
strength (Fig. 4.2(c2)), the hydrogen-induced microcavities coalesce. The two wafers separate, not at the
bonded interface but at a depth defined by the location of hydrogen microcavities. This mechanism,
named Smart-cut, results in a rough SOI structure (Fig. 4.2(c4)). The process is completed by touch-
polishing to erase the surface roughness.
The extraordinary potential of the Smart-cut approach comes from several distinct advantages: (1)
the etch-back step is avoided, (2) the second wafer (Fig. 4.2(c3)) being recyclable, UNIBOND is a single-
wafer process, (3) only conventional equipment is needed for mass production, (4) relatively inexpensive
12-in. wafers are manufacturable, and (5) the thickness of the silicon film and/or buried oxide can be
adjusted to match most device configurations (ultra-thin CMOS or thick-film power transistors and
sensors). The defect density in the film is very low, the electrical properties are excellent, and the BOX
quality is comparable to that of the original thermal oxide. The Smart-cut process is adaptable to a variety
of materials: SiC or III–V compounds on insulator, silicon on diamond, etc. Smart-cut can be used to
transfer already fabricated bulk-Si CMOS circuits on glass or on other substrates.
The problem for SOI is that such an enthusiastic list of merits did not perturb the fantastic progress
and authority of bulk Si technology. There has been no room or need so far for an alternative technology
such as SOI. However, the SOI community remains confident that the SOI advantages together with the
predictable approach of bulk-Si limits will be enough for SOI to succeed soon.
CMOS Circuits
High-performance SOI CMOS circuits, compatible with LV/LP and high-speed ULSI applications,
have been repeatedly demonstrated on submicron devices. Quarter-micron ring oscillators showed
delay times of 14 ps/stage at 1.5 V7 and of 45 ps/stage at 1V.8 PLL operated at 2.5 V and 4 GHz dissipate
19 mW only.8 Microwave SOS MOSFETs, with T-gate configuration, had 66-MHz maximum frequency
and low noise figure.3
More complex SOI circuits, with direct impact on mainstream microelectronics, have also been
fabricated: 0.5 V–200 MHz microprocessor,9 4 Mb SRAM,10 16 Mb and 1 Gb DRAM,11 etc.1,12 Several
companies (IBM, Motorola, Sharp) have announced the imminent commercial deployment of ‘SOI-
enhanced’ PC processors and mobile communication devices.
CMOS SOI circuits show capability of successful operation at temperatures higher than 300°C: the
leakage currents are much smaller and the threshold voltage is less temperature sensitive (≈0.5mV/°C
for fully depleted MOSFETs) than in bulk Si.13 In addition, many SOI circuits are radiation-hard, able
to sustain doses above 10 Mrad.
Bipolar Transistors
As a consequence of the small film thickness, most bipolar transistors have a lateral configuration. The
implementation of BiCMOS technology on SOI has resulted in devices with a cutoff frequency above
27 GHz.14 Hybrid MOS–bipolar transistors with increased current drive and transconductance are formed
by connecting the gate to the floating body (or base); the MOSFET action governs in strong inversion
whereas, in weak inversion, the bipolar current prevails.12
Vertical bipolar transistors have been processed in thick-film SOI (wafer bonding or epitaxial growth
over SIMOX). An elegant solution for thin-film SOI is to replace the buried collector by an inversion
layer activated by the back gate.12
High-Voltage Devices
Lateral double-diffused MOSFETs (DMOS), with long drift region, were fabricated on SIMOX and
showed 90 V/1.3A capability.15 Vertical DMOS can be accommodated in thicker wafer-bonding SOI.
The SIMOX process offers the possibility to synthesize locally a buried oxide (‘interrupted’ SIMOX,
Fig. 4.2(b5)). Therefore, a vertical power device (DMOS, IGBT, UMOS, etc.), located in the bulk region
of the wafer, can be controlled by a low-power CMOS/SOI circuit (Fig. 4.3(a)). A variant of this concept
is the ‘mezzanine’ structure, which served for the fabrication of a 600 V/25A smart-power device.16 Double
SIMOX (Fig. 4.2(b3)) has also been used to combine a power MOSFET with a double-shielded high-
voltage lateral CMOS and an intelligent low-voltage CMOS circuit.17
Innovative Devices
Most innovative devices make use of special SOI features, including the possibility to (1) combine bulk
Si and SOI on a single chip (Fig. 4.3(a)), (2) adjust the thickness of the Si overlay and buried oxide, and
(3) implement additional gates in the buried oxide (Fig. 4.3(b)), by ELO process or by local oxidation
of the sandwiched Si layer in double SIMOX (Fig. 4.2(b3)).
4-6 VLSI Technology
FIGURE 4.3 Examples of innovative SOI devices: (a) combined bipolar (or high power) bulk-Si transistor with low-
voltage SOI CMOS circuits, (b) dual-gate transistors, (c) pressure sensor, and (d) gate all-around (GAA) MOSFET.
SOI is an ideal material for microsensors because the Si/BOX interface gives a perfect etch-stop mark,
making it possible to fabricate very thin membranes (Fig. 4.3(c)). Transducers for detection of pressure,
acceleration, gas flow, temperature, radiation, magnetic field, etc. have successfully been integrated on SOI.1,16
The feasibility of three-dimensional circuits has been demonstrated on ZMR structures. For example, an
image-signal processor is organized in three levels: photodiode arrays in the upper SOI layer, fast A/D
converters in the intermediate SOI layer, and arithmetic units and shift registers in the bottom bulk Si level.18
The gate all-around (GAA) transistor of Fig. 4.3(d), based on the concept of volume inversion, is
fabricated by etching a cavity into the BOX and wrapping the oxidized transistor body into a poly-Si
gate.12 Similar devices include the Delta transistor19 and various double-gate MOSFETs.
The family of SOI devices also includes optical waveguides and modulators, microwave transistors
integrated on high-resistivity SIMOX, twin-gate MOSFETs, and other exotic devices.1,12 They do not
belong to science fiction: the devices have already been demonstrated in terms of technology and
functionality… even if most people still do not believe that they can operate.
FIGURE 4.4 Generic front-channel characteristics of a fully depleted n-channel SOI MOSFET for accumulation
(A), depletion (D), and inversion (I) at the back interface: (a) ID( V G1 ) curves in strong inversion, (b) log ID( V G1 )
curves in weak inversion, and (c) transconductance gm( V G1 ) curves.
to the opposite gate. Due to interface coupling, the front-gate measurements are all reminiscent of the
back-gate bias and quality of the buried oxide and interface.
Totally new ID(VG) relations apply to fully depleted SOI–MOSFETs whose complex behavior is con-
trolled by both gate biases. The typical characteristics of the front-channel transistor are schematically
illustrated in Fig. 4.4, for three distinct bias conditions of the back interface (inversion, depletion, and
accumulation), and will be explained next.
Threshold Voltage
The lateral shift of ID( V G1 ) curves (Fig. 4.4(a)) is explained by the linear variation of the front-channel
dep dep
threshold voltage, V T1 , with back-gate bias. This potential coupling causes V T1 to decrease linearly, with
increasing V G2 , between two plateaus corresponding, respectively, to accumulation and inversion at the
back interface:20
C si C ox2 ( V G2 – V G2 )
acc
dep acc
V T1 = V T1 – -------------------------------------------------- (4.1)
C ox1 ( C ox2 + C si + C it2 )
acc
where V T1 is the threshold voltage when the back interface is accumulated
C ox1 + C si + C it1 Q si
V T1 = Φ fb1 + -----------------------------------
acc
- 2Φ F – -----------
- (4.2)
C ox1 2C ox1
acc
and V G2 is given by
C si Q si
V G2 = Φ fb2 – --------
acc
- 2Φ F – -----------
- (4.3)
C ox2 2C ox2
In the above equations, Csi, Cox , and Cit are the capacitances of the fully depleted film, oxide, and interface
traps, respectively; Qsi is the depletion charge, ΦF is the Fermi potential, and Φfb is the flat-band potential.
The subscripts 1 and 2 hold for the front- or the back-channel parameters and can be interchanged to
account for the variation of the back-channel threshold voltage V T2 with V G1 .
The difference between the two plateaus, ∆V T1 = ( C si ⁄ C ox1 ) 2ΦF , slightly depends on doping, whereas
the slope does not. We must insist on the polyvalence of Eqs.(4.1) to (4.3) as compared to the simple
case of bulk Si MOSFETs (or partially depleted MOSFETs), where
C it 4qε si N A Φ F
V T1 = Φ fb1 + ⎛ 1 + --------1-⎞ 2Φ F + -----------------------------
- (4.4)
⎝ C ox ⎠ C ox
1 1
4-8 VLSI Technology
Subthreshold Slope
For depletion at the back interface, the subthreshold slope (Fig. 4.4(b)) is very steep and the subthreshold
swing S is given by:22
C it
= 2.3 ------ ⎛ 1 + --------1- + α 1 --------
dep kT C si ⎞
S1 - (4.5)
q ⎝ C ox1 C ox1⎠
C ox2 + C it2
-<1
α 1 = ----------------------------------- (4.6)
C si + C ox2 + C it2
accounts for the influence of back interface traps C it2 and buried oxide thickness C ox2 on the front
channel current.22
In the ideal case, where C it1, 2 ≅ 0 and the buried oxide is much thicker than both the film and the
dep
gate oxide (i.e., α1 ≅ 0), the swing approaches the theoretical limit S 1 ≅ 60 mV/decade at 300K.
Accumulation at the back interface does decouple the front inversion channel from back interface defects
but, in turn, makes α1 tend to unity (as in bulk–Si or partially depleted MOSFETs), causing an overall
degradation of the swing.
It is worth noting that the above simplified analysis and equations are valid only when the buried
oxide is thick enough, such that substrate effects occurring underneath the BOX can be overlooked. The
capacitances of the BOX and Si substrate are actually connected in series. Therefore, the swing may
depend, essentially for thin buried oxides, on the density of the traps and surface charge (accumulation,
depletion, or inversion) at the third interface: BOX–Si substrate. The general trend is that the subthreshold
slope improves for thinner silicon films and thicker buried oxides.
Transconductance
For strong inversion and ohmic region of operation, the front-channel drain current and transconduc-
tance are given by
C ox1 WV D µ1
- ⋅ ------------------------------------------------------
I D = --------------------- - ⋅ ( V G1 – V T1 ( V G2 ) ) (4.7)
L 1 + θ 1 ( V G1 – V T1 ( V G2 ) )
C ox1 WV D µ1
- ⋅ -------------------------------------------------------------
g m1 = --------------------- -2 (4.8)
L [ 1 + θ1 ( VG – VT ( VG ) ) ] 1 1 2
where µ1 is the mobility of front-channel carriers, and θ1 is the mobility attenuation coefficient.
The complexity of the transconductance curves in fully depleted MOSFETs (Fig. 4.4(c)) is explained
by the influence of the back gate bias via V T1 ( V G2 ) . The effective mobility and transconductance peak
are maximum for depletion at the back interface, due to combined effects of reduced vertical field and
series resistances.
Silicon on Insulator Technology 4-9
An unusual feature is the distortion of the transconductance (curve I, Fig. 4.4(c)), which reflects the
possible activation of the back channel, far before the inversion charge build-up is completed at the front
channel.23 While the front interface is still depleted, increasing V G1 reduces the back threshold voltage
and eventually opens the back channel. The plateau of the front-channel transconductance (Fig. 4.4(c))
can be used to derive directly the back-channel mobility.
Volume Inversion
In thin and low-doped films, the simultaneous activation of front and back channels induces by continuity
(i.e., charge coupling) the onset of volume inversion.24 Unknown in bulk Si, this effect enables the inversion
charge to cover the whole film. Self-consistent solutions of Poisson and Schrödinger equations indicate
that the maximum density of the inversion charge is reached in the middle of the film. This results in
increased current drive and transconductance, attenuated influence of interface defects (traps, fixed
charges, roughness), and reduced 1/f noise.
Double-gate MOSFETs (DELTA and GAA transistors), designed to take full advantage from volume
inversion, also benefit from reduced short-channel effects (VT drop, punch-through, DIBL, hot-carrier
injection, etc.), and are therefore very attractive, if not unique, devices for down-scaling below 30-nm
gate length.
Defect Coupling
In fully depleted MOSFETs, carriers flowing at one interface may sense the presence of defects located
at the opposite interface. Defect coupling is observed as an apparent degradation of the front-channel
properties, which is actually induced by the buried oxide damage. This unusual mechanism is notorious
after back interface degradation via radiation or hot-carrier injection (see also Fig. 4.7 in Section 4.7).
FIGURE 4.5 Parasitic effects in partially depleted SOI MOSFETs: (a) kink in ID(VD) curves, (b) latch in ID(VG)
curves, (c) drain current overshoot, (d) current undershoot, (e) premature breakdown, and (f) self-heating.
from ideal. Their intrinsic resistance does not allow the body to be perfectly grounded and may generate
additional noise. A floating body is then preferable to a poor body contact.
An exciting partially depleted device is the dynamic-threshold DT-MOS transistor. It is simply config-
ured by interconnecting the gate and the body. As the gate voltage increases in weak inversion, the
simultaneous raise in body potential makes the threshold voltage decrease. DT-MOSFETs achieve perfect
gate-charge coupling, maximum subthreshold slope, and enhanced current, which are attractive features
for LV/LP circuits.
FIGURE 4.6 Typical short-channel effects in fully depleted SOI MOSFETs: (a) threshold voltage roll-off for different
thicknesses of film and buried oxide26 and (b) subthreshold swing degradation below 0.2-µm channel length for
various temperatures.13
A degradation of the subthreshold swing is observed in very short (L ≤ 0.1–0.5 µm), fully depleted
MOSFETs (Fig. 4.6(b)). Two effects are involved: (1) conventional charge sharing, and (2) a surprising
non-uniform coupling effect. We have seen that the subthreshold swing is minimum for depletion and
increases for inversion at the back interface. In very short transistors, the lateral profile of the back
interface potential can be highly inhomogeneous: from depletion in the middle of the channel to weak
inversion near the channel ends, due to the proximity of source and drain regions. This localized weak
inversion region explains the degradation of the swing.13
The transconductance is obviously improved in deep submicron transistors. Velocity saturation
occurs as in bulk silicon. The main short-channel limitation of the transconductance comes from
series resistance effects.
The lifetime of submicron MOSFETs is affected by hot-carrier injection into the gate oxide(s). The
degradation mechanisms are more complex in SOI than in bulk-Si, due to the presence of two oxides,
two channels, and related coupling mechanisms. For example, in Fig. 4.7, the front-channel threshold
voltage is monitored during back channel stress. The shift ∆ V T1 , measured for V G2 = 0 (depleted back
interface), would imply that many defects are being generated at the front interface. Such a conclusion
is totally negated by measurements performed with V G2 = –40V: the influence of buried-oxide defects
is now masked by the accumulation layer and indeed the apparent front-interface damage disappears
(∆ V T1 ≅ 0).28
In n-channels, the defects are created at the interface where the electrons flow; exceptionally,
injection into the opposite interface may arise when the transistor is biased in the breakdown region.
Although the device lifetime is relatively similar in bulk Si and SOI, the influence of stressing bias is
different: SOI MOSFETs degrade less than bulk Si MOSFETs for VG ≅ VD /2 (i.e., for maximum substrate
current) and more for VG ≅ VT (i.e., enhanced hole injection). Device aging is accelerated by accumu-
lating the back interface.28
In p-channels, the key mechanism involves the electrons generated by front-channel impact ionization,
which become trapped into the buried oxide. An apparent degradation of the front interface again occurs
via coupling.28
FIGURE 4.7 Front-channel threshold voltage shift during back-channel stress in a SIMOX MOSFET.28 The apparent
degradation of the gate oxide disappears when the stress-induced defects in the buried oxide are masked by interface
accumulation ( V G2 = –40 V).
The minimum dimensions thus far achieved for SOI MOSFETs are: 70 nm length, 10 nm width
(quantum wires), and 1 to 2 nm thickness.21 When these features will be cumulative in a single transistor,
the body volume (≤10–18 cm3!) will contain 104–105 silicon atoms and 0 to 1 defects. The body doping
(1017–1018 cm–3) will be provided by a unique impurity, whose location may become important. Moreover,
quantum transport phenomena are already being observed in ultra-thin SOI transistors. It is clear that
new physical concepts, ideas, and modeling tools will be needed to account for minimum-size mecha-
nisms in order to take advantage of them.
As far as the technology is concerned, a primary challenge is the mass-production of SOI wafers with
large diameter (≥12 in.), low defect content, and reasonable cost (2 to 3 times higher than for bulk-Si
wafers). The thickness uniformity of the silicon layer is especially important for fully depleted MOSFETs
because it governs the fluctuations of the threshold voltage. It is predictable that several SOI technologies
will not survive, except for special niches.
There is a demand for appropriate characterization techniques, either imported from other semicon-
ductors or entirely conceived for SOI.1 Such a pure SOI technique is the pseudo-MOS transistor (Ψ–MOS-
FET).29 Ironically, it behaves very much like the MOS device that Shockley attempted to demonstrate 50
years ago but, at that time, he didn’t have the chance to know about SOI. The inset of Figure 4.8 shows
that the Si substrate is biased as a gate and induces a conduction channel (inversion or accumulation)
at the film–oxide interface. Source and drain probes are used to measure ID(VG) characteristics. The
Ψ–MOSFET does not require any processing; hence, valuable information is directly available: quality
of the film, interface and oxide, electron/hole mobilities, and lifetime.
Full CMOS processing must address typical SOI requirements such as the series resistance reduction
in ultra-thin MOSFETs (via local film oxidation, elevated source and drain structures, etc.), the lowering
of the source–body barrier by source engineering (silicidation, Si–Ge, etc.), the control of the parasitic
bipolar transistor, and the limitation of self-heating effects. It is now clear that the best of SOI is certainly
not achievable by simply using a very good bulk-Si technology. For example, double-gate SOI MOSFETs
deserve special processing and design.
According to process engineers and circuit designers, partially depleted SOI MOSFETs are more user
friendly as they maintain the flavor of bulk-Si technology. On the other hand, fully depleted transistors
have superior capability; they need to be domesticated in order to become more tolerant to short-channel
effects. A possible solution, which requires further investigation, is the incorporation of a ground plane
underneath the buried oxide.
Advanced modeling is required for correct transcription of the transistor behavior, including the
transient effects due to body charging and discharging, floating-body mechanisms, bipolar transistor,
dual-gate operation, quantum effects, self-heating, and short-channel limitations. Based on such physical
models, compact models should then be conceived for customized simulation and design.
It is obvious that SOI does need SOI-dedicated CAD libraries. This implies a substantial amount
of work which, in turn, will guarantee that the advantages and peculiar constraints of SOI devices
are properly accounted for. The optimum configuration of memories, microprocessors, DSP, etc.,
will most likely be different in SOI as compared to bulk. Not only can SOI afford to combine
fully/partially depleted, low/high power, and DT-MOSFETs in a single chip, but also the basic
mechanisms of operation may differ.
4.9 Conclusion
For the next millennium, SOI offers the opportunity to integrate high-performance and/or innovative
devices that can push away the present frontiers of the CMOS down-scaling. SOI will play a significant
role in the future of microelectronics if subsisting problems can be rapidly solved. The short-term
prospects of SOI-based microelectronics will also closely depend on the penetration rate of LV/LP
SOI circuits into the market. Not only does SOI offer enhanced performance, but also most of SOI
disadvantages (self-heating, hot carriers, early breakdown, etc.) tend to disappear for operation at
low voltage.
A key challenge is associated with industrial strategy, which must be oriented to overcome the
bulk-Si monocultural barrier. Designers, process engineers, and managers are extremely busy loading
the bulk-Si machine. When, eventually, they can afford to take a careful look at the assets of SOI
technology, they will realize the immediate and long-term benefits offered in terms of performance
and scaling extensions.
This is so because SOI is not a totally different technology — it is just a metamorphosis of silicon.
References
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Norwell, 1995.
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device performance,” J. Electrochem. Soc., 138, 3131, 1991.
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5
SiGe Technology
5.1 Introduction
The concept of bandgap engineering has been used for many years in compound semiconductors such
as gallium arsenide (GaAs) and indium phosphide (InP) to realize a host of novel electronic devices. A
bandgap-engineered transistor is compositionally altered in a manner that improves a specific device
metric (e.g., speed). A transistor designer might choose, for instance, to make a bipolar transistor that
has a GaAs base and collector region, but which also has a AlGaAs emitter. Such a device has electrical
properties that are inherently superior to what could be achieved using a single semiconductor. In addition
to simply combining two different materials (e.g., AlGaAs and GaAs), bandgap engineering often involves
compositional grading of materials within a device. For instance, one might choose to vary the Al content
in an AlGaAs/GaAs transistor from a mole fraction of 0.4 to 0.6 across a given distance within the emitter.
Device designers have long sought to combine the bandgap engineering techniques enjoyed in
compound semiconductors technologies with the fabrication maturity, high yield, and hence low cost
associated with conventional silicon (Si) integrated circuit manufacturing. Epitaxial silicon-germanium
(SiGe) alloys offer considerable potential for realizing viable bandgap-engineered transistors in the Si
material system. This is exciting because it potentially allows Si electronic devices to achieve perfor-
mance levels that were once thought impossible, and thus dramatically extends the number of high-
performance circuit applications that can be addressed using Si technology. This chapter reviews the
recent progress in both SiGe heterojunction bipolar transistor (HBT) technology and SiGe field effect
transistor (FET) technology.
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 5-1
5-2 VLSI Technology
FIGURE 5.1 Effective thickness versus effective strain for SiGe strained layer epitaxy. Shown are a theoretical
stability curve (Matthews-Blakeslee), and an empirical curve for UHV/CVD SiGe epitaxy. The symbols represent
actual films used in UHV/CVD SiGe HBTs.
the Ge concentration).1 The critical thickness below which the grown film is unconditionally stable
depends reciprocally on the effective strain (Fig. 5.1). Thus, for practical electronic device applications,
SiGe alloys must be thin (typically <100–200 nm) and contain only modest amounts of Ge (typically
<20–30%). It is essential for electronic devices that the SiGe films remain thermodynamically stable so
that conventional Si fabrication techniques such as high-temperature annealing, oxidation, and ion
implantation can be employed without generating defects.
From an electronic device viewpoint, the property of the strained SiGe alloy that is most often
exploited is the reduction in bandgap with strain and Ge content (roughly 75 meV per 10% Ge).2 This
band offset appears mostly in the valence band, which is particularly useful for realizing n-p-n bipolar
transistors and p-channel FETs.3 While these band offsets are modest compared to those that can be
achieved in III–V semiconductors, the Ge content can be compositionally graded to produce local
electric fields that aid carrier transport. For instance, in a SiGe HBT, the Ge content might be graded
from 0 to 15% across distances as short as 50 to 60 nm, producing built-in drift fields as large as 15
to 20 kV ⋅ cm–1. Such fields can rapidly accelerate the carriers to scattering-limited velocity (1 × 107
cm ⋅ s–1), thereby improving the transistor frequency response. Another benefit of using SiGe strained
layers is the enhancement in carrier mobility. This advantage will be exploited in SiGe channel FETs,
as discussed below.
Epitaxial SiGe strained layers on Si substrates can be successfully grown today by a number of
different techniques, including molecular beam epitaxy (MBE), ultra-high vacuum/chemical vapor
deposition (UHV/CVD), rapid-thermal CVD (RTCVD), atmospheric pressure CVD (APCVD), and
reduced pressure CVD (RPCVD). Each growth technique has advantages and disadvantages, but it is
generally agreed that UHV/CVD4 has a number of appealing features for the commercialization of
SiGe integrated circuits. The features of UHV/CVD that make it particularly suitable for manufacturing
include: (1) batch processing on up to 16 wafers simultaneously, (2) excellent doping and thickness
control on large (e.g., 200 mm) wafers, (3) very low background oxygen and carbon concentrations,
(4) compatibility with patterned wafers and hence conventional Si bipolar and CMOS fabrication
techniques, and (5) the ability to compositionally grade the Ge content in a controllable manner across
short distances. The experimental results presented in this chapter are based on the UHV/CVD growth
technique as practiced at IBM Corporation, and are representative of the state-of-the-art in SiGe
technology.
SiGe Technology 5-3
FIGURE 5.2 Transistor cutoff frequency as a function of publication date comparing Si BJT performance and the
first SiGe HBT result.
5-4 VLSI Technology
arsenic-doped polysilicon emitter layer. This approach ensures that the SiGe HBT is compatible with
commonly used (low-cost) bipolar/CMOS fabrication processes. A typical doping profile measured by
secondary ion mass spectroscopy (SIMS) of the resultant SiGe HBT is shown in Fig. 5.4.
The smaller base bandgap of the SiGe HBT can be exploited in three major ways, and is best illustrated
by examining an energy band diagram comparing a SiGe HBT with a Si BJT (Fig. 5.5). First, note the
reduction in base bandgap at the emitter–base junction. The reduction in the potential barrier at the
emitter–base junction in a SiGe HBT will exponentially increase the collector current density and, hence,
current gain (β = JC/JB) for a given bias voltage compared to a comparably designed Si BJT. Compared
to a Si BJT of identical doping profile, this enhancement in current gain is given by:
∆E ( 0 ) ⁄ kT
J C, SiGe β SiGe ∆E g, Ge ( grade ) ⁄ kT e g, Ge
------------- = ---------- = γ η ------------------------------------------------------------------------
- (5.1)
J C, Si β Si 1 – e g, Ge
– ∆E ( grade ) ⁄ kT
where γ = NCNV (SiGe)/NCNV(Si) is the ratio of the density-of-states product between SiGe and Si, and
η = Dnb(SiGe)/Dnb(Si) accounts for the differences between the electron and hole mobilities in the base.
The position dependence of the band offset with respect to Si is conveniently expressed as a bandgap
grading term (∆Eg,Ge(grade) = ∆Eg,Ge(Wb) – ∆Eg,Ge(0)). As can be seen in Fig. 5.6, which compares the
measured Gummel characteristics for two identically constructed SiGe HBTs and Si BJTs, these theoretical
expectations are clearly borne out in practice.
FIGURE 5.4 Secondary ion mass spectroscopy (SIMS) doping profile of a graded-base SiGe HBT.
SiGe Technology 5-5
FIGURE 5.5 Energy band diagram for both a Si BJT and a graded-base SiGe HBT.
FIGURE 5.6 Measured current/voltage characteristics of both SiGe HBT and Si BJT with a comparable doping profile.
Secondly, if the Ge content is graded across the base region of the transistor, the conduction band
edge becomes position dependent (refer to Fig. 5.5), inducing an electric field in the base that accelerates
the injected electrons. The base transit time is thereby shortened and the frequency response of the
transistor is improved according to:
– ∆E ( grade ) ⁄ kT
τ b, SiGe 2 1 – e g, Ge
- = --- ⎛ ----------------------------------⎞ 1 – ---------------------------------------------
f T, Si kT
------------- = ------------ (5.2)
τ b, Si f T, SiGe ⎝
η ∆E g, Ge ( grade ) ⎠ ∆E g, Ge ( grade ) ⁄ kT
5-6 VLSI Technology
Figure 5.7 compares the measured unity gain cutoff frequency (fT) of a SiGe HBT and a comparably
constructed Si BJT, and shows that an improvement in peak fT of 1.7X can be obtained with relatively
modest Ge profile grading (0–7.5% in this case). More recent studies demonstrate that peak cutoff
frequencies in excess of 100 GHz can be obtained using more aggressively designed (although still stable)
Ge profiles12 (see Fig. 5.8).
The final advantage of using a graded Ge profile in a SiGe HBT is the improvement in the output
conductance of the transistor, an important analog design metric. For a graded-base SiGe HBT, the Early
voltage (a measure of output conductance) increases exponentially compared to a Si BJT of comparable
doping, according to:
– ∆E ( grade ) ⁄ kT
V A, SiGe ∆E ( grade ) ⁄ kT 1 – e g, Ge
--------------- = e g, Ge ------------------------------------------------- (5.3)
V A, Si ( ∆E g, Ge ( grade ) ⁄ kT )
FIGURE 5.7 Measured cutoff frequency as a function of bias current for both SiGe HBT and Si BJT with a
comparable doping profile.
FIGURE 5.8 Cutoff frequency as a function of bias current for an aggressively designed UHV/CVD SiGe HBT.
SiGe Technology 5-7
In essence, the position dependence of the bandgap in the graded-base SiGe HBT weights the base profile
toward the collector region, making it harder to deplete the base with collector-base bias, hence yielding
a larger Early voltage. A transistor with a high Early voltage has a very flat common-emitter output
characteristic, and hence low output conductance. For the device shown in Fig. 5.6, the Early voltage
increases from 18 V in the Si BJT to 53 V in the SiGe HBT, a 3X improvement.
SiGe HBTs have been successfully integrated with conventional high-performance Si CMOS to realize
a SiGe BiCMOS technology.15 The SiGe HBT and ac performance in this SiGe BiCMOS technology is
shown in Fig. 5.9, and is not compromised by the addition of the CMOS devices. Table 5.1 shows the
suite of resultant elements in this SiGe BiCMOS technology. Two SiGe HBTs are available, one with a
reduced collector implant and hence higher BVCEO (5.3 V vs. 3.3 V) that is suitable for RF power
applications. Table 5.2 gives the typical SiGe HBT device parameters at 300K.
Bandgap-engineered SiGe HBTs have other attractive features that make them ideal candidates for
certain circuit applications. For instance, Si BJT technology is well known to have superior low-frequency
noise properties compared to compound semiconductor technologies. Low-frequency noise is often a
major limitation for RF and microwave systems because it directly limits the spectral purity of the
FIGURE 5.9 Cutoff frequency, maximum oscillation frequency, and small-signal base resistance for a small-geom-
etry, state-of-the-art SiGe HBT.
TABLE 5.2 Typical Parameters for a SiGe HBT with AE = 0.5 × 2.5 µm2. All ac
Parameters Were Measured at VCB = 1.0V and fmax Was Extracted Using MAG
Parameter Standard SiGe HBT High-BVCEO SiGe HBT
Peak β 113 97
VA (V) 61 132
βVA (V) 6,893 12,804
Peak fT (GHz) 48 28
rbb at peak fT (Ω) 80 N/A
Peak fmax (GHz) 69 57
BVCEO (V) 3.3 5.3
BVEBO (V) 4.2 4.1
Peak fT × BVCEO (GHz V) 158 143
transmitted signal. Recent work suggests that SiGe HBTs have low-frequency properties as good as or
better than Si BJTs, superior to that obtained in AlGaAs/GaAs HBTs and Si CMOS (Fig. 5.10).29,30 The
broadband (RF) noise in SiGe HBTs is competitive with GaAs MESFET technology and superior to Si
BJTs. In addition, SiGe HBTs have recently been shown to be very robust with respect to ionizing radiation,
an important feature for space-based electronic systems.31,32 Finally, cooling enhances all of the advantages
of a SiGe HBT. In striking contrast to a Si BJT, which strongly degrades with cooling, the current gain,
Early voltage, cutoff frequency, and maximum oscillation frequency (fmax) all improve significantly as the
temperature drops.33–35 This means that the SiGe HBT is well suited for operation in the cryogenic
environment (e.g., 77K), historically the exclusive domain of Si CMOS and III–V compound semicon-
ductor technologies. Cryogenic electronics is in growing use in both military and commercial applications
such as space-based satellites, high-sensitivity instrumentation, high-TC superconductors, and future
cryogenic computers.
FIGURE 5.10 Low-frequency noise spectra of SiGe HBT and a conventional Si nFET of identical geometry.
SiGe Technology 5-9
in a conventional MOSFET, particularly at high gate bias. If, in addition, the holes are confined to a
region of the semiconductor that is intentionally left undoped, the result is a reduction in ionized
impurity scattering and, hence, further increase in mobility.2 This is exactly the approach taken in
bandgap-engineered compound semiconductor FETs known as HEMTs (high electron mobility tran-
sistor). Second, the strain associated with SiGe epitaxy is known to lift the degeneracy of the light and
heavy hole valence bands, resulting in a reduced hole effective mass and hence higher hole mobility.3
Because it is the hole mobility that is improved in strained SiGe, and the valence band offset can be
used to confine these holes, the p-channel FET (pFET) is the logical device to pursue with SiGe bandgap
engineering. A SiGe pFET with an improved hole mobility is particularly desirable in CMOS technology
because the conventional Si pFET has a mobility that is about a factor of two lower than the Si nFET
mobility. This mobility asymmetry between pFET and nFET in conventional Si CMOS technology
requires a doubling of the pFET gate width, and thus a serious real estate penalty, to obtain proper
switching characteristics in the CMOS logic gate. If SiGe can be used to equalize the pFET and nFET
mobilities, then substantial area advantages can be realized in CMOS logic gates, and tighter packing
densities achieved.
It is interesting to note that despite the fact that the SiGe HBT is the most commercially mature SiGe
device, the first SiGe FET (actually a HEMT structure) predates the first SiGe HBT by one year, having
been first reported in 1986.36,37 A number of different SiGe pFET designs have been successfully
demonstrated38–43 with improvements in mobility as high as 50% at 0.25-µm gate lengths.40 Figure 5.11
shows perhaps the simplest configuration of a SiGe pFET, which consists of a SiGe hole channel buried
underneath a thin Si cap layer and the conventional thermal oxide.44,45 In this case, the entire device is
fabricated on a silicon-on-sapphire substrate to improve microwave performance. Significant mobility
advantage can be realized over a comparable Si pFET (Fig. 5.12).
Because a complementary circuit configuration offers many advantages from a power dissipation
standpoint, the realization of n-channel SiGe devices is highly desirable. Strictly speaking, this is not
possible in strained SiGe on Si substrates because only a valence band offset is available and the electrons
cannot be confined as in the SiGe pFET. Fortunately, however, recent work46–51 using strained Si on
relaxed SiGe layers has proven particularly promising because it provides a conduction band offset and
enhanced electron mobility compared to Si.
FIGURE 5.12 Effective mobility as a function of gate drive comparing SiGe pFETs on SOS and conventional Si
pFETs on SOS.
The fabrication of strained Si nFETs on relaxed SiGe layers is, in general, more complicated than
fabricating strained SiGe pFETs in Si substrates. For the strained Si nFET, a graded SiGe buffer layer is
used to reduce and confine the dislocations associated with the growth of relaxed SiGe layers.46 Using
this technique, both strained Si nFETs and strained SiGe pFETs can be jointly fabricated to form a Si-
based heterojunction CMOS (HCMOS) technology. Figure 5.13 shows a schematic cross-section of such
a Si/SiGe HCMOS technology,51 and represents the state-of-the-art in the field of Si/SiGe HCMOS.
Observe that the conducting channels of both transistors are grown in a single step (using UHV/CVD
in this case), and electron and hole confinement occurs in the strained SiGe and strained Si for the pFET
and nFET, respectively. In this technology, both the pFET and nFET are realized in a planar structure,
and are expected to show substantial improvements in performance over conventional Si CMOS. With
layer and doping profile optimization, the parasitic surface channel (which degrades mobility) can be
minimized. Simulation results of anticipated circuit performance indicate that substantial improvements
(4 to 6X) in power-delay product over conventional Si CMOS can be obtained using Si/SiGe HCMOS
technology at 0.2-µm effective gate length.
FIGURE 5.13 Schematic device cross-section of SiGe CMOS technology, consisting of a strained SiGe pFET and
a strained Si nFET (after Ref. 51).
the future evolution of SiGe technology. In addition, it has recently been shown that low concentrations
of C can serve to dramatically reduce boron diffusion in conventional SiGe HBTs.52 This has the potential
to allow much more aggressive SiGe HBT profiles to be realized with stable SiGe strained layers. More
research is required to quantify the impact of C on the device electrical characteristics, although initial
studies appear promising.
Acknowledgments
The author would like to thank D.L. Harame, B.S. Meyerson, S. Subbanna, D. Ahlgren, M. Gilbert,
K. Ismail, and the members of the SiGe team at IBM Corporation, as well as the past and present
members of the Auburn University SiGe research group (A. Joseph, D. Richey, L. Vempati, S. Mathew,
J. Roldán, G. Bradford, G. Niu, B. Ansley, K. Shivaram, G. Banerjee, S. Zhang, S. Salmon, and
U. Gogineni) for their contributions to this work. The support of the Alabama Microelectronics
Science and Technology Center, ONR, DARPA, NRL, U.S. Army SSDC, Navy NCCOSC, Navy Crane,
and MRC are gratefully acknowledged.
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6
SiC Technology
6.1 Introduction
Silicon carbide (SiC)-based semiconductor electronic devices and circuits are presently being developed
for use in high-temperature, high-power, and/or high-radiation conditions under which conventional
semiconductors cannot adequately perform. Silicon carbide’s ability to function under such extreme
conditions is expected to enable significant improvements to a far-ranging variety of applications and
systems. These range from greatly improved high-voltage switching1–4 for energy savings in public electric
power distribution and electric motor drives, to more powerful microwave electronics for radar and
communications,5–7 to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and auto-
mobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC
power MOSFETs and diode rectifiers would operate over higher voltage and temperature ranges, have
superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly
rated silicon-based devices.8 However, these tremendous theoretical advantages have yet to be realized in
experimental SiC devices, primarily due to the fact that SiC’s relatively immature crystal growth and
device fabrication technologies are not yet sufficiently developed to the degree required for reliable
incorporation into most electronic systems.9
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 6-1
6-2 VLSI Technology
This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences
(both good and bad) between SiC electronics technology and well-known silicon VLSI technology are
highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale
applications. Key crystal growth and device-fabrication issues that presently limit the performance and
capability of high-temperature and/or high-power SiC electronics are identified.
FIGURE 6.1 Schematic cross-section {(1120) plane} of the 6H-SiC polytype. (Modified from Ref. 10. With
permission.)
TABLE 6.1 Comparison of Selected Important Semiconductors of Major SiC Polytypes with Silicon and
GaAs
Property Silicon GaAs 4H-SiC 6H-SiC 3C-SiC
Bandgap (eV) 1.1 1.42 3.2 3.0 2.3
Relative dielectric constant 11.9 13.1 9.7 9.7 9.7
Breakdown field ND = 1017 cm–3 0.6 0.6 //c-axis: 3.0 // c-axis: 3.2 >1.5
(MV/cm) ⊥ c-axis: >1
Thermal conductivity (W/cm-K) 1.5 0.5 3–5 3–5 3–5
Intrinsic carrier concentration (cm–3) 1010 1.8 × 106 ~10–7 ~10–5 ~10
Electron mobility @ ND =1016 cm–3 1200 6500 //c-axis: 800 //c-axis: 60 750
(cm2/V-s) ⊥ c-axis: ⊥ c-axis:
800 400
Hole mobility @ NA =1016 cm–3 420 320 115 90 40
(cm2/V-s)
Saturated electron velocity (107 cm/s) 1.0 1.2 2 2 2.5
Donor dopants & shallowest P: 45 Si: 5.8 N: 45 N: 85 N: 50
ionization energy (meV) As: 54 P: 80 P: 80
Acceptor dopants & shallowest B: 45 Be, Mg, C: Al: 200 Al: 200 Al: 270
ionization energy (meV) 28 B: 300 B: 300
1998 Commercial wafer diameter (cm) 30 15 5 5 None
Note: Data compiled from Refs. 11–13, 15, and references therein. (With permission.)
6-4 VLSI Technology
For comparison, Table 6.1 also includes comparable properties of silicon and GaAs. Because silicon is
the semiconductor employed in most commercial solid-state electronics, it is the yardstick against which
other semiconductor materials must be evaluated. To varying degrees, the major SiC polytypes exhibit
advantages and disadvantages in basic material properties compared to silicon. The most beneficial
inherent material superiorities of SiC over silicon listed in Table 6.1 are its exceptionally high breakdown
electric field, wide bandgap energy, high thermal conductivity, and high carrier saturation velocity. The
electrical device performance benefits that each of these properties enable are discussed in the next
section, as are system-level benefits enabled by improved SiC devices.
FIGURE 6.2 Cross-section of power MOSFET structure showing various internal resistances. The resistance RD
of the N-Drift Region is the dominant resistance in high-voltage power devices. (From Ref. 8. With permission.)
FIGURE 6.3 Simulated forward conduction characteristics of ideal Si and SiC 3000 V power MOSFETs and
Schottky rectifiers. The high breakdown field of SiC relative to silicon (Table 6.1) enables the blocking voltage
region (N-Drift Region in Fig. 6.2) to be roughly 10X thinner and 10X heavier-doped, permitting a roughly 100-
fold increase in on-state current density for the 3000-V SiC devices relative to 3000-V silicon devices. (From Ref.
8. With permission.)
6-6 VLSI Technology
frequencies with much greater efficiency (i.e., less switching energy loss). Higher switching frequency in
power converters is highly desirable because it permits use of proportionally smaller capacitors, inductors,
and transformers, which in turn can greatly reduce overall system size and weight.
While SiC’s smaller on-resistance and faster switching help minimize energy loss and heat generation,
SiC’s higher thermal conductivity enables more efficient removal of waste heat energy from the active
device. Because heat energy radiation efficiency increases greatly with increasing temperature difference
between the device and the cooling ambient, SiC’s ability to operate at high junction temperatures permits
much more efficient cooling to take place, so that heatsinks and other device-cooling hardware (i.e., fan
cooling, liquid cooling, air conditioning, etc.) typically needed to keep high-power devices from over-
heating can be made much smaller or even eliminated.
While the preceding discussion focused on high-power switching for power conversion, many of the
same arguments can be applied to devices used to generate and amplify RF signals used in radar and
communications applications. In particular, the high breakdown voltage and high thermal conductivity,
coupled with high carrier saturation velocity, allow SiC microwave devices to handle much higher power
densities than their silicon or GaAs RF counterparts, despite SiC’s disadvantage in low-field carrier
mobility (Section 6.6).6,7,23
and availability are a prerequisite for commercial mass-production of semiconductor electronics. Many
semiconductor materials can be melted and reproducibly recrystallized into large, single crystals with
the aid of a seed crystal, such as in the Czochralski method employed in the manufacture of almost all
silicon wafers, enabling reasonably large wafers to be mass-produced. However, because SiC sublimes
instead of melting at reasonably attainable pressures, SiC cannot be grown by conventional melt-growth
techniques. This prevented the realization of SiC crystals suitable for mass-production until the late
1980s. Prior to 1980, experimental SiC electronic devices were confined to small (typically ~1 cm2),
irregularly shaped SiC crystal platelets (Fig. 6.4, right side) grown as a by-product of the Acheson process
for manufacturing industrial abrasives (e.g., sandpaper)27 or by the Lely process.28 In the Lely process,
SiC sublimed from polycrystalline SiC powder at temperatures near 2500°C are randomly condensed on
the walls of a cavity forming small hexagonally shaped platelets. While these small, nonreproducible
crystals permitted some basic SiC electronics research, they were clearly not suitable for semiconductor
mass-production. As such, silicon became the dominant semiconductor fueling the solid-state technology
revolution, while interest in SiC-based microelectronics was limited.
FIGURE 6.4 Mass-produced 2.5-cm diameter 6H-SiC wafer manufactured circa 1990 via seeded sublimation by
Cree Research (left), and 6H-SiC Lely and Acheson platelet crystals (right) representative of single-crystal SiC
substrates available prior to 1989. 5.1-cm diameter seeded sublimation SiC wafers entered the commercial market
in 1997.
single crystals of SiC that could be cut and polished into mass-produced SiC wafers. The basic growth
process is based on heating polycrystalline SiC source material to ~2400°C under conditions where it
sublimes into the vapor phase and subsequently condenses onto a cooler SiC seed crystal. This produces
a somewhat cylindrical boule of single-crystal SiC that grows taller at a rate of a few millimeters per
hour. To date, the preferred orientation of the growth in the sublimation process is such that vertical
growth of a taller cylindrical boule proceeds along the [0001] crystallographic c-axis direction (i.e., vertical
direction in Fig. 6.1). Circular “c-axis” wafers with surfaces that lie normal (perpendicular) to the c-axis
can be sawed from the roughly cylindrical boule. While other growth orientations (such as growth along
the a-axis) continue to be investigated, the electronic quality of this material has thus far proven inferior
to c-axis-grown wafers.36,37
Commercially Available SiC Wafers
After years of further development of the sublimation growth process, Cree Research became the first
company to sell 2.5-cm diameter semiconductor wafers of 6H-SiC (Fig. 6.4, left side) in 1989.38 Only
with the development of the modified Lely seeded sublimation growth technique have acceptably large
and reproducible single-crystal SiC wafers of usable electrical quality become available. Correspondingly,
the vast majority of silicon carbide semiconductor electronics development has taken place since 1990.
Other companies have subsequently entered the SiC wafer market, and sublimation grown wafers of the
4H-SiC polytype have also been commercialized, as summarized in Table 6.2.
Commercially available 4H- and 6H-SiC wafer specifications are given in Table 6.2. N-type, p-type,
and semi-insulating SiC wafers are commercially available at different prices. Wafer size, cost, and quality
are all very critical to the manufacturability and process yield of mass-produced semiconductor micro-
electronics. Compared to commonplace silicon and GaAs wafer standards, present-day 4H- and 6H-SiC
wafers are small, expensive, and generally of inferior quality. In addition to high densities of crystalline
defects such as micropipes and closed-core screw dislocations discussed in the next subsection,
SiC Technology 6-9
TABLE 6.2 Commercial Vendors and Specifications of Selected Sublimation-Grown SiC Single-
Crystal Wafers
Wafer Micropipes Price
Vendor [Ref.] Year Product Diameter (#/cm2) (U.S.$)
Cree 1993 6H n-type, Si-face, R-Grade 3.0 cm 200–1000 1000
[38] 6H n-type, Si-face, P-Grade 3.0 cm 200–1000 2900
6H n-type, C-face, P-Grade 3.0 cm 200–1000 3000
6H p-type, Si-face, P-Grade 3.0 cm 200–1000 3300
4H n-type, Si-face, R-Grade 3.0 cm 200–1000 3800
Cree 1997 4H n-type, Si-face, R-Grade 3.5 cm 100–200 750
[38] 4H n-type, Si-face, P-Grade 3.5 cm 100–200 1300
4H n-type, Si-face, P-Grade 3.5 cm <30 2300
1998 4H n-type, Si-face, R-Grade 5.1 cm <200 2100
4H n-type, Si-face, P-Grade 5.1 cm <200 3100
1997 4H p-type, Si-face, R-Grade 3.5 cm <200 1900
4H Semi-Insulating, R-Grade 3.5 cm <200 4800
6H n-type, Si-face, P-Grade 3.5 cm <200 1000
6H p-type, Si-face, P-Grade 3.5 cm <200 2200
Nippon Steel [142] 1997 4H n-type 2.5 cm NA NA
SiCrystal [143] 1997 4H n-type, Quality I 3.5 cm <200 1200
4H n-type, Quality III 3.5 cm 400–1000 900
4H n-type, Quality I 2.5 cm <200 600
6H n-type, Quality I 3.5 cm <200 1200
Sterling and 1998 6H n-type 3.5 cm <100 800
ATMI/Epitronics 4H n-type 3.5 cm <100 800
[144][145]
commercial SiC wafers also exhibit significantly rougher surfaces, and larger warpage and bow than is
typical for silicon and GaAs wafers.39 This disparity is not surprising considering that silicon and GaAs
wafers have undergone several decades of commercial process refinement, and that SiC is an extraordi-
narily hard material, making it very difficult to properly saw and polish. Nevertheless, ongoing wafer
sawing and polishing process improvements should eventually alleviate wafer surface quality deficiencies.
SiC Wafer Crystal Defects
While the specific electrical effects of SiC crystal defects are discussed later in Section 6.6, the micropipe
defect (Table 6.2) is regarded as the most damaging defect that is limiting upscaling of SiC electronics
capabilities.9,40 A micropipe is a screw dislocation with a hollow core and a larger Burgers vector, which
becomes a tubular void (with a hollow diameter on the order of micrometers) in the SiC wafer that
extends roughly parallel to the crystallographic c-axis normal to the polished c-axis wafer surface.41–44
Sublimation-grown 4H- and 6H-SiC wafers also contain high densities of closed-core screw dislocation
defects that, like micropipes, cause a considerable amount of localized strain and SiC lattice deforma-
tion.42,43,45,46 Similar to horizontal branches on a tree with its trunk running up the c-axis, dislocation
loops emanate out along the basal plane from screw dislocations.41,47 As shown in Table 6.2, micropipe
densities in commercial SiC wafers have shown steady improvement over a 5-year period, leading to
wafers with less than 30 micropipes per square centimeter of wafer area. However, as discussed in Section
6.6, SiC wafer improvement trends will have to accelerate if some of SiC’s most beneficial high-power
applications are going to reach timely commercial fruition.
SiC Epilayers
Most SiC electronic devices are not fabricated directly in sublimation-grown wafers, but are instead
fabricated in much higher quality epitaxial SiC layers that are grown on top of the initial sublimation-
grown wafer. Well-grown SiC epilayers have superior electrical properties and are more controllable and
reproducible than bulk sublimation-grown SiC wafer material. Therefore, the controlled growth of high-
quality epilayers is highly important in the realization of useful SiC electronics.
6-10 VLSI Technology
FIGURE 6.5 Cross-sectional schematic representation of “off-axis” polished SiC surface used for homoepitaxial
growth. When growth conditions are properly controlled and there is a sufficiently short distance between steps, Si
and C atoms impinging onto the growth surface find their way to steps where they bond and incorporate into the
crystal. Thus, ordered lateral “step-flow” growth takes place, which enables the polytypic stacking sequence of the
substrate to be exactly mirrored in the growing epilayer. (Modified from Ref. 10. With permission.)
SiC Technology 6-11
Because screw dislocations propagate up the c-axis, one could conceivably alleviate screw dislocations
by growing epilayers on SiC wafers with their surface parallel to the c-axis using “a-axis” wafers. Unfor-
tunately, efforts directed at realizing a-axis wafers and epilayers have to date been much less successful
than c-axis wafers and epilayers, primarily because defects that form and propagate up the basal plane
(the vertical wafer and epilayer growth direction in a-axis-oriented wafers) have proven more harmful
and difficult to eliminate than screw dislocations in conventional c-axis wafers and epilayers.36,37
Selected-area epitaxial growth techniques have recently led to startling reductions in GaN epilayer
defect densities.57 While selective-area epitaxial growth of 3C-SiC has been demonstrated, the applicability
of similar techniques to realizing superior electrical-quality SiC will be much more difficult due to the
step-flow homoepitaxial growth mechanism of α-SiC as well as high growth temperatures (>1400°C),
which are incompatible with conventional growth-masking materials like SiO2.
contact formation.59,60 Co-implantation of carbon with p-type dopants has recently been investigated
as a means to improve the electrical conductivity of implanted p-type contact layers.61
Following implantation, the patterning mask is stripped and a much higher temperature (~1200 to
1800°C) anneal is carried out to achieve maximum electrical activation of dopant donor or acceptor ions.
The final annealing conditions are crucial for obtaining desired electrical properties from ion-implanted
layers. At higher implant anneal temperatures, the SiC surface morphology can seriously degrade as
damage-assisted sublimation etching of the SiC surface begins to take place.62 Because sublimation etching
is driven primarily by loss of silicon from the crystal surface, annealing in silicon overpressures can be
used to prevent surface degradation during high-temperature anneals. Such overpressure can be achieved
by close-proximity solid sources, such as using an enclosed SiC crucible with SiC lid and/or SiC powder
near the wafer, or by annealing in a silane-containing atmosphere.
temperature annealing, the lowest-resistance ohmic contacts are most easily implemented on SiC degen-
erately doped by site competition (Section 6.4) or high-dose ion implantation (Section 6.5). If the SiC
doping is sufficiently degenerate, many metals deposited on a relatively clean SiC surface are ohmic in the
“as deposited” state.68 Regardless of doping, it is common practice in SiC to thermally anneal contacts to
obtain the minimum possible ohmic contact resistance. Most SiC ohmic contact anneals are performed
at temperatures around 1000°C in non-oxidizing environments. Depending on the contact metallization
employed, this anneal generally causes limited interfacial reactions (usually metal-carbide or metal-silicide
formation) that broaden and/or roughen the metal–semiconductor interface, resulting in enhanced con-
ductivity through the contact.
Truly enabling harsh-environment SiC electronics will require ohmic contacts that can reliably
withstand prolonged harsh-environment operation. Most reported SiC ohmic metallizations appear
sufficient for long-term device operation up to 300°C. SiC ohmic contacts that withstand heat soaking
under no electrical bias at 500 to 600°C for hundreds or thousands of hours in non-oxidizing gas or
vacuum environments have also been demonstrated. In air, however, there has only been demonstra-
tion to date of a contact that can withstand heat soaking (no electrical bias) for 60 hours at 650°C.69
Some very beneficial aerospace systems will require simultaneous high-temperature (T > 300°C) and
high current density operation in oxidizing air environments. Electromigration, oxidation, and other
electrochemical reactions driven by high-temperature electrical bias in a reactive oxidizing environ-
ment are likely to limit SiC ohmic contact reliability for the most demanding applications. The
durability and reliability of SiC ohmic contacts is one of the critical factors limiting the practical
high-temperature limits of SiC electronics.
SiC Schottky Contacts
Rectifying metal–semiconductor Schottky barrier contacts to SiC is useful for a number of devices,
including metal–semiconductor field-effect transistors (MESFETs) and fast-switching rectifiers. Refer-
ences 64, 65, 67, and 70 summarize electrical results obtained in a variety of SiC Schottky studies to date.
Due to the wide bandgap of SiC, almost all unannealed metal contacts to lightly doped 4H- and 6H-SiC
are rectifying. Rectifying contacts permit extraction of Schottky barrier heights and diode ideality factors
by well-known current-voltage (I-V) and capacitance-voltage (C-V) electrical measurement techniques.63
While these measurements show a general trend that Schottky junction barrier height does somewhat
depend on metal–semiconductor workfunction difference, the dependence is weak enough to suggest
that surface state charge also plays a significant role in determining the effective barrier height of SiC
Schottky junctions. At least some experimental scatter exhibited for identical metals can be attributed to
cleaning and metal deposition process differences, as well as different barrier height measurement pro-
cedures. The work by Teraji et al.,71 in which two different surface cleaning procedures prior to titanium
deposition lead to ohmic behavior in one case and rectifying behavior in the other, clearly shows the
important role that process recipe can play in determining SiC Schottky contact electrical properties.
It is worth noting that barrier heights calculated from C-V data are often somewhat higher than
barrier heights extracted from I-V data taken from the same diode. Furthermore, the reverse current
drawn in experimental SiC diodes, while small, is nevertheless larger than expected based on theoretical
substitution of SiC parameters into well-known Schottky diode reverse leakage current equations
developed for narrow-bandgap semiconductors. Bhatnagar et al.72 proposed a model to explain these
behaviors, in which localized surface defects, perhaps elementary screw dislocations where they intersect
the SiC-metal interface, cause locally reduced junction barriers in the immediate vicinity of defects.
Because current is exponentially dependent on Schottky barrier height, this results in the majority of
measured current flowing at local defect sites instead of evenly distributed over the entire Schottky
diode area. In addition to local defects, electric field crowding along the edge of the SiC Schottky barrier
can also lead to increased reverse-bias leakage current and reduced reverse breakdown voltage.15,16,63
Schottky diode edge termination techniques to relieve electric field edge crowding and improve Schottky
rectifier reverse properties are discussed later in Section 6.6. Quantum mechanical tunneling of carriers
through the barrier may also account for some excess reverse leakage current in SiC Schottky diodes.73
SiC Technology 6-15
The high-temperature operation of rectifying SiC Schottky diodes is primarily limited by reverse-bias
thermionic leakage of carriers over the junction barrier. Depending on the specific application and the
barrier height of the particular device, SiC Schottky diode reverse leakage currents generally grow to
excessive levels at around 300 to 400°C. As with ohmic contacts, electrochemical interfacial reactions
must also be considered for long-term Schottky diode operation at the highest temperatures.
From a purely electrical point of view, there are two prime operational deficiencies of SiC oxides and
MOSFETs compared to silicon MOSFETs. First, effective inversion channel mobilities in most SiC MOS-
FETs are much lower (typically well under 100 cm2/V-s for inversion electrons) than one would expect
based on silicon inversion channel MOSFET carrier mobilities. This seriously reduces the transistor gain
and current-carrying capability of SiC MOSFETs, so that SiC MOSFETs are not nearly as advantageous
as theoretically predicted. Second, SiC oxides have not proven as reliable and immutable as well-developed
silicon oxides, in that SiC MOSFETs are more prone to threshold voltage shifts, gate leakage, and oxide
failures than comparably biased silicon MOSFETs. The excellent works by Cooper80 and Brown et al.83
discuss noteworthy differences between the basic electrical properties of n-type versus p-type SiC MOS
devices. SiC MOSFET oxide electrical performance deficiencies appear mostly attributable to differences
between silicon and SiC thermal oxide quality and interface structure that cause the SiC oxide to exhibit
undesirably higher levels of interface state densities (~1011 to 1013 eV–1cm–2), fixed oxide charges (~1011
to 1012 cm–2), charge trapping, carrier oxide tunneling, and roughness-related scattering of inversion
channel carriers.
One of the most obvious differences between thermal oxidation of silicon and SiC to form SiO2 is the
presence of C in SiC. While most of the C in SiC converts to gaseous CO and CO2 and escapes the oxide
layer during thermal oxidation, leftover C species residing near the SiC–SiO2 interface nevertheless appear
to have a detrimental impact on SiO2 electrical quality.80,81 Cleaning treatments and oxidation/anneal
recipes aimed at reducing interfacial C appear to improve SiC oxide quality. Another procedure employed
to minimize detrimental carbon effects has been to form gate oxides by thermally oxidizing layers of
silicon deposited on top of SiC.84 Likewise, deposited insulators also show promise toward improving
SiC MOSFET characteristics, as Sridevan et al.85 have recently reported greatly improved SiC inversion
channel carrier mobilities (>100 cm2/V-s) using thick deposited gate insulators.
SiC surfaces are well known to be much rougher than silicon surfaces, due to off-angle polishing
needed to support SiC homoepitaxy (Fig. 6.5) as well as step-bunching (particularly pronounced in
4H-SiC) that occurs during SiC homoepilayer growth (Section 6.4).39,86 The impact of surface mor-
phology on inversion channel mobility is highlighted by the recent work of Scharnholz et al.,87 in
which improved mobility (>100 cm2/V-s) was obtained by specifically orienting SiC MOSFETs in a
direction such that current flowed parallel to surface step texture. The interface roughness of SiC may
also be a factor in poor oxide reliability by assisting unwanted injection of carriers that damage and
degrade the oxide.
As Agarwal et al.88 have pointed out, the wide bandgap of SiC reduces the potential barrier impeding
tunneling of damaging carriers through SiC thermal oxides, so that perfectly grown oxides on
atomically smooth SiC would not be as reliable as silicon thermal oxides. Therefore, it is highly
probable that alternative gate insulators will have to be developed for optimized implementation of
inversion-channel SiC FETs for the most demanding high-power and/or high-temperature electronic
applications.
SiC RF Devices
The main use of SiC RF devices appears to lie in high-frequency solid-state high-power amplification at
frequencies from around 600 MHz (UHF-band) to perhaps around 10 GHz (X-band). As discussed in
better detail in Refs. 6, 7, 23, 96, and 97, the high breakdown voltage and high thermal conductivity,
coupled with high carrier saturation velocity, allow SiC RF transistors to handle much higher power
densities than their silicon or GaAs RF counterparts, despite SiC’s disadvantage in low-field carrier
mobility (Section 6.2). This power output advantage of SiC is briefly illustrated in Fig. 6.6 for the specific
case of a Class A MESFET-based RF amplifier. The maximum theoretical RF power of a Class A MESFET
operating along the DC load line shown in Fig. 6.6 is approximated by7:
I dson ( V b – V knee )
P max = -------------------------------------
- (6.1)
8
The higher breakdown field of SiC permits higher drain breakdown voltage (Vb), permitting RF operation
at higher drain biases. Given that there is little degradation in Idson and Vknee for SiC vs. GaAs and silicon,
the increased drain voltage directly leads to higher SiC MESFET output power densities. The higher
thermal conductivity of SiC is also crucial in minimizing channel self-heating so that phonon scattering
does not seriously degrade channel carrier velocity and Idson. As discussed in Refs. 7 and 97, similar RF
output power arguments can be made for SiC-based static induction transistors (SITs).
6-18 VLSI Technology
FIGURE 6.6 Piecewise linear MESFET drain characteristic showing DC load line used in Class A RF amplifier
operation. The higher breakdown voltage Vb enabled by SiC’s higher breakdown field enables operation at higher
drain biases, leading to higher RF power densities. (From Ref. 7. With permission.)
The high power density of high-frequency SiC transistors could prove very useful in realizing solid-
state transmitters for cell phone base stations, high-definition television (HDTV) transmitters, and radar
transmitters, because it reduces the number of devices needed to generate sufficient RF power for these
applications. Fewer transistors capable of operating at higher temperatures reduces matching and cooling
requirements, leading to reduced overall size and cost of these systems. While excellent for fixed-base
high-power RF transmission systems, SiC RF transistors are not well suited for portable handheld RF
transceivers where drain voltage and power are restricted to function within the operational limitations
of small-sized battery packs.
Because rapid progress is being made toward improving the capabilities of SiC RF power transistors,
the reader should consult the latest electron device literature for up-to-date SiC RF transistor capabilities.
A late-1997 summary of solid-state high-power RF amplification transistor results, including 4H-SiC,
6H-SiC, silicon, GaAs, and GaN device results, is given in Fig. 6.7.7 Despite the fact that SiC RF transistors
are not nearly as optimized, they have still demonstrated higher power densities than silicon and GaAs
RF power transistors. The commercial availability of semi-insulating SiC substrates to minimize parasitic
capacitances is crucial to the high-frequency performance of SiC RF MESFETs. MESFET devices fabri-
cated on semi-insulating substrates are conceivably less susceptible to adverse yield consequences arising
from micropipes than vertical high-power switching devices, primarily because a c-axis micropipe can
no longer short together two conducting sides of a high field junction in most areas of the lateral channel
MESFET structure. In addition to micropipes, other non-idealities, such as variations in epilayer doping
and thickness, surface morphological defects, and slow charge trapping/detrapping phenomena causing
unwanted device I-V drift,98 also limit the yield, size, and manufacturability of SiC RF transistors.
However, increasingly beneficial SiC RF transistors should continue to evolve as SiC crystal quality and
device processing technology continues to improve.
In addition to high-power RF transistors, SiC mixer diodes show excellent promise for reducing
undesired intermodulation interference in RF receivers.99 More than 20-dB dynamic range improvement
was demonstrated using non-optimized SiC Schottky diode mixers. Following further development and
optimization, SiC-based mixers should improve the interference immunity of a number of RF systems
where receivers and high-power transmitters are closely located, as well as improve the reliability and
safety of flight RF-based avionics instruments used to guide aircraft in low-visibility weather conditions.
FIGURE 6.7 Theoretical (lines) and experimental (symbols) RF power densities of RF transistors fabricated in
silicon, GaAs, SiC, and GaN as of late 1997. (From Ref. 96. With permission.)
digital and analog signal-level functions up to 300°C when high-power output is not required.100,101 Aside
from ICs where it is advantageous to combine signal-level functions with high-power or unique SiC
sensors/MEMS onto a single chip, more expensive SiC circuits solely performing low-power signal-level
functions appear largely unjustifiable for low-radiation applications at temperatures below 250 to 300°C.
Achieving long-term operational reliability is one of the primary challenges of realizing 300 to 600°C
devices and circuits. Circuit technologies that have been used to successfully implement VLSI circuits in
silicon and GaAs, such as CMOS, ECL, BiCMOS, DCFL, etc., are to varying degrees candidates for T >
300°C SiC integrated circuits. High temperature gate-insulator reliability (Section 6.5) is critical to the
successful realization of MOSFET-based integrated circuits. Gate-to-channel Schottky diode leakage
limits the peak operating temperature of SiC MESFET circuits to around 400°C (Section 6.5). Prototype
bipolar SiC transistors have exhibited poor gains,102 but improvements in SiC crystal growth and surface
passivation should improve SiC BJT gains.103 As discussed in Section 6.5, a common obstacle to all
technologies is reliable long-term operation of contacts, interconnect, passivation, and packaging at T >
300°C. Because signal-level circuits are operated at relatively low electric fields well below the electrical
failure voltage of most micropipes, micropipes affect signal-level circuit process yields to a much lesser
degree than they affect high-field power device yields. Non-idealities in SiC epilayers, such as variations
in epilayer doping and thickness, surface morphological defects, and slow charge trapping/detrapping
phenomena causing unwanted device I–V drift, presently limit the yield, size, and manufacturability of
SiC high-temperature integrated circuits.83 However, continued progress in maturing SiC crystal growth
and device fabrication technology should eventually enable the realization of SiC VLSI circuits.
Robust circuit designs that accommodate large changes in device operating parameters with temper-
ature will be necessary for circuits to function successfully over the very wide temperature ranges (as
large as 650°C spread) enabled by SiC. While there are similarities to silicon device behavior as a function
of temperature, there are also significant differences that will present challenges to SiC integrated circuit
designers. For example, in silicon devices, dopant atoms are fully ionized at standard operating temper-
atures of interest, so that free carrier concentrations correspond with dopant impurity concentrations.14,15
Therefore, the resistivity of silicon increases with increasing temperature as phonon scattering reduces
carrier mobility. SiC device layers, on the other hand, are significantly “frozen-out” due to deeper donor
and acceptor dopant ionization energies, so that non-trivial percentages of dopants are not ionized to
produce free carriers that carry current at or near room temperature. Thus, the resistivity of SiC layers
6-20 VLSI Technology
FIGURE 6.8 Optical micrograph of 1 × 2 mm2 300°C 6H-SiC operational amplifier integrated circuit. The chip
contains 14 depletion-mode N-channel MOSFETs integrated with 19 resistors. (From Ref. 105. With permission.)
can sometimes initially decrease with increasing temperature as dopant atoms ionize to contribute more
current-conducting free carriers, then decrease similar to silicon after most dopant atoms have ionized
and increased phonon scattering degrades free carrier mobility. Thus, SiC transistor parameters can
exhibit temperature variations not found in silicon devices, so that new device-behavior models are
sometimes necessary to carry out proper design of wider-temperature range SiC integrated circuits.
Because of carrier freeze-out effects, it will be difficult to realize SiC-based ICs operational at temperatures
much lower than –55°C (the lower end of the U.S. Mil-Spec. temperature range).
Small-scale prototype logic and analog amplifier SiC-based ICs (one of which is shown in Fig. 6.8)
have been demonstrated using SiC variations of NMOS, CMOS, JFET, and MESFET device topolo-
gies.33,83,104–108 These prototypes are not commercially viable as of this writing, largely due to their high
cost, unproven reliability, and limited temperature range that is mostly covered by silicon-on-insulator-
based circuitry. However, increasingly capable and economical SiC integrated circuits will continue to
evolve as SiC crystal growth and device fabrication technology continues to improve.
FIGURE 6.9 Experimental SiC (symbols) and theoretical SiC and silicon (lines) Schottky diode specific on
resistance plotted as a function of off-state blocking voltage. While the graph clearly shows that the area-nor-
malized performance of small-area SiC devices is orders of magnitude better than silicon, these results have not
been successfully upscaled to realize large-area high-current SiC devices due to high densities of device-degrading
defects present in commercial SiC wafers and epilayers. (From Ref. 117. With permission.)
In addition to micropipe defects, the density of non-hollow core (elementary) screw dislocation defects
in SiC wafers and epilayers has been measured on the order of several thousands per square centimeter
of wafer area (Section 6.4). While these defects are not nearly as detrimental to device performance as
micropipes, recent experiments have shown that they degrade the leakage and breakdown characteristics
of pn junctions.109,110 Less direct experimental evidence exists to suggest that elementary screw dislocations
may also cause localized reductions in minority carrier diffusion lengths111,112 and non-uniformities and
catastrophic localized failure to high-voltage Schottky rectifiers under reverse bias.72,113 While localized
breakdown is well known to adversely degrade silicon device reliability in high-power switching appli-
cations, the exact impact of localized breakdown in SiC devices has yet to be quantified. If it turns out
that SiC power devices roughly adhere to the same reliability physics well known for silicon power devices,
it is possible that SiC devices containing non-hollow core screw dislocations could prove unacceptably
unreliable for use in the most demanding high-power conversion applications, such as large-motor
control and public power distribution. Thus, these applications might require much larger (i.e., much
longer-term) improvements in SiC material quality so as to eliminate all screw dislocations (both hollow
core and non-hollow core) from any given device.
SiC High-Voltage Edge Termination
For SiC power devices to successfully function at high voltages, peripheral breakdown due to edge-related
electric field crowding15,16,63 must be avoided through careful device design and proper choice of insu-
lating/passivating dielectric materials. The peak voltage of most prototype high-voltage SiC devices has
been limited by often destructive edge-related breakdown, especially in SiC devices capable of blocking
multiple kilovolts.114,115 In addition, most testing of multi-kilovolt SiC devices has required the device to
be immersed in specialized high-dielectric strength fluids or gas atmospheres to minimize damaging
electrical arcing and surface flashover at device peripheries.114,116,117
6-22 VLSI Technology
A variety of edge termination methodologies, many of which were originally pioneered in silicon high-
voltage devices, have been applied to prototype SiC power devices with varying degrees of success. Some
of these approaches include tailored dopant guard rings,122–124 tailored etches,118–121 neutral ion implant
damage rings,125,126 metal guard rings,127 and anode contact-insulator overlap.128,129 The higher voltages
and higher local electric fields of SiC power devices will place larger stresses on packaging and on wafer
insulating materials, so it is unclear that traditional materials used to insulate/passivate silicon high-
voltage devices will prove sufficient for reliable use in SiC high-voltage devices, especially if those devices
are to be operated at high temperatures.
SiC solid-state switches are based on well-known silicon device topologies, like the thyristor, vertical
MOSFETs, IGBT, GTO, etc., that try to maximize power density via vertical current flow using the
substrate as one of the device terminals. Because these switches all contain high-field junctions responsible
for blocking current flow in the OFF-state, their maximum operating currents are primarily restricted
by the material quality deficiencies discussed in Section 6.6. Therefore, while blocking voltages over 2
kV have been demonstrated in low-current devices,116 experimental SiC power switches have only realized
modest current ratings (under 1 A in most devices).
Silicon power MOSFETs and IGBTs are extremely popular in power circuits, largely because their MOS
gate drives are well insulated and require little drive signal power, and the devices are “normally off ” in
that there is no current flow when the gate is unbiased at 0 V. However, as discussed in Section 6.5, the
performance and reliability of SiC power device structures with inversion channel MOS field-effect gates
(i.e., MOSFETs, IGBTs, etc.) are limited by poor inversion channel mobilities and questionable oxide
reliability at high temperatures. Thus, SiC device structures that do not rely on high-quality gate oxides,
such as the thyristor, appear more favorable for more immediate realization, despite some non-trivial
drawbacks in operational circuit design and switching speed.
Recently, some non-traditional power switch topologies have been proposed to somewhat alleviate
SiC oxide and material quality deficiencies while maintaining normally off insulated gate operation.
Shenoy et al.136 and Hara,137 respectively, have implemented lateral and vertical doped-channel deple-
tion/accumulation mode power SiC MOSFETs that can be completely depleted by built-in potentials at
zero gate bias so that they are “normally off.” Spitz et al.116 recently demonstrated high-voltage SiC lateral
MOSFETs implemented on semi-insulating substrates. These devices could conceivably reduce the adverse
yield consequences of micropipes, because a c-axis micropipe can no longer short together two conducting
sides of a high-field junction in most regions of the device. With the assistance of lateral surface electric
field tailoring techniques, Baliga138 has suggested that lateral-conduction SiC power devices could deliver
better power densities than traditional vertical SiC power device structures. Baliga has also proposed the
advantageous high-voltage switching by pairing a high-voltage SiC MESFET or JFET with a lower-voltage
silicon power MOSFET.138
FIGURE 6.10 Micromachined SiC-based lateral resonator device. The excellent mechanical and electrical prop-
erties of SiC are enabling the development of harsh-environment microelectromechanical systems (MEMS) for
operation beyond the limits of conventional silicon-based MEMS. (From Prof. M. Mehregany, Case Western
Reserve University. With permission.)
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Temperature Silicon Carbide Planar IC Technology and First Monolithic SiC Operational Amplifier
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Operating on a 5-V Power Supply, IEEE Transactions on Electron Devices, 45, 45, 1998.
107. Diogu, K. K., Harris, G. L., Mahajan, A., Adesida, I., Moeller, D. F., and Bertram, R. A., Fabrication
and Characterization of a 83 MHz High Temperature β-SiC MESFET Operational Amplifier with
an AlN Isolation Layer on (100) 6H-SiC, 54th Annual IEEE Device Research Conference, Santa
Barbara, CA, IEEE, Piscataway, NJ, 1996, 160.
108. Neudeck, P. G., 600°C Digital Logic Gates, NASA Lewis 1998 Research & Technology Report, 1999.
109. Neudeck, P. G., Huang, W., and Dudley, M., Breakdown Degradation Associated with Elementary
Screw Dislocations in 4H-SiC P+N Junction Rectifiers, Power Semiconductor Materials and
Devices, Materials Research Society Symposia Proceedings, 483, Pearton, S. J., Shul, R. J., Wolfgang,
E., Ren, F., and Tenconi, S., Eds., Materials Research Society, Warrendale, PA, 1998, 285.
110. Neudeck, P. G., Huang, W., Dudley, M., and Fazi, C., Non-Micropipe Dislocations in 4H-SiC
Devices: Electrical Properties and Device Technology Implications, Wide-Bandgap Semiconductors
for High Power, High Frequency and High Temperature, Materials Research Society Symposia
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Society, Warrendale, PA, 1998, 107.
111. Doolittle, W. A., Rohatgi, A., Ahrenkiel, R., Levi, D., Augustine, G., and Hopkins, R. H., Under-
standing the Role of Defects in Limiting the Minority Carrier Lifetime in SiC, Power Semiconductor
Materials and Devices, Materials Research Society Symposia Proceedings, 483, Pearton, S. J., Shul,
R. J., Wolfgang, E., Ren, F., and Tenconi, S., Eds., Materials Research Society, Warrendale, PA, 1998,
197.
112. Hubbard, S. M., Effect of Crystal Defects on Minority Carrier Diffusion Length in 6H SiC Measured
Using the Electron Beam Induced Current Method, Master of Science dissertation, Case Western
Reserve University, Cleveland, OH, 1998.
113. Raghunathan, R. and Baliga, B. J., Role of Defects in Producing Negative Temperature Dependence
of Breakdown Voltage in SiC, Applied Physics Letters, 72, 3196, 1998.
114. Neudeck, P. G., Larkin, D. J., Powell, J. A., Matus, L. G., and Salupo, C. S., 2000 V 6H-SiC p-n
Junction Diodes Grown by Chemical Vapor Deposition, Applied Physics Letters, 64, 1386, 1994.
115. Domeij, M., Breitholtz, B., Linnros, J., and Ostling, M., Reverse Recovery and Avalanche Injection
in High Voltage SiC PIN Diodes, Silicon Carbide, III-Nitrides, and Related Materials, Materials
Science Forum, 264-268, Morkoc, H., Pensl, G., Monemar, B., and Janzen, E., Eds., Trans Tech
Publications, Switzerland, 1998, 1041.
116. Spitz, J., Melloch, M. R., Cooper, J. A., Jr., and Capano, M. A., 2.6 kV 4H-SiC Lateral DMOSFET's,
IEEE Electron Device Letters, 19, 100, 1998.
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117. Kimoto, T., Wahab, Q., Ellison, A., Forsberg, U., Tuominen, M., Yakimova, R., Henry, A., and
Janzen, E., High-Voltage (>2.5kV) 4H-SiC Schottky Rectifiers Processed on Hot-Wall CVD and
High-Temperature CVD Layers, Silicon Carbide, III-Nitrides, and Related Materials, Materials
Science Forum, 264-268, Pensl, G., Morkoc, H., Monemar, B., and Janzen, E., Eds., Trans Tech
Publications, Switzerland, 1998, 921.
118. Peters, D., Schorner, R., Holzlein, K. H., and Friedrichs, P., Planar Aluminum-Implanted 1400 V
4H Silicon Carbide p-n Diodes with Low On Resistance, Applied Physics Letters, 71, 2996, 1997.
119. Ueno, K., Urushidani, T., Hashimoto, K., and Seki, Y., The Guard-Ring Termination for the High
Voltage SiC Schottky Barrier Diodes, IEEE Electron Device Letters, 16, 331, 1995.
120. Itoh, A., Kimoto, T., and Matsunami, H., Excellent Reverse Blocking Characteristics of High-Voltage
4H-SiC Schottky Rectifiers with Boron-Implanted Edge Termination, IEEE Electron Device Letters,
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121. Singh, R. and Palmour, J. W., Planar Terminations in 4H-SiC Schottky Diodes with Low Leakage
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122. Ramungul, N., Khemka, V., Chow, T. P., Ghezzo, M., and Kretchmer, J., Carrier Lifetime Extraction
from a 6H-SiC High-Voltage P-i-N Rectifier Reverse Recovery Waveform, Silicon Carbide, III-
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Monemar, B., and Janzen, E., Eds., Trans Tech Publications, Switzerland, 1998, 1065.
123. Konstantinov, A. O., Wahab, Q., Nordell, N., and Lindefelt, U., Ionization Rates and Critical Fields
in 4H Silicon Carbide, Applied Physics Letters, 71, 90, 1997.
124. Harris, C. I., Konstantinov, A. O., Hallin, C., and Janzen, E., SiC Power Device Passivation Using
Porous SiC, Applied Physics Letters, 66, 1501, 1995.
125. Alok, D., Baliga, B. J., and McLarty, P. K., A Simple Edge Termination for Silicon Carbide Devices
with Nearly Ideal Breakdown Voltage, IEEE Electron Device Letters, 15, 394, 1994.
126. Alok, D. and Baliga, B., SiC Device Edge Termination Using Finite Area Argon Implantation, IEEE
Transactions on Electron Devices, 44, 1013, 1997.
127. Raghunathan, R. and Baligà, B. J., EBIC Measurements of Diffusion Lengths in Silicon Carbide,
1996 Electronic Materials Conference, Santa Barbara, CA, TMS, Warrendale, PA, 1996, 18.
128. Su, J. N. and Steckl, A. J., Fabrication of High Voltage SiC Schottky Barrier Diodes by Ni Metalli-
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7
Passive Components
Integration Issues
It is well known and recognized that magnetic components should be avoided when designing integrated
circuits due to their lack of integrability. New developments in the field of magnetic component fabri-
cation are promising devices that can be integrated and miniaturized using monolithic fabrication
techniques as opposed to today's bulk methods. The driving forces for such developments rest in certain
applications that benefit or rely on inductive or magnetically coupled devices using ferromagnetic media.
Examples of such applications include tuned RF tanks, matching networks, dc-dc power conversion and
regulation, network filters, and line isolators/couplers.
Emerging applications requiring more mobility, lower power dissipation, and smaller component and
system sizes have been drivers for the development of highly integrated systems and/or subsystems. In
order to match these trends, it has become necessary to be able to integrate high-quality magnetic devices
(i.e., inductors and transformers) with the systems they operate in as opposed to being stand-alone
discrete devices. Not only does their discrete nature prevent further miniaturization, but their very nature
also hampers improved performance (e.g., speed).
The main features of a monolithic magnetic device include:
1. High values of inductance compared to air core spirals
2. Enhanced high-frequency performance
3. Energy storage, dc bias, and power handling capabilities
4. Use of ferromagnetic materials as a magnetic core
5. Photolithographic fabrication of windings and magnetic core
6. Multi-layer mask fabrication for complete magnetic device design
7. Standard or semi-standard IC processing techniques
Due to the use of standard photolithography, etching, and patterning methods for their fabrication,
monolithic magnetic devices may appear compatible with IC processes. However, two main characteristics
make these devices more suitably fabricated off-line from a mainstream IC process:
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 7-1
7-2 VLSI Technology
• Coarser design rules. Usually, magnetic device designs do not require sub-micron geometries as
demanded by semiconductor designs. This discrepancy means that an expensive sub-micron
process for these components would unnecessarily raise the device cost.
• Use of ferromagnetic core materials. The use of iron, cobalt, nickel, and their alloys is at the heart
of a high-quality magnetic device. Some of these materials are alien and contaminating to semi-
conductor cleanrooms. As a result, processing sequences and logistics for full integration with
semiconductors is still in the development phase.
With these two major differences, integration of magnetics and semiconductors may require the use of
multi-chip modules or single package multi-die cases. Full integration into a single monolithic die
requires separate processing procedures using the same substrate.
The construction of a monolithic micromagnetic device fabricated on a substrate such as silicon or
glass is shown in Fig. 7.1. In this diagram, the magnetic layer is sandwiched between upper and lower
conductor layers that are connected together by means of an electrically conducting via. This structure
is referred to as a toroidal device from its discrete counterpart.
Conversely, a dual structure can be made where two magnetic layers sandwich the conductor layer (or
layers). This dual structure can be referred to as an EE device since it is derived from the standard discrete
“EE” core type. In either case, as required by the operation of any magnetically coupled device, the
magnetic flux path in the magnetic film and the current flow in the coil conductor are orthogonal, in
accordance with Ampere's circuital law. Interlayer insulation between conductors and the magnetic
layer(s) is necessary, both to reduce capacitive effects and to provide a degree of electrical voltage
breakdown. These parameters are affected by the choice of insulator systems used in microfabricated
circuits, due to the differing values of dielectric constants and breakdown voltages used. Some commonly
used insulator systems include silicon dioxide and polyimide, each of which has distinctly different
processing methods and physical characteristics. Conductor layers for the coil windings can be fabricated
using standard aluminum metallization. In some cases, copper conductors are a better choice due to
their higher conductivity and hence lower resistive losses. This is especially important if the device is to
handle any significant power. The magnetic film layer is a thin film of chosen magnetic material typically
between 1 and 10 µm in thickness. Such materials can be routinely deposited by standard techniques
such as sputtering or electrodeposition. The specific method chosen must yield magnetic films with the
desired properties, namely permeability, parallel loss resistance, and maximum flux density. These param-
eters vary with the deposition conditions and techniques, such that significant development and opti-
mization has occurred to produce the desired results.
Since the design may call for energy storage and hence gaps in the core, the fabrication method can
be modified to incorporate these features. Figure 7.2 shows the geometry of a planar magnetic core with
a gap produced by photolithography. In this case, the gap is formed as a result of the artwork generated
for the core design. Figure 7.3 shows the design of a gap using multi-layer magnetic films. The energy
storage region exists in the edge insulation region between the two magnetic layers.
The fabrication and construction of conductors for the coil usually involve depositing standard inter-
connect metals (e.g., aluminum) by sputter deposition. The thicknesses are chosen based on the current-
Passive Components 7-3
FIGURE 7.2 Planar, single-layer magnetic core configuration for energy storage (top view).
FIGURE 7.3 Multiple magnetic layers for energy storage micromagnetics (cross-sectional view).
carrying capability and the frequency of operation, as well as the desired configuration (inductor or
transformer). The dc resistance of the conductors must be minimized to reduce dc losses, but the
conductor thickness and arrangement must also result in minimal ac losses. This can be accomplished
by reduced resistivity (i.e., copper vs. aluminum) and by multiple conductor layers to reduce skin and
proximity effects at high frequencies.
1 2 1
E = --- LI = ---
2 2 ∫ ∫ ∫ B ⋅ H dv (7.1)
where L is the transformer or inductor's inductance in Henries, and I (A) is the maximum current carried
by the corresponding winding. This is related to the magnetic flux density, B, and magnetic field, H,
present in the volume of the device. So, for a small physical volume, one can see from Eq. (7.1) that the
energy stored is also small. This limited energy storage capability limits these devices to operation in
low-power circuits. In order to obtain a high B-H product for more energy storage, a combination of
high-permeability and low-permeability regions should be fabricated (i.e., a gap in the high permeability
path is introduced). This gap region helps to maintain a high flux density as well as an appreciable field.
The highly permeable region, on the other hand, while being able to maintain high flux density does not
support large magnetic fields due to the fundamental relationship between magnetic field and flux:
B = µ0 µr H (7.2)
7-4 VLSI Technology
In Eq. (7.2), µ0 is the permeability of vacuum (4π × 10–7 H/m) and µr is the relative permeability of
the medium in which the magnetic field produces the corresponding magnetic flux density. The size of
this gap determines both the energy storage levels and the inductance attainable (which is lower than
the inductance attainable without a gap). In micromagnetic fabrication, two approaches may be taken
to create this “air gap” region. One is to introduce a planar lithographical feature into the core structure
(Fig. 7.2), and the other is to rely on multiple magnetic core layers separated by insulating layers (Fig.
7.3). The drawback of the lithographical gap is the limits imposed by the design rules. In this case, the
gap may not be any smaller than the minimum design rule, which can be quite coarse. Excessive gap
sizes result in very low inductance, requiring an increase in number of turns to compensate for this
drop. Consequently, electrical losses in these windings increase and also the fabrication becomes more
complicated. The drawback of multiple magnetic core layers is the need to add another level of processing
to obtain at least a second (or more) magnetic layer(s). The stack-up of these layers and the edge
terminations determine the amount of energy storage possible in the device. Unlike the lithographically
produced gap, the energy storage in this case is much more difficult to estimate due to the two-
dimensional nature of the edge termination fields in the gap region surrounding the multi-layer mag-
netic cores. In uniform field cases, the energy stored in volume of the gap can be obtained from Eqs.
(7.1) and (7.2) due to the continuity and uniformity of the flux density vector in both the core and gap
regions, giving:
2
1 2 1 B V gap
E = --- LI ≈ --- --------------
- (7.3)
2 2 µ0
where Vgap is the volume of the gap region in cubic meters (m3). The approximation is valid as long as
the gap region carries a uniform flux density and is “magnetically long” compared to the length of the
highly permeable core region (i.e., gap length/µr gap >> core length/µr mag). Usually, this condition can be
satisfied with most ferromagnetic materials of choice, but some ferromagnetic materials may have low
enough permeabilities to render this approximation invalid. In this event, some energy is stored within
the ferromagnetic material and Eq. (7.3) should be modified. Eq. (7.3) is very useful in determining the
size of gap needed to support the desired inductance and current levels for the device. For example, if a
250-nH inductor operating at 250 mA of current bias were needed, the gap volume necessary to support
these specifications would be about 2 × 10–5 mm3, assuming a material with a maximum flux density of
1.0 T. In the planar device of Fig. 7.2 with nominal magnetic film dimensions of 2 µm in the normal
direction and 200 µm in the planar direction, the required gap width would be about 5 µm. Since the
gap in this case is obtained by photolithography, the minimum feature size for this process would need
to be 5 µm. If a different material of lower maximum flux density capability of 0.5 T were used instead,
the rated current level of 250 mA would have to be downgraded to 62 mA to prevent saturation of the
magnetic material. Conversely, the gap length of 5 µm could be increased to 20 µm while maintaining
the same current level, assuming adjustments are made to the turns to maintain the desired inductance.
Such tradeoffs are common, but are more involved due to the interaction of gap size with inductance
level and number of turns.
Another aspect of the design is the conductor for coil windings for an inductor or for primary and
secondary windings in the case of a transformer. The number of turns is usually selected based on the
desired inductance and turns ratio (for a transformer), which are typically circuit design parameters. As
is well known, the number of turns around a magnetic core gives rise to an inductance, L, given by:
2
µ0 µr N A
L = --------------------
-H (7.4)
l
In this relation, N is the number of turns around a magnetic core of cross-sectional area A (m2) and
magnetic path length l (m). The inductance is reduced by the presence of a gap since this will serve to
Passive Components 7-5
increase the path length. The choice of conductor thickness is always made in light of the ac losses
occurring when conductors carry high-frequency currents. The conductors will experience various cur-
rent redistribution effects due to the presence of eddy currents induced by the high-frequency magnetic
fields surrounding the conductors. The well-known skin effect is one of such effects. Current will crowd
toward the surface of the conductor and flow mainly in a thickness related to the skin depth, δ,
1
δ = ------------------- m (7.5)
πfµ 0 σ
For a copper conductor, δ = 66/ f ( MHz ) µm. At 10 MHz, the skin depth in copper is 20 µm, placing
an upper limit on conductor thickness. When the interconnect metallization is aluminum,
δ = 81/ f ( MHz ) µm, so the upper limit at 10 MHz becomes 25 µm of metal thickness. Usually, the
proximity of conductors to one another forces further optimization due to the introduction of losses due
to eddy currents induced by neighboring conductors. In this case, the conductor thickness should be
further adjusted with respect to the skin depth to reduce the induced eddy currents. The increase in
conductor resistance due to the combined skin and proximity effects in a simple primary-secondary
winding metallization scheme (shown in Fig. 7.4) can be calculated as an increase over the dc resistance
of the conductor from:
In this relationship, h is the thickness of the metallization being used and Rac is obtained once the dc
resistance (Rdc, also a function of h) is known. A distinct minimum for Rac can be obtained and yields
the lowest possible ac resistance when:
h π
--- = --- (7.7)
δ 2
π π
Rac = --- Rdc tanh --- = 1.44Rdc (7.8)
2 2
When the geometry differs from the simple primary-to-secondary interface of Fig. 7.4 to more turns,
layers, shapes, etc., a more complicated analysis is necessary.4 The simple relation of Eq. (7.7) is nolonger
valid. Nevertheless, this relation provides a very good starting point for many designs. A qualitative
FIGURE 7.4 Configuration of primary and secondary transformer metallization for ac resistance calculation.
7-6 VLSI Technology
FIGURE 7.5 The variation of high-frequency metallization resistance with metal thickness for the configura-
tion in Fig. 7.4. A distinct minimum is observed due to skin and proximity effects.
explanation of this behavior stems from the fact that a thicker metallization will produce less dc resistance,
but provides poor ac utilization due to current crowding near the surface. On the other hand, a thinner
metallization increases the dc resistance, while providing better ac conductor utilization. The optimum
situation is somewhere in between these two extreme cases, as can be seen from Fig. 7.5.
The principles presented in this section regarding design issues are at the core of every magnetic
component design for integrated circuits. However, many design details — especially at elevated frequen-
cies — are beyond the scope of this text. It is important to note that many of the limitations on high-
frequency designs (100 MHz and higher) are imposed by the properties of the magnetic materials used
in the cores of these devices.
To overcome the problem of low resistivity, the magnetic layers must be deposited in thin films with
limited thickness. Since eddy currents flow in the metallic films at high frequencies, their effect can be
greatly reduced by making the film thickness less than a skin depth. The skin depth in the magnetic film,
δm, is given by:
1
δ m = ------------------------ m (7.9)
πfµ o µ r σ
In a thin film of permalloy (µr = 2000), the skin depth at 10 MHz is 3 µm. In order to limit eddy current
losses in the film, its thickness must be chosen to be less than 3 µm. This limitation will conflict with
the inductance requirement, since a larger inductance requires a thicker magnetic film (see Eq. 7.4). Such
difficulties can be overcome by depositing the magnetic film in multiple layers insulated from one another
to restrict eddy current circulation. Such a structure would still provide the overall thickness needed to
achieve the specified inductance while limiting the eddy current loss factor. The use of multi-layers also
allows the reduction of die size due to the build-up of magnetic core cross-section (A in Eq. 7.4) in
vertical layers, rather than by increasing the planar dimensions. As a result, it can be seen that a tradeoff
exists between number of layers and die size to yield the most economical die cost.
In addition to eddy current losses due to the low magnetic metal resistivity, hysteresis losses occur in any
magnetic material due to the traversing of the non-linear B-H loop at the frequency of operation. This is
due to the loss of energy needed to rotate magnetic domains within the material. This loss is given by
°∫
P hys = f ⋅ H ⋅ dB (7.10)
which is the area enclosed by the particular B-H loop demanded by the circuit operation and f is the
frequency of operation. Total loss is expressed in many forms, depending on the application. In many cases,
it is given in the form of a “parallel” or “shunt resistance” (Fig. 7.6) and it therefore presents a reduction
in impedance to the source as well as a reduction in the overall quality factor of the inductor or transformer.
It also represents a finite power loss since this loss is simply V2/Rp watts, where V is the applied voltage.
Notice that Rp is a non-linear resistance with both frequency and flux level dependencies. It can be
specified at a given frequency and flux level and is usually experimentally measured. It can also be
extracted from core loss data usually available in the form
2
α β V
P = kf B = ----- (7.11)
Rp
In this relation, k, α, and β are constants for the material at hand. This model is useful for circuit
simulation purposes, thereby avoiding the non-linear properties of the magnetic material. Care, however,
should be exercised in using such models since with a large enough excitation, the value of the shunt
resistor changes.
FIGURE 7.6 Magnetic material losses are represented by a parallel shunt resistance.
7-8 VLSI Technology
⎧ 8r avg 8r avg
1 ( r out – r in )⎞ 2 ⎛ ----------------------- ⎫
+ ------ ⎛ ----------------------- + 3.583⎞ – 0.5 ⎬ (7.12)
–7 2
L = 4π × 10 N r avg ⎨ ln ----------------------- ln
⎝ ⎠ ⎝ ( ) ⎠
⎩ ( r out – r in ) 24 r avg r out – r in ⎭
In this formula, rout and rin are the outer and inner radii of the spiral, respectively, and the average
radius ravg is
( r out + r in )
r avg = -----------------------
- (7.13)
2
The formula is an approximation that loses accuracy as the device size becomes large (i.e., large rout with
respect to rin).
The loss factors of such devices are strongly influenced by the non-idealities of the substrates and
insulators on which they are deposited. For example, aluminum spiral inductors fabricated on silicon
with highly doped substrates and epitaxial layers can have significant reductions in quality factor
due to the conductivity of the underlying layers. These layers act as ground planes, producing the
effect of an image of the spiral underneath. This in turn causes a loss in inductance. This can be as
much as 30 to 60% when compared to a spiral over a perfect insulator. In addition, an increase in
the loss factor occurs due to circulating eddy currents in the conductive under-layers. Increases in
the effective resistance of 5 to 10 times the perfect insulator case are possible, increasing with
increased frequency. All these effects can be seen to degrade the performance of these inductors,
thus requiring design optimization.10–12
These substrate effects appear in the form of coupling capacitances from the spiral metal to the
substrates, as well as spreading resistances in the substrate itself. The spreading resistance is frequency
dependent, increasing with higher frequency. The amount of coupling to the substrate depends on the
coupling capacitances and hence the separation of the spiral from the substrate. This distance is the
dielectric thickness used in the IC process. Only with very large dielectric thicknesses are the substrate
effects negligible. In practical cases where it is relatively thin and limited to a few microns, the effects are
very large, giving an overall quality factor, Q, which is significantly lower than the Q of the spiral without
the substrate. Fig. 7.7 shows a typical degradation curve of Q on a resistive substrate for “thick” and
“thin” separations or dielectric thicknesses. The trends of this curve are also similar if the dielectric
thickness variable is replaced by the substrate resistivity as a variable. The exact amount of degradation
depends on the separation involved, the dielectric constant, and the resistivity of the substrate. With
these quantities known, it is possible to construct a circuit model to include these effects and hence solve
for the overall quality factor, including the substrate effects.
Passive Components 7-9
In order to improve the inductor quality factor on a resistive substrate, some design solutions are
possible. One solution to this problem is to increase the substrate resistivity. Another is to design a
spiral with a small footprint to reduce coupling to the substrate. In order to offset the increased
resistance (which also reduces Q), thicker metallization would be necessary and clearly a tradeoff
situation arises requiring some design optimization by circuit modeling or, more accurately, by elec-
tromagnetic finite-element analysis.
7.3 Resistors
Resistors have been available for use in integrated circuits for many years.13–16 Some of these are made
in silicon and thus are directly integrated with the rest of the IC process. Others, similar to the magnetic
device case, are thin-film resistors fabricated in an off-line process that is not necessarily compatible with
silicon IC processing. Integrated silicon resistors offer simplicity in fabrication but have less than ideal
characteristics with loose tolerances. For this reason, many circuits rely on the ratio of resistor values
rather than on their absolute values. Thin-film resistors, on the other hand, are far superior, offering
tight tolerances and the ability to trim their absolute value down to very precise values. They also display
more stability in terms of temperature and frequency dependence.17
Usually, resistors in integrated circuits are characterized in terms of their sheet resistance rather than
their absolute resistance value. Sheet resistance, Rsheet, is defined as the resistance of a resistive strip with
equal length and width so that
ρ
R sheet = - ( Ω ⁄ M ) (7.14)
t
where ρ is the material resistivity (Ω⋅m) and t is its thickness (m). Once Rsheet is given, the resulting
resistor value is obtained by multiplying by its length-to-width aspect ratio. In order to avoid very high
aspect ratios, an appropriate sheet resistivity should be used. For example, with Rsheet = 10 Ω/M a 10:1
length-to-width ratio would give a 100-Ω resistor. However, to obtain a 1-kΩ resistor, it would be better
to use a different material with, for example, Rsheet = 100 Ω/M with the same 10:1 ratio instead of using
a 100:1 ratio with the low-resistivity material.
7-10 VLSI Technology
Diffused Resistors
This can be formed during either the base or emitter diffusion of a bipolar process. For an npn process,
the base diffusion resistor is a p-type of moderate sheet resistivity, typically in the range of 100 to 200
Ω /. This can provide resistors in the 50 to 10 kΩ range. The heavily doped n+ emitter diffusion will
produce an n+-type resistor with low sheet resistivity of 2 to 10 Ω/. This can provide resistors with low
values in the 1 to 100 Ω range. Due to tolerances in the photolithographic and etching processes, the
tolerance in the absolute resistance can be as high as range. Due to tolerances on the photolithographic
and etching processes, the tolerance on the absolute resistance can be as high as ±30%. However, resistor
pairs can be matched closely in temperature coefficients and doping profiles, especially when placed side-
by-side on the chip, so that the resultant tolerance of the resistor ratio can be made to be less than ±1%.
Since a diffusion resistor is based on a p-type base over an n-type epitaxy, or an n+-type emitter over a
p-type base, it is essential that the formed p-n junctions are always reverse-biased to ensure that current
flows in the intended portion of the resistor. The presence of such a reverse-biased p-n junction also
introduces a distributed capacitance from the resistor body to the substrate. This will cause high-
frequency degradation, whereby the resistor value drops from its nominal design value to a lower
impedance value due to the shunting capacitance.
Pinched Resistors
A variation to the diffused resistor that is used to increase the sheet resistivity of base region is to use
the n+-type emitter as a means to reduce the cross-sectional area of the base region, thereby increasing
the sheet resistivity. This can increase the sheet resistance to about 1 kΩ/. In this case, one end of
the n+-type emitter must be tied to one end of the resistor to contain all current flow to the pinched
base region.
Epitaxial Resistors
High resistor values can be formed using the epitaxial layer since it has higher resistivity than other
regions. Epitaxial resistors can have sheet resistances around 5 kΩ /. However, epitaxial resistors have
even looser tolerances due to the wide tolerances on both epitaxial resistivity and epitaxial layer thickness.
MOS Resistors
A MOSFET can be biased to provide a non-linear resistor. Such a resistor provides much greater values
than diffused ones while occupying a much smaller area. When the gate is shorted to the drain in a
MOSFET, a quadratic relation between current and voltage exists and the device conducts current only
when the voltage exceeds the threshold voltage. Under these circumstances, the current flowing in this
resistor (i.e., the MOSFET drain current) depends on the ratio of channel width-to-length. Hence, to
increase the resistor value, the aspect ratio of the MOSFET should be reduced to give longer channel
length and narrower channel width.
Thin-Film Resistors
As mentioned before in the magnetic core case, a resistive thin-film layer can be deposited (e.g., by
sputtering) on the substrate to provide a resistor with very tight absolute-value tolerance. In addition,
given a large variety of resistor materials, a wide range of resistor values can be obtained in small
footprints, thereby providing very small parasitic capacitances and small temperature coefficients. Some
common thin-film resistor materials include tantalum, tantalum nitride, and nickel-chromium. Unlike
Passive Components 7-11
semiconductor resistors, thin-film resistors can be laser trimmed to adjust their values to very high
accuracies of up to 0.01%. Laser trimming can only increase the resistor value since the fine beam
evaporates a portion of the thin-film material. By its nature, laser trimming is a slow and costly operation
that is only justified when very high accuracy on absolute values is necessary.
7.4 Capacitors
As in the inductor case, the limitation on integrated capacitors is die size, due to the limited
capacitance/unit area available on a die. These limitations are imposed by the dielectrics used with
their dielectric constants and breakdown voltages. Most integrated capacitors are either junction
capacitors or MOS capacitors.
Junction Capacitors
A junction capacitor is formed when a p-n junction is reversed-biased. This can be formed using the
base–emitter, base–collector, or collector–substrate junctions of an npn structure in bipolar ICs. Of
course, the particular junction must be maintained in reverse-bias to provide the desired capacitance.
Since the capacitance arises from the parallel plate effect across the depletion region, whose thickness in
turn is voltage dependent, the capacitance is also voltage dependent, decreasing with increased reverse-
bias. The capacitance depends on the reverse-voltage in the following form:
C0
C ( V ) = -----------------------------
-n (7.15)
( 1 + V ⁄ ψ0 )
The built-in potential, Ψ0, depends on the impurity concentrations of the junction being used. For
example, Ψ0 = 0.7 V for a typical bipolar base–emitter junction. The exponent n depends on the doping
profile of the junction. The approximations n = 1/2 for a step junction and n = 1/3 for a linearly graded
junction are commonly used. The resultant capacitance depends on C0, the capacitance per unit area
with zero bias applied. This depends on the doping level and profile. The base–emitter junction provides
the highest capacitance per unit area, around 1000 pF/mm2 with a low breakdown voltage (~5 V). The
base–collector junction provides about 100 pF/mm2 with a higher breakdown voltage (~40 V).
MOS Capacitors
MOS capacitors are usually formed as parallel plate devices with a top metallization and a high conduc-
tivity n+ emitter diffusion as the two plates, with a thin oxide dielectric sandwiched in between. The
oxide is usually a thin layer of SiO2 with a relative dielectric constant εr of 3 to 4, or Si3N4 with εr of 5
to 8. Since the capacitance obtained is ε0εrA/toxide, the oxide thickness, toxide , is critical. The lower limit
on the oxide thickness depends on the process yields and tolerances, as well as the desired breakdown
voltage and reliability. MOS capacitors can provide around 1000 pF/mm2, with breakdown voltages up
to 100 V. Unlike junction capacitors, MOS capacitors are voltage independent and can be biased either
positively or negatively. Their breakdown, however, is destructive since the oxide fails permanently. Care
should be taken to prevent overvoltage conditions.
References
1. Saleh, N. and Qureshi, A., “Permalloy thin-film inductors,” Electronics Letters, vol. 6, no. 26, pp.
850-852, 1970.
2. Soohoo, R., “Magnetic film inductors for integrated circuit applications,” IEEE Trans. Magn., vol.
MAG-15, pp. 1803, 1979.
7-12 VLSI Technology
3. Mino, M. et al., “A new planar microtransformer for use in micro-switching converters,” IEEE
Trans. Magn., vol. 28, pp. 1969, 1992.
4. Vandelac, J. and Ziogas, P., “A novel approach for minimizing high frequency transformer copper
loss,” IEEE Trans. Power Elec., vol. 3, no. 3, pp. 266-76, 1988.
5. Sato, T., Tomita, H., Sawabe, A., Inoue, T., Mizoguchi, T., and Sahashi, M., “A magnetic thin film
inductor and its application to a MHz Switching dc-dc converter,” IEEE Trans. Magn., vol. 30, no.
2, pp. 217-223, 1994.
6. Grover, F., Inductance Calculations, Dover Publishing, New York, 1946.
7. Welsby, V., Theory and Design of Inductance Coils, MacDonald & Co., London, 2nd ed., 1960.
8. Walker, C., Capacitance, Inductance, and Crosstalk Analysis, Artech House, Boston, 1990.
9. Gupta, K. C., Garg, R., and Chadha, R., Computer-Aided Design of Microwave Circuits, Artech
House, Dedham, MA, 1981.
10. Remke, R. and Burdick, G.,“Spiral inductors for hybrid and microwave applications,” Proc. 24th
Electron Components Conf., May 1974, pp. 152-161.
11. Arnold, R. and Pedder, J.,“Microwave characterization of microstrip lines and spiral inductors in
MCM-D technology,” IEEE Trans. Comp., Hybrids, and Manuf. Tech., vol. 15, pp. 1038-45, 1992.
12. Nguyen, N. M. and Meyer, R. G.,“Si IC-compatible inductors and LC passive filters,” IEEE J. Solid-
State Circuits, vol. 25, pp. 1028-1031, Aug. 1990.
13. Glaser, A. and Subak-Sharpe, G., Integrated Circuit Engineering, Addison-Wesley, Reading, MA,
1977.
14. Goodge, M. E., Semiconductor Device Technology, Howard Sams & Co., Inc., Indiana, 1983.
15. Grebene, A. B., Bipolar and MOS Analog Integrated Circuit Design, John Wiley, New York, 1984.
16. Gray, P. R. and Meyer, R. G., Analysis and Design of Analog Integrated Circuits, John Wiley, New
York, 1993.
17. Sergent, J. E. and Harper, C. A., Hybrid Microelectronics Handbook, McGraw-Hill, New York, 1995.
18. Levy, R. A., Microelectronic Materials and Processes, Kluwer Academic Publishers, Dordrecht, Neth-
erlands, 1989.
8
Power IC Technologies
8.1 Introduction
VLSI technology has advanced so greatly that Gigabit DRAMs have become a reality, and the technology
faces an optical lithography limit. Microelectronics mostly advances signal processing LSIs such as
memories and microprocessors. Power systems and the related circuits cannot be outside the influence
of VLSI technology.1 It would be quite strange for power systems alone to still continue to consume a
large space while brains become smaller and smaller. On the other hand, almost all of the systems require
actuators or power devices to control motors, displays, and multimedia equipment. The advances in
microelectronics have made it possible to integrate large-scale circuits in a small silicon chip, ending up
in high system performance and resultant system miniaturization. The system miniaturization inevitably
necessitated power IC development. Typical early power ICs were audio power amplifiers, which used
bipolar transistors as output devices. The pn junction isolation method was well suited to integrate
bipolar transistors with control circuits.
Real advancements in intelligent power ICs were triggered by the invention of power DMOSFETs2 in
the 1970s. DMOS transistors have ideal features for output devices of power ICs. No driving dc current
is necessary, and large currents can be controlled simply by changing the gate voltage. In addition, DMOS
switching speed is sufficiently fast.
The on-resistance of vertical DMOSFETs has been greatly reduced year by year with advances in fine
lithography in LSI technology. In the mid-1980s, the new concept “Smart Power”3 was introduced. Smart
Power integrates bipolar and CMOS devices with vertical DMOS, using a process primarily optimized
for poly-silicon gate self-aligned DMOS. The main objective is to integrate control and protection circuits
with vertical power devices, not only to increase device reliability and performance, but also to realize
easy use of power devices. The concept of Smart Power was applied to high-voltage vertical DMOS with
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 8-1
8-2 VLSI Technology
drain contact on the back side of the chip because discrete DMOS technology was already well advanced
in the early 1980s. The main application field was automotive, replacing mechanical relays and eliminating
wire harnesses.
As the technology of microlithography has further advanced, the on-resistance of DMOS, especially
low-voltage DMOS, has continuously decreased. In the early 1990s, the on-resistance of low-voltage
lateral DMOS became lower than that of bipolar transistors.4 It was even realized that low-voltage lateral
DMOS is superior to vertical planar discrete DMOS since fine lithography does not contribute to a
decrease in on-resistance of vertical DMOS because of JFET resistance. Recently, with the introduction
of a 0.6-µm design rule, lateral DMOS has become predominant over the wide voltage range — from
20 V up to 150 V. Mixed technology, called BCD,4 integrating BiCMOS and DMOS, is now widely accepted
for low-voltage power ICs.
For high-voltage power ICs, DMOS is not suitable for output devices because of a high on-resistance.
Thyristor-like devices, such as GTOs, have conventionally been used for high-voltage applications. Integra-
tion of thyristor-like devices needs a method of dielectric device isolation (DI). The conventional DI method,
called EPIC,5 has been used for high-voltage telecommunication ICs, called SLIC. However, it has problems
of high cost and large wafer warpage. In 1985 and 1986, wafer direct-bonding technology was invented,6,7
and low-cost DI wafers became available. Wafer warpage of directly bonded SOI wafers is very small. This
made it possible not only to fabricate large-diameter (8-in.) SOI wafers, but also to apply advanced lithog-
raphy to DI power ICs. The chip size of DI power ICs can be reduced by narrow-trench isolation and by
the use of high-performance lateral IGBTs. The low-cost DI wafers and the chip size reduction have widened
the application fields of DI power ICs, covering automotive, motor control, and PDP drivers.
pn Junction Isolation
One of the fundamental issues in integrated circuits is how to electrically isolate each device from the
others. pn junction isolation is the most familiar method and has been used since the beginning of bipolar
IC history. Figure 8.5 shows the cross-section of a typical junction isolation structure. First, an n-type
epitaxial layer is formed on p-type silicon substrate. p-type diffusion layers are then formed to reach the
p-type substrate, resulting in isolated n-type islands surrounded by p-type regions. By keeping the
substrate potential in the lowest level, the pn junctions, surrounding the islands, are reverse-biased and
the depletion layers are formed to electrically isolate each island from the others.
If this method is applied to high-voltage power ICs, a thick n-type epitaxial layer is required and deep
isolation diffusions are necessary. Deep diffusion accompanies large lateral diffusion, ending up in a large
8-4 VLSI Technology
isolation area. One solution for this is to use buried p+ diffusion layers for upward isolation diffusions,
as shown in Fig. 8.6. However, 200 V is a practical limit for conventional pn junction isolation.
A variety of methods have been proposed to overcome this voltage limit. Figure 8.7 shows a typical
example for this.8 A shallow hole is formed where a high-voltage device is formed before the n-type
epitaxial growth. This allows a locally thicker n-type epitaxial layer for high-voltage transistors.
Another distinguished example is shown in Fig. 8.8, where an n+-substrate is used in place of a p-type
substrate. p-type and n-type epitaxial layers are subsequently formed. This example makes it possible to
integrate a vertical DMOSFET with a backside drain contact with junction-isolated BiCMOS control
circuits. This structure was proposed as “Smart Power” in the mid-1980s.
3. Coupling between two devices can be minimized, thus attaining better IC performances: no latch-
up, high speed, large noise immunity, and ruggedness.
4. High-temperature operation is feasible because there are virtually no parasitics and leakage current
is low.
5. Radiation hardness for space use.
Figure 8.9 shows a cross-section of the conventional DI, called EPIC. The crystalline silicon islands
completely surrounded by silicon dioxide film are floating in the supporting substrate made of a thick
polysilicon layer. The fabrication process of EPIC wafers is complicated and illustrated in Fig. 8.10.
The problem with EPIC is the high cost of wafers and large wafer warpage. The development of the
EPIC method was initiated by the early works of J.W. Lathlop et al.,12 and J. Bouchard et al.,13 in 1964.
The EPIC method was first applied to high-speed bipolar ICs owing to its low parasitic capacitance.
Early work on high-voltage integrated circuits was triggered by the need for display drivers and high-
voltage telecommunication circuits. Efforts to achieve high-voltage lateral MOSFETs started in the early
1970s, and the 800-V lateral MOSFET, using RESURF concept and DMOS (DSA2) technology, was
developed for display drivers in 1976, before the RESURF concept was fully established.14
The need for high-voltage SLICs advanced the EPIC technology because it required electrically floating
high-voltage bi-directional switches, which were realized only by the DI technique.
A variety of dielectric isolation methods, classified as silicon on insulator (SOI) technology, were
invented in the 1970s. These are SOS (silicon on sapphire15), SIMOX,16 and recrystallized poly-silicon
such as ZMR.17 And, silicon wafer direct-bonding (SDB)6,7 was proposed in 1985.
FIGURE 8.10 Fabrication process of EPIC wafers. A very thick poly-crystalline silicon layer is deposited on oxidized
single-crystal silicon with a grooved surface. The crystalline silicon is grounded and polished so that the silicon layers
isolate each other by the grooves.
8-6 VLSI Technology
The SOI wafer structure is simple. A single crystalline silicon layer is formed on the buried oxide layer
or insulator substrate. Major methods are SIMOX and wafer bonding. SIMOX is a method that forms a
buried oxide layer by a high dose of oxygen ion implantation and subsequent high-temperature annealing.
Wafer bonding is a method that bonds an oxidized wafer and a substrate wafer at room temperature and
strengthens the bond by annealing at high temperature. The thickness of the bonded SOI layer is adjusted
by mechanical grinding and polishing.
In the late 1980s, MOS gate power device technology was greatly improved. In particular, the success
of the MOS bipolar composite devices such as IGBTs18,19 and MCTs20 made it possible to control a large
current by the MOS gate. The large current-handling capability of IGBTs has accelerated adopting DI
with IGBT outputs.
In the early SLICs, double-injection devices with current control gates such as gated diodes and GTOs
were used for such switches.21 Recently developed SLICs (telecommunication ICs) have adopted lateral
IGBTs or MOS gated thyristors because of the ease of gate drive. All the commercialized SLICs, so far,
have adopted the conventional DI method. The success of SLIC was supported by the fact that monolithic
integration and added function deserved expensive DIs for telecommunications application.
In the 1990s, wafer bonding technology was well established and low-cost SOI wafers were made
available. A low-cost DI method realized by SOI technology, using several micron thick or less silicon
layers, changed the situation of DI research and widened the application fields.
If the silicon layer is thin, devices in the SOI layer are isolated with narrow trenches. This makes SOI
technology very attractive for high-voltage applications because chip size can be reduced and resultant
chip cost is reduced. The SOI technology widened the application field of DI toward consumer use.
High-voltage SOI research work started in the early 1990s. Research efforts have been directed toward:
1. Monolithic device integration of multiple number of high-voltage, high-current devices with
control circuits
2. ICs allowing high temperature operation and ruggedness
3. Low-cost DI power IC process development
4. High-current, high-speed, MOS-controlled lateral output devices with self-protection functions
Field Plate
It is very important to realize a high breakdown voltage in a planar device structure. In other words,
it is ideal if a one-dimensional pn junction breakdown voltage is realized in an actual pn junction, formed
by thermal impurity diffusion. Actual pn junctions consist of cylindrical junctions and spherical junctions
near the surface. Generally, the breakdown voltage of cylindrical or spherical junctions is significantly
lower than that of an ideal 1-D planar junction, if junction curvature is small.
A field plate is a simple and frequently used technique to increase the breakdown voltage of an actual
planar junction. Figure 8.11 shows an example. Field plates, placed on the thick-field oxide, induce
depletion layers underneath themselves. The curvature of the formed depletion layers can be increased
with the induced depletion layers, thereby relaxing the curvature effects of the field plate.
Resurf Technique
The resurf technique was originally proposed in 197914 as a method to obtain a high breakdown voltage
in a conventional JI structure, where the breakdown voltage is limited by the thickness of the epitaxial
layer. Figure 8.12 shows a high-voltage structure, where the depletion layer develops in the p-substrate
and n-epitaxial-layer. If the epi-layer is thick or impurity doping is high (a), breakdown occurs before
Power IC Technologies 8-7
n-epi layer is completely depleted. If an appropriate epi-layer thickness is chosen (b), the epi-layer is
completely depleted when breakdown occurs. The achieved breakdown voltage is very high because the
depletion layer is sufficiently thick, both in lateral direction and vertical direction. The important point
is that the total charge Qc in the epi-layer is chosen so that the value satisfies the equation:
Qc = ε Ec (8.1)
where Ec denotes critical electric field in silicon (3 × 105 V/cm). This charge can be depleted just when
the electric field becomes Ec or breakdown occurs. In other words, the epi-layer is completely depleted
just when breakdown occurs, if the total epi-layer dose is Qc/q, which is approximately 2 × 1012/cm2.
FIGURE 8.13 A method to shield the influence of the metal interconnection layer. (Copyright (1994) IEEE. With
permission.)
devices. These problems are often solved with a thicker insulator layer under the interconnection layers.
However, special means are required if the breakdown voltage is over 400 V.
Figure 8.13 shows one of the methods to shield the influence of metal interconnection layers on the
underlying devices. A spiral-shaped high-resistance poly-silicon layer, connecting source and drain elec-
trodes, effectively shields the influence of the interconnection layer on the depletion layer.22 This is because
the potential of the high-resistance poly-silicon layer is determined by small leakage current.
Another typical example is multiple floating field plates. The cross-section of the structure is similar
to Fig. 8.13. The difference is that the poly-silicon forms multiple closed field rings, which are
electrically floating each other. Multiple floating field plates also prevent breakdown voltage reduction
due to metal interconnection.
FIGURE 8.14 A high-voltage SOI device structure with n+ buried layer on the buried oxide.
FIGURE 8.15 A high-voltage SOI device structure without n+ buried layer on the buried oxide.
layer both share the applied voltage, high breakdown voltage is realized in a relatively thin SOI. This type
of power IC fully enjoys the features of SOI technology.
1. Complete device isolation by trench technique and small isolation region
2. Virtually no parasitic active component
3. A high breakdown voltage exceeding 500 V is realized by applying a large portion of the voltage
across the thick buried oxide
4. Small wafer warpage and fine lithography is applicable
5. High-temperature operation is possible
There are two big issues associated with high-voltage devices on SOI.11 One is how to realize a high
breakdown voltage under the influence of substrate ground potential. The other is how to attain a low
on-resistance with a thin silicon layer. In the conventional DI, the wrap-around n+ region (see Fig. 8.14)
is used in the DI island to prevent the influence of substrate potential on the device breakdown voltage.
However, for thin silicon layers, this method cannot be used. The bottom silicon dioxide layer simply
works as an undoped layer as far as the Poisson equation is concerned. Thus, a SOI layer on a grounded
silicon substrate structure behaves in a way similar to the structure of a doped n-type thin silicon layer
on undoped silicon layer (corresponding to silicon dioxide) on a grounded p silicon substrate. Thus, the
SOI layer works in the same way as a resurf layer.
A high breakdown voltage of a thin silicon layer device can be realized by sharing a large applied
voltage with the buried dioxide film, whose breakdown field is far greater than that of silicon. The buried
oxide film is able to sustain a large share of applied voltage, because the dielectric breakdown field is
larger than that of silicon.
Figure 8.16 shows a typical SOI diode structure and its potential distribution. It is seen that almost a
half of the voltage is applied across the buried oxide. Figure 8.17 shows the electric field distribution
along the symmetry axis of the diode of Fig. 8.16. The electric field in the oxide is larger than that in
silicon because the following relation holds.
The two electric field components Et(Si), Et(I), normal to the interface of the silicon and the bottom
insulator layer, have the relation:
8-10 VLSI Technology
FIGURE 8.17 Electric field distribution along the symmetry axis of diode shown in Fig. 8.16.
Power IC Technologies 8-11
where ε(Si), ε(I) denote dielectric constants for silicon and silicon dioxide, respectively. Using an insulator
film with a lower dielectric constant will increase the device breakdown voltage because the insulator
layer sustains a larger share of the applied voltage.
For optimized SOI diodes, the breakdown voltage is substantially limited to the breakdown voltage of
the 1-D MOS diode portion, as illustrated in Fig. 8.18, consisting of n+/n–/oxide/substrate. Figure 8.19
shows the measured SOI device breakdown voltage as a function of SOI layer thickness with buried oxide
thickness as a parameter. The calculated breakdown voltage of 1-D MOS diodes are shown together. A
500-V breakdown voltage can be obtained with a 13-µm thick SOI with 3-µm thick buried oxide.
FIGURE 8.20 SOI diode with shallow n+ layer diffused from the bottom of the SOI layer.
It is very difficult to achieve a high breakdown voltage exceeding 600 V in simple SOI structures,
because a thicker buried oxide layer of 4 µm or more is required. Maximum breakdown voltage is
substantially limited with the breakdown voltage of the 1-D MOS diode and actually the realized
breakdown voltage is lower than this limit. If the influence of the substrate potential can be shielded, it
is possible to achieve a higher breakdown voltage in the SOI device.
A new high-voltage SOI device structure, free from the above constraints, was proposed in 1991,1 that
realizes a 1200-V breakdown voltage.23
To improve the breakdown voltage, an SOI structure with a shallow n+ layer diffused from the
bottom of SOI layer was proposed.24 Figure 8.20 shows the structure of an SOI diode with a shallow
n+ layer and the electric field strength in the MOS diode portion compared to that without a shallow
n+ layer. In general, if a larger portion of the applied voltage is carried with the bottom oxide layer,
a higher breakdown voltage can be achieved. The problem is how to apply a higher electric field
across the buried oxide without increasing the electric field strength in the SOI layer. This problem
can be solved by placing a certain amount of positive charge on the SOI layer– buried oxide interface.
The positive charge at the interface shields the high electric field in the buried oxide, so that a voltage
across the oxide layer can be increased without applying a higher electric field in the SOI layer. The
shallow n+ layer diffused from the bottom is a practical technique to place the positive charge on the
SOI layer–buried oxide interface, as shown in Fig 8.20. The required dose of the shallow n+ layer is
around 1 × 1012cm–2.
FIGURE 8.21 Calculated ideal profile for a lateral diode on thin SOI.
8-14 VLSI Technology
FIGURE 8.22 Vertical DMOS structure with upside surface drain contact.
FIGURE 8.24 State-of-the-art lateral DMOS and vertical trench MOSFET on-resistance as a function of breakdown
voltage (black circles show lateral DMOS, and open squares show trench MOSFETs).
vertical DMOS output will be replaced by power ICs with a lateral DMOS output, if current capacity is
small — for example, less than 10 A.
High-side switching operation is an important function in automotive applications, especially in case
of H-bridges for motor control. The on-resistance of conventional junction-isolated, high-voltage MOS-
FETs, shown in Fig. 8.23, is significantly influenced by the source to substrate bias,26 because the drift
layer is depleted. However, in the SOI MOSFETs shown in Fig. 8.25, the drift layer is not depleted, but
a hole inversion layer is formed. Thus, the substrate bias influence of SOI LDMOS is small.26
Figure 8.26 shows a 60-V DMOS in a 2-µm thick p-type SOI. The fabrication process is completely
compatible with the CMOS process. The threshold voltage is controlled by channel implant. The exper-
imentally obtained specific on-resistance of the 60-V LDMOS is 100 mΩ ⋅ mm.2 The developed power
MOSFET is completely free from substrate bias influence.27 This is because the hole accumulation layer
is induced on the buried oxide, leaving the n-drift layer unchanged. These results indicate that this device
can be used for high-side switches without on-resistance increase.
FIGURE 8.27 On-resistance versus breakdown voltage for bipolar transistor, DMOS, LIGBT, and VIGBT (dis-
crete IGBTs).
Power IC Technologies 8-17
FIGURE 8.28 Cross-section of large current lateral IGBT.30 (Copyright (1997) IEEE. With permission.)
FIGURE 8.29 Typical current-voltage curves of a multi-channel LIGBT (Vertical scale: 50 mA/Div, Horizontal scale:
0.5 V/Div).
multi-channel LIGBT. The current is an exponential function of the drain bias (collector bias) for the
low-voltage range. The current-voltage curves seem to have a 0.8-V offset voltage, just like a diode. The
typical switching speed of the developed LIGBTs is 300 ns.
It is extremely important to increase the operating current density of LIGBTs in order to reduce chip
size. This is because output devices occupy most of the chip area and the cost of the power ICs depends
significantly on the size of the power devices. The current density of the developed LIGBT is 175 A/cm2
for 3-V forward voltage.
8-18 VLSI Technology
circuit library can be used without changes because the same CMOS fabrication process can be applied
without modification if a relatively thick SOI layer is used.
This section shows the possibility of integration of an MPU, together with BiCMOS analog circuits
and 60-V power LDMOS. 4-bit MPUs, vertical npn, pnp, and 60-V power DMOS were fabricated on 2-
µm SOI wafers by a conventional 0.8-µm BiCMOS process.27 The 60-V DMOS used CMOS p-well without
using self-alignment.
The fabricated 4-bit MPU, consisting of 30,000 FETs for the core, 6000 FETs for the cache, and 120,000
FETs for the ROM, operated at a 20% faster clock speed of 50 MHz at 25°C, as compared to 42 MHz of
the bulk version MPU, and even operated at over 200°C. It was found that the clock speed could be
improved and that a large latch-up immunity at high temperature was realized even if the MOSFETs
were not isolated by trenches. The maximum operating temperature was more than 300°C. It was found
that the yield of the MPU fabricated on SOI was the same as that on bulk wafers, verifying that the crystal
quality of the currently available SOI wafers was sufficiently good. It was also found that both SOI and
bulk MPUs could be operated at 300°C if MPUs consisted of pure CMOS, although the power consump-
tion of the bulk MPU was larger than that of the SOI MPUs.
One of the characteristic features of the SOI power IC structure, shown in Fig. 8.33, is that there are
no buried layers for bipolar transistors. It was found that vertical npn and pnp transistors fabricated on
the n-well and p-well layers exhibited sufficiently good characteristics, and the typical current gains hFE
for the vertical npn and pnp transistors were 80 and 30, respectively.
All these results show that system integration including power LDMOS will be a reality in SOI wafers.
FIGURE 8.34 Leakage current vs. SOI layer thickness. (Copyright (1994) IEEE. With permission.)
FIGURE 8.35 Output voltage of a bandgap reference circuit as a function of operation temperature. (Copyright
(1995) IEEE. With permission.)
8-22 VLSI Technology
References
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1991, 16.
2. Tarui, Y., Hayashi, Y., and Sekigawa, T., “Diffusion self-aligned MOST: a new approach for high
speed device,” Proc. of the 1st Conference on Solid State Devices, Tokyo, 1969, 105.
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power,” IEDM Tech. Digest, 1983, 408.
4. Murari, B., Bertotti, F., and Vignola, G. A., Smart Power ICs, Springer-Verlag, 1995.
5. Beasom, J. D., “A process for simultaneous fabrication of vertical npn and pnp’s and p-ch MOS
devices,” IEDM Tech. Digest, 1973, 41.
6. Shimbo, M., Furukawa, K., Fukuda, K., and Tanzawa, K., “Silicon-to-silicon direct bonding
method,” J. Appl. Phys., vol. 60, p. 2987, 1986.
7. Ohashi, H., Ohura, J., Tsukakoshi, T., and Shimbo, M., “Improved dielectrically isolated device
intergation by silicon wafer-wafer direct bonding (SDB) technique,” IEDM Tech. Digest, 1986, 210.
8. Okabe, T., Sakamoto, K., and Hoya, K., “Semi-well isolation-based intelligent power IC technology,”
Proc. of ISPSD, 1988, 96.
9. Becke, H. W., “Approaches to isolation in high voltage integrated circuits (invited paper),” IEDM
Tech. Digest, 1985, 724.
10. Rumennik, V., “Power devices are in the chips,” IEEE SPECTRUM, July 1985, 42.
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film,” Proc. of ISPSD, 1990, 97.
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13. Bouchard, J. and Hammmond, F. W., Abstract No. 165, “The iso-layer process,” J. Electrochem.
Soc., vol. 111, p. 197C, 1964.
14. Appels, J. A. and Vaes, H. M. J., “High voltage thin layer devices (RESUF DEVICES),” IEDM Tech.
Digest, 1979, 238.
15. Rosen, R. S., Sprinter, M. R., and Tremain, R. E. Jr., “High voltage SOS/MOS devices and circuit
elements: design, fabrication, and performance,” IEEE J. Solid State Circuits, vol. SC-11, p. 431,
1976.
16. Izumi, Doken, M., and Ariyoshi, H., “C.M.O.S. devices fabricated on buried SiO2 layers formed
by oxygen implantation into silicon,” Electron. Lett., vol. 14, p. 593, 1978.
17. Geis, M. W., Flanders, D. C., and Smith, H. I., “Crystallographic orientation of silicon on an
amorphous substrate using an artificial surface-relief grating and laser crystallization,” Appl. Physics
Lett., vol. 35, p. 71, 1970.
18. Baliga, B. J., Adler, M. S., Gray, P. V., and Love, R. P., “The insulated gate rectifier (IGR) a new
switching device,” IEDM Tech. Digest, 1982, 264.
19. Nakagawa, A., Ohashi, H., Kurata, M., Yamaguchi, H., and Watanabe, K., “Non-latch-up 75A
bipolar-mode MOSFET with large ASO,” IEDM Tech. Digest, 1984, 860.
20. Temple, V. A. K., “MOS controlled thyristor,” IEDM Tech. Digest, 1984, 282.
21. Kamei, T., “High voltage integrated circuits for telecommunication,” IEDM Tech. Digest, 1981, 254.
22. Endo, K., Baba, Y., Udo, Y. Yasui, M., and Sano, Y., “A 500A 1-chip inverter IC with new electric
field reduction structure,” Proc. of ISPSD, 1994, 379.
23. Funaki, H., Yamaguchi, Y., Hirayama, K., and Nakagawa, A., “New 1200V MOSFET structure on
SOI with SIPOS shielding layer,” Proc. of ISPSD, 1998, 25.
24. Yasuhara, N., Nakagawa, A., and Furukawa, K., “SOI device structure implementing 650V high
voltage output devices on VLSIs,” IEDM Tech., Digest, 1991, 141.
25. Merchant, S., Arnold, E., Baumgart, H., Mukherjee, S., Pein, H., and Pinker, R., “Realization of
high breakdown voltage (>700V) in thin SOI devices,” Proc. of ISPSD, 1991, 141.
26. Arnold, E., Merchant, S., Amato, M., Mukherjee, S., and Pein, H., “Comparison of junction-isolated
and SOI high-voltage devices operating in the source-follower mode,” Proc. of ISPSD, 1992, 242.
Power IC Technologies 8-23
27. Funaki, H., Yamaguchi, Y., Kawaguchi, Y., Terazaki, Y., Mochizzuki, H., and Nakagawa, A., “High
voltage BiCDMOS technology on bonded 2µm SOI integrating vertical npn, pnp, 60V-LDMOS
and MPU, capable of 200°C operation,” IEDM Tech. Digest, 1995, 967.
28. Yasuhara, N., Matsudai, T., and Nakagawa, A., “SOI thickness and buried oxide thickness depen-
dencies of high voltage lateral IGBT switching characteristics,” Ext. Abstr. Int. Conf. SSDM, 1993,
270.
29. Omura, I., Yasuhara, N., Nakagawa, A., and Suzuki, Y., “Numerical analysis of switching charac-
teristics — switching speed enhancement by reducing the SOI thickness,” Proc. of ISPSD, 1993, 248.
30. Funaki, H., Matsudai, T., Nakagawa, A., Yasuhara, N., and Yamaguchi, Y., “Multi-channel SOI lateral
IGBTs with large SOA,” Proc. of ISPSD, 1997, 33.
31. Yamaguchi, Y., Nakagawa, A., Yasuhara, N., Watanabe, K., and Ogura, T., “New anode structure
for high voltage lateral IGBTs,” Ext. Abst. Int. Conf. SSDM, 1990, 677.
32. Gonzalez, F., Shekhar, V., Chan, C., Choy, B., and Chen, N., “Fabrication of a 300V high current
(300mA/output), smart-power IC using gate-controlled SCRs on bonded (BSOI) technology,”
IEDM Tech. Digest, 1995, 473.
33. Sumida, H., Hirabayashi, H., Shimabukuro, H., Takazawa, Y., and Shigeta, Y., “A high performance
plasma display panel driver IC using SOI,” Proc. of ISPSD, 1998, 137.
34. Nakagawa, A., Funaki, H., Yamaguchi, Y., and Suzuki, F., “Improvements in lateral IGBT design
for 500V 3A one chip inverter ICs,” Proc. of ISPSD, 1999, 321.
35. Matsudai, T., Yamaguchi, Y., Yasuara, N., Nakagawa, A., and Mochizki, H., “Thin SOI IGBT leakage
current and a new device structure for high temperature operation,” Proc. of ISPSD, 1994, 399.
36. Yamaguchi, Y., Yasuhara, N., Matsudai, T., and Nakagawa, A., “200°C High temperature operation
of 250V 0.5A one chip inverter ICs in SOI,” Proc. of PCIM INTER’98, Japan, 1998, 1.
9
Noise in VLSI
Technologies
9.1 Introduction
The progress of VLSI technologies is a result of an intimate interaction between improvements in IC
chip design and in device properties of the underlying process technologies. The semiconductor
roadmap following Moore’s law is responsible for an exponential decrease of minimum feature size of
devices. The associated increase of device speed and decrease of supply voltage have strong implications
for the available noise margin of a VLSI chip. This chapter addresses the main issues relevant for noise
in VLSI technologies at various levels as indicated schematically in Fig. 9.1. At the microscopic level,
the fundamental sources of noise associated with carrier transport are derived with emphasis on
semiconductors. The next level deals with the noise properties of active devices and passive compo-
nents. Three classes of active devices are chosen for illustration: bipolar junction transistors (BJTs),
field effect transistors (FETs), and two terminal junction devices (diodes). Although the treatment of
these device classes implies silicon-based technologies (Si-BJT, Si-MOSFET, Si-diode), it can generally
be applied to other device classes as well (HBT, MESFET, etc.). Finally, the chip level noise is presented
in terms of the major contributions being amplifier noise, oscillator noise, timing jitter, and intercon-
nect noise. The evolution of VLSI technologies into the deep-sub-micron regime has significant
implications for the treatment of fundamental noise mechanisms, which are briefly outlined in the
last section of the chapter.
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 9-1
9-2 VLSI Technology
FIGURE 9.1 Schematic describing the various levels of noise studied in this chapter and their causal relationship.
Thermal Noise
Thermal noise is, in general, associated with random motion of particles in a force-free environment.
Since the mean available energy per degree of freedom is proportional to temperature, the resulting noise
is referred to as thermal noise. Specifically, carrier transport in semiconductors is treated by considering
energy distribution functions, such as the Fermi–Dirac distribution. The effect of local fields and scat-
tering of carriers in position and momentum space is described by a change in the distribution function.
This is expressed by the Boltzmann transport equation. Noise is a stochastic process and is characterized
in terms of time-averaged quantities, as the instantaneous value cannot be predicted. The fundamental
origins of thermal noise in semiconductors are microscopic velocity fluctuations. Velocity fluctuations
occur due to various mechanisms, such as electron-phonon scattering, electron-electron scattering, etc.
Since the same mechanisms give rise to macroscopic resistivity of a material, noise can be viewed as the
microscopic property of transport. Consequently, noise is intimately related to bulk transport in a
semiconductor. The voltage noise spectral density is given by:
∫ 〈 ∆v ( t )∆v ( t + τ )〉 e
jωτ
S ∆v ( ω ) = 2 ⋅ dτ (9.1)
–∞
In the above expression, ∆v(t) denotes the instantaneous velocity fluctuation, ω the frequency, and S the
spectral density of noise. Velocity fluctuations can also be viewed as the driving force for diffusion, where
the diffusion coefficient is given by:
∫ 〈 ∆v ∆v ( t + τ )〉 e
– jωτ
D(ω) = dτ (9.2)
0
Therefore, the voltage noise spectral density can be directly related to the real part of the frequency-
dependent diffusion function as:
Noise in VLSI Technologies 9-3
S ∆v ( ω ) = 4 ⋅ Re [ D ( ω ) ] (9.3)
The current noise spectral density due to a charge q in a slab of material of length L can be derived from
the carrier velocity fluctuation as:
2
q
S ∆i ( ω ) = -----2 ⋅ S ∆v ( ω ) (9.4)
L
The current noise spectral density of the whole slab of material of area A is then obtained by integrating
the carrier density n(x) and the diffusion coefficient over the length of the sample, as given by:
L
2
4q A
L
2 ∫
S I ( ω ) = ------------
- ⋅ n ( x )Re [ D ( ω, x ) ]dx (9.5)
0
In the limit of uniform carrier density, thermal equilibrium, and neglecting quantum effects, the diffusion
coefficient can be expressed in terms of the carrier mobility using the Einstein relation:
kT
D = ------µ (9.6)
q
A
S I ( ω ) = 4kT ⋅ ⎛ nqµ ⋅ ----⎞ (9.7)
⎝ L⎠
The above expression leads to the well-known Johnson thermal noise of a conductance G = σA/L, where
the conductivity is σ = nqµ and the carrier mobility is denoted by µ:
S I ( ω ) = 4kT ⋅ G ( ω ) (9.8)
In general, the conductance is the real part of the frequency-dependent admittance of the material
as indicated above. Note that the thermal noise expression given here is valid only when the mean
scattering time of the carriers is negligible with respect to the inverse of the frequency at which the
noise is measured. This assumption is true for most studies of semiconductors where the mean
scattering times are on the order of 1 ps. The generalized expression for finite scattering times is
discussed in a later section. The thermal noise expression also provides a direct relation between the
microscopic noise and the bulk resistance (conductance), indicating the nature of noise as being due
to the same type of scattering mechanisms as those causing resistance in a sample. A prominent feature
of thermal noise is its direct dependence on temperature, giving rise to the possibility of measuring a
thermodynamic quantity with noise.
Shot Noise
The discrete nature of particles undergoing an average flow in space, together with their velocity distri-
bution, results in a random arrival at a fixed plane of incidence. The corresponding fluctuations of the
flow are referred to as shot noise. Specifically, the discrete flow of charge in a field yields shot noise of
current in semiconductors. Shot noise can be derived as being due to a random train of pulses corre-
sponding to events, such as carrier emission from an electrode, carrier injection across a semiconductor
junction, etc. The power spectral density of the resulting time-dependent waveform is given by:
9-4 VLSI Technology
2 2
S ( ω ) = 2ν ⋅ 〈 a 〉 ⋅ F ( ω ) (9.9)
Here, F(ω) is the Fourier transform of the impulse function, ν the mean rate of the events, and <a2>
the mean square amplitude of the pulses. For a current pulse δi(t) due to the transit of a charge q through
a sample, the Fourier transform is given by:
τ
T
1
∫
– jωτ
F ( ω ) = --- ⋅ δi ( t ) ⋅ e dt (9.10)
q
0
At sufficiently low frequencies, the transit time τΤ can be neglected with respect to 1/ω, and the current
pulse can be considered a delta function. The Fourier transform function then becomes unity. The mean
rate of current pulses is ν = I/q, where I is the mean value of the current, and the mean pulse amplitude
<a> = q, so that the power spectral density of shot noise current is given by:
S I ( ω ) = 2qI (9.11)
Note that the above expression is valid only for negligible transmit times of the carriers through a sample
region with respect to the inverse of the frequency at which the noise is measured. The shot noise for
non-negligible transit times and scattering times is treated in more detail later. One of the most significant
properties of shot noise is its dependence on the mean current flow or bias in a semiconductor, in contrast
to thermal noise which is dependent only on the temperature and resistivity of the material. Shot noise
can also be measured only when the energy distribution function of the carriers can be probed by a
reference plane of incidence, such as a p-n junction in a semiconductor.
Generation-Recombination Noise
The generation and recombination of charge carriers due to traps in semiconductors results in fluctua-
tions of the current flow through the semiconductor. The temporal change in the carrier number N from
a rate of generation g(t) and a rate of recombination r(t) is given by:
d ( ∆N ) ∆N
---------------- = – -------- + ∆g ( t ) – ∆r ( t ) (9.12)
dt τ
Here, τ is the mean lifetime of the carriers. The noise spectral density of the carrier number fluctuations
is found to be:
2 τ
S N ( ω ) = 4 〈 ∆N 〉 ⋅ -------------------
2 2
- (9.13)
1+ω τ
A current fluctuation is related to a carrier number fluctuation through ∆I/I = ∆N/N. The current noise
spectral density from generation and recombination of carriers is then given by:
2
I 2 τ
S I ( ω ) = 4 -----0-2 〈 ∆N 〉 ⋅ -------------------
2 2
- (9.14)
N0 1+ω τ
Here, I0 denotes the mean current and N0 the mean carrier number. The form of the above expression
implies a constant noise power below a characteristic frequency ωc = 1/τ, and a 1/ω2 dependence (Lorent-
zian) at higher frequencies. This type of noise is observed in systems with a single well-defined trapping
time constant or energy level of traps. The most significant feature of GR noise is its explicit frequency
Noise in VLSI Technologies 9-5
dependence, in contrast to the “white” spectral densities of thermal and shot noise. This frequency
dependence has strong implications for semiconductors, since the characteristic frequency is well within
the frequency range of most applications.
Flicker Noise
Flicker noise is, in general, a phenomenon observed in many systems with an inverse frequency dependence
of the noise spectral density over a wide frequency regime. In semiconductors, the presence of energy
traps can lead to generation and recombination of carriers and a corresponding frequency-dependent
noise of the flicker noise type. A phenomenological approach for deriving the frequency dependence of
flicker noise is to consider the expression for generation-recombination noise given by:
τ τ
S I ( ω ) = A ( I ) ⋅ -------------------
2 2
- (9.15)
1+ω τ
Here, A(I) summarizes the current-dependent pre-factor given earlier. A distribution of characteristic
time constants given by a probability density P(τ)dτ would result in a current noise spectral density of
the form:
τ1
τ
S I ( ω ) = A ( I ) ⋅ ⎛ -------------------
- ⋅ P ( τ )dτ⎞
∫
⎝ 1 + ω2 τ2 ⎠
(9.16)
τ0
In the case of MOSFETs, the tunneling of carriers from the channel through an oxide to a trap at a
distance x from the channel/oxide interface produces a probability distribution of time constants:
1
P ( τ ) ∝ --- (9.17)
τ
Such a distribution of time constants yields the flicker noise expression for the current noise spectral density:
A(I)
S I ( ω ) ∝ ----------- (9.18)
ω
Note that the inverse frequency dependence of the noise is obtained from the integral above with the
approximation: 1/τ1 < ω < 1/τ0. The most important characteristic of flicker noise is its explicit inverse
frequency dependence, like GR noise. Another feature is the dependence of flicker noise magnitude on
material properties such as trap densities, carrier mobility, etc. Consequently, no general form can be
given for the flicker noise of semiconductors, but specific devices need to be considered.
Although the overall frequency dependence of flicker noise is universally found to be inversely pro-
portional to frequency in semiconductors, the expression for the amplitude of flicker noise is strongly
dependent on device technology. In general, for Si-BJTs and Si-MOSFETs, the flicker noise power is found
to increase with bias current according to a power-law as given by:
γ
I
S I ( ω ) = K ⋅ -----α- (9.19)
ω
The bias exponent γ has typical values between 1 and 2, and the frequency exponent α varies around
unity by about 20%.
9-6 VLSI Technology
Quantum Limit
Quantum effects become relevant for noise processes for sufficiently high frequencies and low temper-
atures, such that a quantum of energy is comparable to or larger than the thermal energy:
hω ≥ kT (9.20)
Consequently, the treatment of thermal or shot noise power requires modifying the mean available energy
for each degree of freedom, which results in the following generalized expression for the spectral density
of current noise:
1 hω hω ⁄ kT ⎞
S I ( ω ) = S I ( ω ) ⋅ ⎛ --- ------- + --------------------------
Q C
- (9.21)
⎝ 2 kT [ e hω ⁄ kT – 1 ]⎠
Here, the quantum correction (denoted by Q) to the classical noise power (denoted by C) is given by
the expression in the parentheses, which includes both the Planck distribution function and the zero-
point energy term. In the limit of low frequencies or high temperatures ( hω << kT), the expression in
parentheses reduces to unity and the classical form for the noise is recovered.
A further implication of quantum effects is a fundamental lower limit on the noise power of a linear
amplifier, which is given by:
∆P min (G – 1)
- = ------------------ ⋅ hω 0
------------ (9.22)
∆f G
Here, P denotes the noise power G of the amplifier gain and ∆f is a frequency interval centered around
the signal frequency ω0. This limit on the noise is a result of the uncertainty principle applied to the
number of photons and the corresponding phase of an electromagnetic wave.
Passive Components
The most relevant contribution to noise from passive components is the thermal noise of a resistance R
given by:
t
S v = 4kTR (9.23)
The thermal noise is determined by the magnitude of the resistance and its equilibrium temperature
only. It exhibits a “white” (constant) noise spectral density as a function of frequency and becomes
frequency dependent at high frequencies, either due to the reactive components of a real resistor or
fundamentally due to non-equilibrium effects.
Besides the thermal noise of resistors, the reactive components (inductors and capacitors) also play a
major role in affecting noise in VLSI chips. The ideal reactive components are not associated with any
noise sources. However, non-ideal properties such as series resistance in inductors and leakage currents
in capacitors give rise to thermal and shot noise, respectively. Moreover, the reactive components intro-
duce the frequency dependence of noise or cause phase shifts between voltage and current noise sources.
Noise in VLSI Technologies 9-7
Finally, the thermal noise bandwidth of a resistance R or a conductance G is limited by the series
inductance L or the shunt capacitance C, respectively. The resulting integrated thermal noise powers are
given by:
2 kT
〈 i n〉 = ------ (9.24a)
L
2 kT
〈 v n〉 = ------ (9.24b)
C
Here, in and vn denote the noise current and noise voltage, respectively, integrated over the whole
frequency bandwidth.
Diodes
A p-n junction is characterized by a depletion region and an energy barrier. The depletion region can
be modeled by a frequency-dependent admittance, comprised of a diffusion plus depletion conductance
GJ(ω) and a diffusion plus depletion capacitance CJ(ω). In the presence of a bias across the junction, the
current-voltage characteristic is given by:
⎧ qV ⎫
I D = I S ⋅ ⎨ exp ⎛ -------⎞ – 1 ⎬ (9.25)
⎝ kT ⎠
⎩ ⎭
Here, ID is the total current through the diode, IS the reverse saturation current, and V the forward voltage
across the diode. The junction noise is shown to be arising from the shot noise due to current across the
junction, and the thermal noise from the conductance of the junction:
S I ( ω ) = 2q ( I D + 2I S ) + 4kT [ G J ( ω ) – G J ( 0 ) ] (9.26)
Here, the frequency-dependent junction conductance is denoted by GJ(ω) and the low-frequency junction
conductance is given by:
q
G J ( 0 ) = ------ ⋅ ( I D + I S ) (9.27)
kT
Note that the general expression for the diode noise (Eq. 9.26) reduces to the pure shot noise form 2qI
at low frequencies and to the thermal noise form 4kTG at zero bias.
t
S Rx = 4kTR x (9.28a)
s
S IB = 2qI B (9.28b)
9-8 VLSI Technology
FIGURE 9.2 Schematic cross-section of an npn bipolar junction transistor in a conventional device layout.
s
S IC = 2qI C (9.28c)
γ
f I
S IB = K B ⋅ ---Bα- (9.28d)
f
γ
f I
S IC = K C ⋅ ---Cα- (9.28e)
f
The flicker noise magnitudes are strongly dependent on device processing and technology, and are
summarized in the pre-factors K for each term. Note that, in general, the flicker noise exponents α and
γ are different for base and collector currents. The resistor Rx denotes the total of base, emitter, and
collector resistances, and the individual thermal noise terms need to be included appropriately within
the device model. Since the noise sources are distributed in various regions of the device, it is useful to
refer the noise either at the input or the output in order to estimate their contributions to the overall
noise performance of the device. Here, we choose to refer the noise to the input of the device. The total
input referred noise is given by taking into account the transconductance gm:
2
IN t s f 2 s f ( Rx + Zπ )
S tot = S Rx + ( S IB + S IB ) ⋅ R x + ( S IC + S IC ) ⋅ ------------------------
2 2
- (9.29)
gm Zπ
In the above expression, the input impedance relevant for noise is denoted as Zπ, indicating a π-model
for the small-signal equivalent circuit of the device. For high gain BJTs, the general expression can be
simplified and separated to obtain the voltage and current noise terms.
The input referred voltage noise is given by:
γ 2
I [ RB + Zπ ]
S v = 4kTR B + ⎛ 2qI B + K B ⋅ ---Bα-⎞ R B + 2qI C ---------------------------
IN 2
- (9.30)
⎝ f ⎠ g Z
2 2
m π
γ γ
I I 1
S i = 2qI B + K B ⋅ ---Bα- + ⎛ 2qI C + K C ⋅ ---Cα-⎞ ⋅ ----------------
IN
-2 (9.31)
f ⎝ f ⎠ gm Zπ
2
The input referred voltage and current noise expressions can be used to completely characterize the
noise properties of an individual device. The circuit noise performance is obtained by deriving the noise
parameters from the above expressions, as described in the next section. Note that all types of bipolar
devices (heterojunction bipolar transistors, etc.) can be treated in a manner similar to that given here.
Noise in VLSI Technologies 9-9
The overall frequency dependence of noise in BJTs is discussed, together with that of MOSFETs, at the
end of the next section.
t
S Rx = 4kTR x (9.32a)
s
S IG = 2qI G (9.32b)
t
S ID = β ⋅ 4kTg µ (9.32c)
γ
f I
S IG = K G ⋅ ----Gα (9.32d)
f
γ
f I
S ID = K D ⋅ ----Dα (9.32e)
f
Note that, except for the channel thermal noise of the drain current, the intrinsic noise sources in a
MOSFET are very similar to that of a BJT. The pre-factor β to the channel thermal noise was introduced
to account for the specific operation of FETs in general. It was shown to have a value of 2/3 for MOSFETs
and a value between 1/3 and 2/3 for JFETs. For sub-micron MOSFETs, high field effects are known to
increase its value to well above 2/3. In a manner similar to that used for BJTs, one can express the noise
at the input by taking into account the transconductance of the device, and then separate into voltage
and current contributions.
The total input referred noise is given by:
2
IN t s f 2 t f ( Rx + Zπ )
S tot = S Rx + ( S IG + S IG ) ⋅ R x + ( S ID + S ID ) ⋅ ------------------------
2 2
- (9.33)
gm Zπ
γ γ 2
I I [ RG + Zπ ]
S v = 4kTR G + ⎛ 2qI G + K G ⋅ ----Gα⎞ ⋅ R G + ⎛ β ⋅ 4kTg m + K D ⋅ ----Dα⎞ ----------------------------
IN 2
(9.34)
⎝ f ⎠ ⎝ f ⎠ g Z
2 2
m π
γ γ
I I 1
S i = 2qI G + K G ⋅ ----Gα + ⎛ β ⋅ 4kTg m + K D ⋅ ----Dα⎞ ----------------
IN
-2 (9.35)
f ⎝ f ⎠ gm Zπ
2
The overall frequency behavior of the noise in FETs is similar to that of BJTs; however, the contributions
from the device parameters are different in each case specific to the device properties. In the above
expressions, the flicker noise becomes predominant below a “corner” frequency fc1; whereas above a
second “corner” frequency fc2, the noise increases with frequency. Figure 9.4 illustrates this behavior
schematically, where the high-frequency increase of noise is referred to as being due to impedance
coupling. In this region, the thermal or shot noise from one region of the device is coupled into other
regions due to the reactive components and gives rise to frequency dependence. Figure 9.5 also illustrates
the overall behavior of noise figure vs. frequency measured on devices from different technologies. The
bias-dependent behavior of noise in the low-frequency flicker noise regime is illustrated in Fig. 9.6, where
measured output current noise power at 10 Hz is plotted as function of drain current for n-channel
MOSFETs, with different gate lengths as given in the legend of the figure. Note that although all devices
exhibit power law behavior, the exponent increases with decreasing gate length.
Amplifier Noise
Amplifier noise is a small-signal phenomenon and can thus be treated by a linear approximation. It is
directly determined by the noise and gain of the devices used in the design. The noise figure of an
amplifier can be computed from the noise parameters of the active devices used in the circuit. The noise
FIGURE 9.4 Schematic of amplitude noise as function of frequency, indicating the three distinct regions of noise
(flicker, thermal/shot, and impedance coupling).
Noise in VLSI Technologies 9-11
FIGURE 9.5 Measured noise figure vs. frequency for various device technologies. The plot indicates the relative
magnitude of the three noise regions shown schematically in Fig. 9.4. The plot also presents the wide range of noise
behavior found in device technologies.
FIGURE 9.6 Output current noise spectral density vs. drain current for a set of n-channel MOSFETs with equal
gate widths and different lengths, as given in the legend. Note that all devices exhibit power-law bias dependence,
but the exponent increases with decreasing gate length.
parameters are a set of four quantities that characterize the noise of any 2-port (e.g., active device,
amplifier, etc.) completely. They are derived from the input referred voltage and current noise sources
of the 2-port in the following manner. For a noise voltage vn and a noise current in at the input of a 2-
port, the corresponding noise correlation matrix is given by:
9-12 VLSI Technology
2 *
1
Ĉ = ------- ⋅ 〈 v n〉 〈 v n i n〉 (9.36)
2B * 2
〈 v n i n〉 〈 i n〉
Here, B denotes the frequency bandwidth. The voltage and current noise sources used in the expression
above are related to the noise spectral densities derived in the previous sections as follows:
2
IN 〈 v n〉
S v = ---------
- (9.37a)
B
2
IN 〈 i n〉
S i = --------
- (9.37b)
B
The noise parameters are the minimum noise figure Fmin, the complex optimum source impedance Zopt, and
the noise conductance gn. They are expressed in terms of the input referred noise voltage and current as follows:
2
[ v n + Z opt ⋅ i n ]
F min = 1 + ----------------------------------
- (9.38a)
4kTBZ opt
2
〈 v n〉
Z opt = ---------
2
- (9.38b)
〈 i n〉
2
〈 i n〉
g n = -------------
- (9.38c)
4kTB
The correlation matrix expressed in terms of the four noise parameters is given by:
2 ( F min – 1 )
g n Z opt ----------------------- – g n Z opt
2
Ĉ = 2kT ⋅ (9.39)
( F min – 1 ) *
----------------------- – g n Z opt gn
2
The noise parameters are directly measurable quantities for an active device or circuit and, thus, the
noise correlation matrix can be evaluated quantitatively. The overall noise figure of a linear 2-port depends
not only on its four noise parameters, but also on the source impedance as given by:
g 2
F = F min + ----n- ⋅ Z s – Z opt (9.40)
Rs
Here, Rs is the real part of the source impedance Zs. For a cascade of amplifiers with individual noise
figures Fi and gain Gi (i = 1, 2, …), the total noise figure is given by:
( F2 – 1 ) ( F3 – 1 )
- + ------------------- + …
F = F 1 + ------------------ (9.41)
G1 G1 G2
Noise in VLSI Technologies 9-13
The above expression shows that the primary contribution to the total noise figure of any amplifier
comprised of several stages is from the initial stages. A quantity that takes into account both noise figure
and gain of an amplifier is the noise measure given by:
F–1
M = ------------------------- (9.42)
1 – (1 ⁄ G)
The noise measure can be used as a figure-of-merit for the overall noise–gain performance of a linear
amplifier for analog applications. As described by Eq. 9.41, the primary contribution to amplifier noise
can be attributed to the noise of the input active device. Hence, an experimental study of noise in devices
provides valuable information for optimum design of low noise amplifiers.
For the purpose of illustrating the main features of amplifier noise, we show measured RF noise
behavior of an active device. Figure 9.7 shows the frequency dependence of minimum noise figure, input
referred voltage noise, input referred current noise, and noise measure for a BJT. Note that in the frequency
range shown in the figure, all quantities increase with frequency corresponding to the impedance coupling
regime. The voltage noise is a measure of the thermal noise of the input resistance, and the current noise
is a measure of the input referred shot noise. In order to optimize the device technology for low noise
applications, it is important to study the relative contributions from the various regions of an active
device to the total noise power. This is done most conveniently by extracting a small-signal noise model
of the device from measured data. After successively removing the noise contributions from various
regions, the resulting noise parameters can be plotted and compared. Figure 9.8 shows the results of
such noise modeling of a BJT. The four noise parameters are plotted vs. frequency, with the individual
contributions from the various regions of the device illustrated in the figure. Here, it is seen that the
FIGURE 9.7 Plots of minimum noise figure, input referred voltage noise, input referred current noise, and noise
measure vs. frequency for an npn BJT with an emitter width of 0.5 µm technology. The plots show the increase of
noise with frequency in the impedance coupling regime.
9-14 VLSI Technology
FIGURE 9.8 Plots of the four RF noise parameters vs. frequency obtained from fitting measured data on an npn
BJT to a small-signal model of the device. The different curves in each plot indicate the individual contributions
from the various regions of the device, as discussed in the text.
major contribution to the minimum noise figure is the base resistance, followed by the base–collector
shot noise at higher frequencies. The noise conductance is primarily determined by the base–collector
shot noise. The optimum source resistance is given by the thermal noise of the base resistance. Finally,
the optimum source reactance is not explicitly determined by any of the noise sources, but by the input
impedance of the device.
Oscillator Noise
The major noise source in oscillators is phase noise caused by mixing of device noise (flicker, shot,
thermal) with the carrier frequency due to the non-linear operation of the circuits. In general, noise in
oscillators is a large-signal phenomenon and, hence, linearization techniques have limited applicability.
Several approaches have been published for calculating the phase noise. The simplest is that of Leeson,
which estimates the phase noise of oscillators due to non-linear mixing of device flicker noise, and finite
bandwidth of the oscillator. More advanced approaches include both analytical and numerical studies,
as given in the references. Here, we briefly outline the fundamental features of noise in a negative
conductance LCR oscillator driven by an external current source (e.g., an active device). In the presence
of small-signal noise, the output voltage of the oscillator with an intrinsic amplitude v0 and frequency
ω0 is given by:
v ( t ) = v 0 ⋅ [ 1 + a ( t ) ] ⋅ cos { ω 0 t – ϕ ( t ) } (9.43)
Noise in VLSI Technologies 9-15
The amplitude fluctuations a(t) and phase fluctuations φ(t) can be evaluated to first order by just
taking into account the mixing of the noise with the free oscillations. The spectral density of the amplitude
fluctuations (AM noise) is given by:
SI ( ω )
S a ( ∆ω ) = ---------------------------------------------------------------------------
2
- (9.44)
2 ∆ω
2v 0 ( G L – G 0 ) ⋅ 1 + Q 0 ⎛ --------⎞
2 2
⎝ ω0 ⎠
Here, GL is the loss conductance, G0 the lowest-order term of an expansion of the nonlinear negative
conductance, and Q0 the Q-factor of the oscillator. The frequency offset from the fundamental oscillator
is denoted by ∆ω. The spectral density of the phase fluctuations (PM noise) is given by:
2S I ( ω )
S ϕ ( ∆ω ) = ---------------------------------------------------------
-2 (9.45)
2 ∆ω
v 0 ( G L – G 0 ) ⋅ Q 0 ⎛ --------⎞
2 2
⎝ ω0 ⎠
Both amplitude and phase noise exhibit a ∝ 1/∆ω2 dependence as a function of frequency offset from
the oscillation frequency. Note that the phase noise is always larger than the amplitude noise and is
therefore of most relevance to chip design. Moreover, a frequency-dependent current noise SI (ω) ∝ 1/ω
(flicker noise of device) gives rise to a ∝ 1/∆ω3 dependence of phase noise. Figure 9.9 shows schematically
a simplified case of oscillator noise with two typically encountered types of phase noise frequency
dependencies. For small offset frequencies, the phase noise is caused by up-conversion of the device
flicker noise. At larger offset frequencies, the phase noise shows a behavior depending on the value of
the flicker noise corner frequency with respect to that of the oscillator bandwidth.
Timing Jitter
In digital circuits, the timing of pulses exhibits a random fluctuation as a function of time, which is
referred to as jitter. Jitter is fundamentally caused by the noise of individual components of the circuit
FIGURE 9.9 Schematic of frequency dependence of phase noise vs. offset from the fundamental frequency. In a
simplified model, the phase noise can be treated as a product of two terms resulting from device noise and oscillator
bandwidth. The two cases shown relate the flicker noise corner frequency fc to the oscillator bandwidth fB.
9-16 VLSI Technology
(active devices, resistors, interconnect delays, etc.) and is of primary concern to the design of low-
noise oscillators. As signal levels decrease and clock frequencies increase, jitter becomes a serious noise
phenomenon in VLSI circuits. Jitter can be expressed in terms of fluctuations of the fundamental
period of oscillation. The distribution of these fluctuations has a standard deviation that is used as a
measure of jitter:
2 2
〈 T 〉 – 〈 T〉
σ T = -------------------------------- (9.46)
〈 T〉
For example, the thermal noise of collector load resistors in a differential pair stage of a ring oscillator
is shown to result in jitter given by:
t
σ RC = 2kTC C ⋅ f ( I E, R C ) (9.47)
Note that the above expression contains the voltage noise fluctuations from the collector resistance RC
and shunt capacitance CC. The thermal noise of transistor input resistances (e.g., base or gate resistance)
is shown to give rise to a jitter of the form:
t
σ RX = 4kTR X ⋅ f ( I E, C C ) (9.48)
Note that here the thermal noise of the input resistance Rx directly affects the jitter of the circuit. Similarly,
other noise sources at the oscillator input will modulate the fundamental frequency and contribute
proportionally to jitter.
Interconnect Noise
Interconnects in VLSI chips are a source of noise referred to as crosstalk, which originates from capacitive
and inductive coupling of signals between transmission lines. A quantitative treatment of crosstalk
requires an appropriate modeling of the impedance of the transmission lines. At sufficiently high fre-
quencies, the wavelength of the propagating electromagnetic wave becomes comparable to the length
scales of the transmission lines. In this regime, the transmission needs to be treated as a distributed entity.
The electrical properties of a distributed transmission line can be characterized by the characteristic
impedance Z0 and the propagation coefficient γ. For a “quasi-TEM” mode of propagation along the line,
these quantities are given by:
R + jωL
Z0 = --------------------- (9.49a)
G + jωC
Here, the transmission line is characterized by a lateral resistance per unit length R, a lateral inductance
per unit length L, a perpendicular conductance per unit length G, and a perpendicular capacitance per
unit length C. The magnitude of the crosstalk between two lines is determined by their mutual capacitance
Cm and mutual inductance Lm. Since the capacitive noise is proportional to Cm⋅dV/dt, and the inductive
noise is proportional to Lm⋅dI/dt, the crosstalk can be treated as being proportional to VDD/τ and pro-
portional to Isat/τ, where τ is a pulse rise or fall time.
Another more fundamental source of noise in VLSI interconnects is the thermal noise of transmission
lines. It can be shown that by treating the interconnect as a distributed transmission line, the thermal
noise can be expressed as:
Noise in VLSI Technologies 9-17
t
S v = 4kTR ⋅ f ( γ , l ) (9.50)
In the above expression, the thermal noise due to the resistance R of the interconnect is modified by a
function of only the propagation coefficient γ and the total length l of the interconnect.
Scaling
The scaling of silicon technology with decreasing minimum feature size is associated with changes in
active device parameters as well as changes in passive components and interconnect dimensions. The
effect of technology scaling on noise in VLSI chips can be estimated by considering the dependence of
the noise of the individual components of the chip on their scaled properties. It turns out that general
expressions for technology scaling of noise cannot be formulated, since device dimensions are chosen
specific to the chip design. However, one can observe certain trends for active devices. It is found that
in MOSFETs, the flicker noise scaling is primarily determined by changes in the gate-oxide quality (trap
density in the oxide) and roughness of the oxide–channel interface (carrier mobility in the channel). At
RF frequencies, the noise is dependent on device dimensions (base resistance of BJT, gate resistance of
MOSFET, etc.) and on small-signal properties (base-collector capacitance, gate-channel capacitance, etc.).
Although the specific choice of device dimensions primarily determines its noise, the trend of increasing
cutoff frequencies results in improvement of RF noise at a given frequency due to decreased device
parasitics. However, the thermal noise of interconnects increases as the technology is scaled to smaller
dimensions, due to the associated decrease of cross-sectional area.
Processing
Process development in VLSI technologies is intimately related to device performance. As described
above, the RF noise in BJTs is significantly determined by thermal noise in the base resistance and by
shot noise from the base–collector junction. These contributions can be minimized by utilizing super-
self-aligned device layouts, as shown schematically in Fig. 9.10. In this case, the extrinsic base region
is significantly reduced to decrease the base thermal noise. The effect of the shot noise from the
base–collector junction is minimized by reducing the base–collector capacitance that acts as a feedback
capacitance and couples the collector current shot noise into the base. In MOSFETs, a reduction of
the gate resistance is achieved through the use of higher conducting gate stacks (Fig. 9.11)or a multi-
finger layout. Moreover, the coupling of channel thermal noise into the gate region can be minimized
by reducing the gate–channel capacitance. In general, processing has a strong influence on the flicker
noise of semiconductor devices. In BJTs, the passivation of the base–emitter junction region improves
flicker noise substantially. In MOSFETs, the quality of the gate-oxide and its interface with the channel
FIGURE 9.10 Schematic of a super-self-aligned BJT layout used to reduce base thermal noise and the effect of
base–collector shot noise.
9-18 VLSI Technology
FIGURE 9.11 Schematic of a silicide-gate MOSFET used to reduce the thermal noise from the gate resistance.
affects flicker noise and can be improved through annealing treatments. One of the approaches being
studied presently for reducing RF noise in MOSFETs is the use of silicon-on-insulator substrates instead
of conducting substrate material, in order to reduce parasitic elements of the device.
Non-Equilibrium Transport
In deep-submicron devices at high electric fields, the assumption of thermal equilibrium between carriers
and lattice is not valid. Here, we briefly indicate the type of corrections required for estimating the noise
in non-equilibrium transport.
The diffusion coefficient in non-equilibrium transport can be modified by approximating it to be a
simple frequency-dependent quantity of the form:
D(0)
D ( ω ) = -----------------------2 (9.51)
1 + ( ωτ )
SI ( 0 )
S I ( ω ) = ----------------------
-2 (9.52)
1 + ( ωτ )
In the above expression, the quantity τ is the mean scattering time of the carriers. A further effect of
non-equilibrium transport is velocity-velocity correlations, which modify the macroscopic values of the
noise spectral densities and need to be considered in detail.
The general expression for shot noise in semiconductors needs to include finite carrier transit times
and is given by:
2 2
〈 N 〉 – 〈 N〉
S I ( ω ) = 2qI ⋅ ----------------------------- ⋅ f ( ω, τ, τ T ) (9.53)
〈 N〉
Here, N is the number of carriers, τ the mean scattering time, and τT the carrier transit time. We can
consider several limiting cases of the above expression. For sufficiently low frequencies and small transit
times, such that ω << 1/τ << 1/τΤ, the shot noise is given by:
2 2
〈 N 〉 – 〈 N〉
S I ( ω ) = 2qI ⋅ ----------------------------- (9.54)
〈 N〉
The above expression is the full shot noise in a semiconductor sample where all the carriers are traversing
the sample along the field direction. For a Poisson distribution function of carrier number, the variance
Noise in VLSI Technologies 9-19
of the fluctuations is equal to the mean of the distribution, and then the simple expression 2qI is recovered
for the shot noise. For sufficiently small scattering times, such that τ << τT , the shot noise is given by:
2
〈 N 〉 – 〈 N〉
2
⎧ 2τ 1 ⎫
S I ( ω ) = 2qI ⋅ ----------------------------- ⋅ ⎨ ----- ⋅ -----------------------2 ⎬ (9.55)
〈 N〉 τ
⎩ T 1 + ( ωτ ) ⎭
The above expression indicates that the shot effect is reduced by the randomizing due to scattering of
carriers. At high frequencies, the shot noise also shows a decrease due to effective acceleration of carriers
along the field direction.
9.6 Conclusions
In this chapter, the issue of noise in VLSI technologies was treated by introducing the microscopic noise
mechanisms from fundamental carrier transport in semiconductors. The noise properties of active
semiconductor devices and passive components were given in a general form and certain approximations
relevant for most applications were outlined. The noise at the chip level was presented in terms of specific
circuits where noise-critical applications are realized. Finally, trends in future VLSI technologies and their
implications for noise were briefly mentioned.
Acknowledgments
Collaborations with the following organizations within Lucent Technologies are gratefully acknowledged:
VLSI Technology Integration Department in Orlando, FL; Analog Design Methodology Group in Read-
ing, PA; Compact Modeling and Measurements Group in Cedar Crest, PA. In addition, we gratefully
acknowledge the many helpful discussions with colleagues from the Physical Research, Silicon Research,
and Wireless Research Laboratories at Bell Laboratories.
References
Section 9.1
1. Meindl, J. D., “Ultra-Large Scale Integration,” IEEE Trans. Elec. Dev., ED-31, 1555, 1984.
2. van der Ziel, A. and Amberiadis, K., “Noise in VLSI,” VLSI Electronics, Vol. 7, Academic Press, 1984,
261ff.
3. van der Ziel, A., “Noise in VLSI,” VLSI Handbook, Academic Press, 1985, 603ff.
4. Tsividis, Y., Mixed Analog-Digital VLSI Devices and Technology, McGraw-Hill, 1995.
5. Martin, S., Archer, V., Boulin, D., Frei, M., Ng, K., and Yan, R.-H., “Device Noise in Silicon RF
Technologies,” Bell Labs Technical Journal, 2(3), 30, 1997.
Section 9.2
6. van der Ziel, A., Noise in Measurements, Wiley, 1976.
7. Gupta, M. S. (ed.), Electrical Noise: Fundamentals & Sources, IEEE Press, 1977.
8. Buckingham, M. J., “Noise in Electronic Devices and Systems,” Wiley, 1983.
9. Ferry, D. K. and Grondin, R. O., Physics of Submicron Devices, Plenum Press, 1991.
Section 9.3
10. Motchenbacher, C. D. and Connelly, J. A., Low Noise Electronic System Design, Wiley, 1993.
11. Ng, K., Complete Guide to Semiconductor Devices, McGraw-Hill, 1995.
12. Martin, S., Booth, R., Chyan, Y.-F., Frei, M., Goldthorp, D., Lee, K.-H., Moinian, S., Ng, K., and
Subramaniam, P., “Modeling of Correlated Noise in RF Bipolar Devices,” IEEE MTT-S Digest,
MTT-Symposium, 1998, 941.
13. See also Refs. 6, 7, and 8.
9-20 VLSI Technology
Section 9.4
14. Hillbrand and Russer, “An Efficient Method for Computer Aided Noise Analysis of Linear Amplifier
Networks,” IEEE Trans. Circ. Syst., CAS-23, 235, 1976.
15. Abidi, A. and Meyer, R.G., “Noise in Relaxation Oscillators,” IEEE J. Solid-State Circuits, SC-18,
794, 1983.
16. Brews, J. R., “Electrical Modeling of Interconnections,” Submicron Integrated Circuits (Ed. R. K.
Watts), Wiley, 1989.
17. Vendelin, G. D., Pavio, A. M., and Rohde, U. L., Microwave Circuit Design, Wiley, 1990.
18. Gray, P. R. and Meyer, R. G., Analog Integrated Circuits, Wiley, 1993.
19. Engberg, J. and Larsen, T., Noise Theory of Linear and Nonlinear Circuits, Wiley, 1995.
20. Verghese, N. K., Schmerbeck, T. J., and Allstot, D. J., Simulation Techniques and Solutions for Mixed-
Signal Coupling in Integrated Circuits, Kluwer, 1995.
21. Schaeffer, D. K. and Lee, T. H., “A 1.5 V, 1.5 GHz CMOS Low Noise Amplifier,” IEEE J. Solid-State
Circuits, 32, 745, 1997.
22. McNeill, J. A., “Jitter in Ring Oscillators,” IEEE J. Solid-State Circuits, 32, 370, 1997.
23. Restle, P. J., Jenkins, K. A., Deutsch, A., and Cook, P. W., “Measurement and Modeling of On-Chip
Transmission Line Effects in a 400 MHz Microprocessor,” IEEE J. Solid-State Circuits, 33, 662, 1998.
24. Demir, A., Mehrotra, A., and Roychowdhury, J., “Phase Noise in Oscillators: A Unifying Theory
and Numerical Methods for Characterization,” IEEE Trans. Circ. Syst.-1: Fundamental Theory and
Application, to be published, 1999.
25. See also Refs. 6 and 8.
Section 9.5
26. Simeon, E. and Claeys, C., “The Low-Frequency Noise Behavior of Silicon-on-Insulator Technol-
ogies,” Solid-State Electronics, 39, 949, 1996.
27. Abou-Allam, E. and Manku, T., “A Small-Signal MOSFET Model for Radio Frequency IC Appli-
cations,” IEEE Trans. CAD of IC and Systems, 437, 1997.
28. Tin, S. F., Osman, A. A., and Mayaram, K., “Comments on “A Small-Signal MOSFET Model for
Radio Frequency IC Applications,” IEEE Trans. CAD of IC and Systems, 17, 372, 1998.
29. See also Refs. 7 and 9.
10
Micromachining
10.1 Introduction
There has been a tremendous growth in activity over the past seven years in exploring the use of
micromachining for the fabrication of novel microstructures, microsensors, and microdevices and also
their integration with electronic circuits. Specific application areas have developed to such an extent
that there are specialist meetings on the following topics: sensors and actuators,1 microelectromechanical
system (MEMS),2 microchemical analysis systems (µTAS),3 optical-MEMS,4 MEMS-electronics,5 chem-
ical sensors,7 and microstructures and microfabricated systems.7 Early examples of MEMS devices and
innovations are reviewed in Peterson’s8 classic paper. Up until recently, the MEMS micromachining
processes were developed outside the realm of a CMOS line although the advantages of IC fabrication
processes and the economies of batch fabrication have been used for production of microdevices at low
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 10-1
10-2 VLSI Technology
cost and high volume. The tremendous successes of microfabricated silicon pressure sensors used for
blood pressure monitoring and automotive air intake manifold pressure sensing, ink-jet printer heads,
and the air bag accelerometer sensors, and most recently projection overhead display systems, demon-
strate the tremendous success of this technology. There are several important differences between MEMS
processing and IC processing that make this an exciting and rapidly evolving field:
• Wider range of materials
• Wider range of fabrication processes utilized
• Use of three-dimensional structures
• Material properties are not fully characterized
• Interdisciplinary expertise necessary for successful technology implementation
• CAD tools are not yet fully developed for integrated thermal/mechanical, magnetic, optical, and
electronic design
In keeping with the general philosophy of this volume, I will emphasize the fundamental principles
and discuss CMOS-compatible processing methods. Selected examples of MEMS devices will be given
to illustrate some of the exciting applications of this technology. The reader is referred to the compre-
hensive survey by Göpel et al.9 and the vast diversity of micromachining and micromanufacturing
methods described in recent books by Kovacs,10 Madou,11 and Sze.12 In addition, reference materials
include a collection of classic papers by Trimmer,13 texts on sensors by Middlehoek and Audet,14 Ristic,15
Gardener,16 and bio and chemical sensors texts by Janata,17 Madou and Morrison,18 Moseley et al.,19 and
Wilson et al.20
Subtractive processes
Bulk micromachining µm-cm/1:400 Single-crystal silicon, GaAs glass Dopant-selective electrochemical High Low 9–11, 27–49
etching Buried layer
Reactive ion etch µm-mm/1:100 Wide range of materials Buried layer Low High 62–64
Laser ablation 1-100 µm/1:50 Various Timed Low High 22
Electrodischarge machining 2 µm-mm/* Si, metals Timed Low Med 25
Precision mechanical cutting nm-cm/* PMMA Tool position Low High 23
Focussed ion beam machining nm-µm Various Timed Low High 24
Chemical etching µm/1:10 Metals, semiconductors, insulators Timed High Low 21,26,50
Ultrasonic machining 25 µm-mm/* Glass, ceramic, semiconductor, metals Tool position Moderate Moderate —
Additive processes
Physical vapor deposition Wide range of Electron beam or thermal — Moderate High 26
materials evaporation/sputtering
Chemical vapor deposition Surface LPCVD of polysilicon/PSG or Selectivity of sacrificial etch to High Moderate 67–71,
micromachining sputtered aluminum/photoresist sacrificial layer to structural layer
Laser-assisted CVD nm-µm Various — Low High —
Molecular beam epitaxy nm Semiconductors — Low Very High —
LIGA µm-cm PMMA — Low High 51,101
Electroplating into a mold: µm-mm Cu, Ag, Au, Fe, permalloy — High Low
µm-mm/1:10 Polyimide — High Moderate 96,98–100
µm-mm SU-8 — High Low 97
µm-mm Thick photoresist — High Low —
10-3
10-4 VLSI Technology
(a)
(b)
FIGURE 10.1(a-b) (a) Diamond lattice of silicon with principal axis indicated; (b) schematic cross-section of bulk
micromachining processing steps to form a cavity in a (100) silicon wafer.
Examples of commonly used formulations are given in Table 10.2. This process has been extremely
successful for the fabrication of diaphragms for pressure sensors and other devices, aligning the [110]
flat of a (100) wafer to a mask opening a rectangular opening which are produced. Etching into the
bulk of the silicon crystal the dimensions of the resulting structure are defined by the slow etching
{111} planes (see Fig. 10.1c), which are parallel and perpendicular to the [011] flat on a (100) silicon
wafer. Alternatively, on a (110) silicon wafer, a slot is produced, as shown in Fig. 10.1(d). Note here
that the shape is bounded by the {111} crystal planes in the vertical direction and the {100} planes or
{311} planes at the base of the groove. There is insufficient space here to describe the mechanism of
etch chemistry, and the reader is referred to the work of Seidel,28 Kendall,29 Palik et al.,30 Hesketh et
al.,31 and Allongue et al.,32 the recent review given by Kovacs et al.,33 and a recent workshop of Wet
Chemical Etching of Silicon.34
KOH is perhaps the most widely used bulk micromachining wet chemical etchant, although it is a
strong ionic contaminant to the CMOS process. Despite these difficulties, it has been demonstrated
in post- and pre-processing formalisms with stringent chemical cleaning. The etch has been charac-
terized extensively.35–37 Table 10.2 lists the plane selectivity of useful concentrations that in addition
to the surface roughness are a function of the solution composition. However, roughness appears to
be related to hydrogen bubble release from the surface, and work by Bressers et al.38 has demonstrated
Micromachining 10-5
(c)
(d)
FIGURE 10.1(c-d) (c) Electron micrograph of a cavity etched in (100) silicon wafer, dimensional marker is 100 µm;
(d) slots etched in (110) silicon wafer, dimensional marker is 10 µm.
that the addition of ferricyanide ions reduces hillock formation. Note that selectivity to oxide masking
layers is not as high as CsOH and TMAH. Alcohol can be added to the etch to improve the surface
finish and uniformity.39
CsOH etchant has been characterized,40–42 and the results are summarized in Table 10.2. It has high
selectivity to silicon dioxide and is dopant selective, producing smooth membranes at high concentrations.
Surface roughness is often a key parameter in device design and is of key importance for technologically
useful etches to obtain controlled surface conditions.
EDP has been demonstrated as compatible with CMOS processing. It has high selectivity to dielectric
and metallization layers and contains no ionic contaminants. Etch has been characterized by Reisman et
al.43 and Finne and Klein.44 The popular formulations are as follows: Type-S is 1000 ml ethylenediamine,
160 g pyrocatechol, 133 ml water, and 6 g pyrazine; Type-F is 1000 ml ethylenediamine, 320 g pyrocat-
echol, 320 ml water, and 6 g pyrazine. These solutions etch thermal oxide at about 55 Å/h at 115°C, there
is no detectable attack of LPCVD silicon nitride, and the following metals — Au, Cr, Ag, and Cu — are
resistant to EDP. The plane selectivity is listed in Table 10.2.
10-6
TABLE 10.2 Bulk Etching Solutions for Silicon
Isotropic etches
HNA 250 ml HF/ 20 4–20 — — — — 50
500 ml HNO3/ [function of
800ml CH3COOH stirring]
Anisotropic etches
KOH 45 85 55 ~1.5 200 300 40,000 Au Yes Not CMOS 27–34,
compatible, 36–38
inexpensive,
safe, widely used
KOH/isopropyl 26/4 80 66 ~0.6 ~200 High Very high Au >10 × 1020/cm3 Not CMOS 39
alcohol decreases rate compatible,
by 20 inexpensive,
safe, widely used
CsOH 50 70 19 0.2–2.5b 50 2000 Very high Au Yes Expensive 40–42
material, good
selectivity with
SiO2
Ethylenediamine/ 255cc/ 45grm/ 100 66 <1 35 3500 Very high Au, Cu, Cr, >7 × 1019/cm3 Carcinogenic, 43–44
pyrocatechol/water 120cc Ag, Ta, Ni decreases rate widely used, low
by 50 anisotropy
TMAH 4 80 54 — 25 5000 Very high Al [Si Yes Flammable, low 45–47,
20 doping of anisotropy 49
solution]
(a)
(b)
FIGURE 10.2 (a) Schematic diagram of isotropic etching, indicating undercut of mask and definition of isotropy;
(b) effect of isotropic etching on grooves sawed into silicon wafer. The etching has rounded the tops of the grooves.
(Kasapbasioglu, H. et al., J. Electrochem. Soc., 140, 2319, 1993. With permission.)
10-8 VLSI Technology
TMAH has been studied extensively due to its low ionic contamination with CMOS. The early work
on etch characterization was carried out by Tabata.45 Characteristics are listed in Table 10.2 and the plane
selectivity is markedly lower than KOH; however, selectivity to SiO2 is quite high. The solution also
passivates aluminum surfaces when the pH is adjusted into a suitable range.46 This makes it a strong
candidate for CMOS post-processing; however, the etch rate is reduced with silicon doping and there are
unresolved issues regarding the solution stability. Ammonium persulphonate was added to the TMAH
bath to reduce surface roughness by limiting the formation of hydrogen bubbles, specifically for a 5 wt
% solution, 40 g/l silicic acid, and 5 to 10 g/l ammonium persulphate.47 Changes in the surface mor-
phology and high index plane selectivity are observed with the addition of alcohol48 and hillock formation
has been studied.49
Isotropic etching in a mixture of hydrofluoric acid (HF) and nitric acid (HNO3) produces typically
rounded profiles.50 Figure 10.2 shows a schematic diagram of the profile produced during isotropic
etching. The etching takes place in a two-step process, the first being oxidation of the silicon by the
HNO3, and the second being dissolution of the oxidized layer into a soluble H2SiF6 silicate. These two
processes have different reaction rates and, hence, polishing occurs at low concentrations of HF where
it defines the rate-limiting step in the reaction. The etchant can be stabilized by the addition of acetic
acid, which helps prevent the dissociation of the nitric acid into NO3– and NO2–. The etch is dopant
selective, having a lower etch rate for a lightly doped region (<1017/cm3) of silicon relative to heavier
doping regions.21 Figure 10.2(b) shows the application of this etching mixture to the rounding of pins
that have been produced by mechanical sawing of the silicon.
(a)
(b)
FIGURE 10.3 (a) Schematic diagram of a heavily doped layer diaphragm formation; (b) etch stop of heavily doped silicon
for KOH and EDP anisotropic etching solutions. (Collins, S. D., J. Electrochem. Soc., 144, 2242, 1997. With permission.)
(a)
(b)
FIGURE 10.4 (a) Typical experimental set-up for electrochemical etch stop method for formation of thin silicon
diaphragms (SCE is the Standard Calomel Electrode); (b) current–voltage characteristics of the p-type (solid line)
and n-type (dashed line) silicon in 40 wt. % KOH solution at 60°C, where OCP is the open circuit potential and PP
passivation potential. (Kloeck, B. et al., IEEE Trans. Electron. Dev., 36, 663, 1989. With permission.)
illumination level. The anodic current is a direct measure of the dissolution rate and, by defining an
optically opaque insoluble mask on the silicon surface, high aspect ratio structures have been defined
in the surface. Porous silicon is under investigation as a MEMS material as discussed by Schöning et
al.57 for its extremely high surface area.
RIE Etching
Dry etching offers the advantages of controlled dimensions independent of the crystal planes in the
substrate, in addition to higher dimensional control to sub-micron over wet chemical methods. The
process utilized either a dc, RF, microwave, or inductively coupled energy to excite a plasma of reactive
ions and accelerate them to the substrate. Depending on the ion acceleration potential utilized and
the gas pressure, there are very different process characteristics. Figure 10.5 shows the different
processes of (a) sputtering by physical bombardment of the surface, (b) chemical etching which is
isotropic, and (c) reactive ion etching in which the ion bombardment enhances the chemical etching
rate. This ion-assisted mechanism provides anisotropy, which is useful technologically for the fabri-
cation of high aspect ratio structures. Ion milling represents the processes at high potentials where
sputtering is dominant and at the other extreme at low substrate bias plasma etching where chemistry
plays the dominant role. The reader is referred to excellent texts on dry etching equipment and
processing methods.62,63 Key factors in the design of dry etching processes for films are the selectivity
with respect to the masking layer and with respect to the substrate material. The etch rate, uniformity,
and anisotropy are other key process parameters.
FIGURE 10.5 (a) Sputtering, (b) plasma etching, and (c) reactive ion etching.
10-12 VLSI Technology
Deep-RIE Etching
Deep-RIE etching was developed by the application of a novel etch chemistry and high-density plasmas
created by either microwave or inductively coupled sources. Mixed gas chemistries can be utilized to
provide sidewall passivation and further increase the anisotropy of the process. Selectivities with respect
to a photoresist mask of 200:1 can be reached, allowing one to etch completely through a silicon wafer.
Bhardwaj et al.64 have demonstrated deep reactive ion etching by alternating between deposition of a
passivating film and etch chemistry. The surface is coated with a Teflon-like material and the material
remains on the sidewalls; however, ion bombardment removes it from the horizontal surfaces. Typically,
a low bias voltage is utilized so that the mask erosion rate is minimized. An example of grooves etched
with this process is given in Fig. 10.6.
Corner Compensation
Corner compensation of the bulk etched structure is important to maintain the shape of a microma-
chined structure. For example, microchambers for DNA sequencing by hybridization have been fab-
ricated with corner compensation structures oriented in the [110] direction.65 A great deal of work
has examined the compensation of exposed corners for etching in KOH solutions under different
conditions.66 The shape of the compensation structure is shown in Fig. 10.7. There are several com-
mercially available CAD tools for silicon bulk etching. Figure 10.7(c) is an example of a etched cantilever
in CsOH solution. The CAD simulation shows the faceting high-index planes and the general features
of the structure.
(a)
(b)
FIGURE 10.6 (a) Method of side-wall passivation during RIE etching; (b) slot produced by deep RIE etching process.
(Bhardwaj, J. et al. in Microstructures and Microfabricated Systems-III, Proceedings of the Electrochemical Society, 97-
5, 118, 1997. With permission.)
Micromachining 10-13
(a)
(b)
FIGURE 10.7(a-b) (a) Exposed corner etched in 50 wt% CsOH for 4 hours; (b) corner compensation structure 20-
µm wide after etching for 3 hours in 49 wt% KOH.
10-14 VLSI Technology
(c)
(d)
FIGURE 10.7(c-d) (c) Etched cantilever beams in silicon dioxide by etching in CsOH solution; (d) example of CAD
simulation of etched cantilever structures in silicon. (Shih, B. et al., submitted to J. Electrochem Soc., 1998. With
permission.)
Micromachining 10-15
FIGURE 10.8 Cross-sectional diagram of processing steps in the surface micromachining process. (Courtesy of Tong,
W. C. et al., Sensors and Actuators, 20, 25, 1989. With permission.)
10-16 VLSI Technology
tensile stress film with a small stress gradient through the film.70 Polysilicon is an extremely stable
and good-quality material for producing micromechanical elements, as demonstrated by the success
of these devices (examples are given in the next section). Sealing of surface micromachined structures
has been developed for absolute pressure sensors by reactive sealing of small openings in the surface
or by dry deposition of another layer of material like silicon nitride.71 Surface micromachining is not
limited to poly-Si and PSG. A wide range of material combinations have been studied.15 Machining
with aluminum as the structural layer and a photoresist as the sacrificial layer is discussed by West-
erberg et al.72
Stiction
Stiction in surface micromachined structures is an issue that must be addressed due to the very small
gaps present between surfaces. Tas et al.73 investigated the origins of stiction in surface micromachined
devices and found that roughness plays an important role. The critical dimensions for the mechanical
force to snap back a cantilever beam against the stiction force was investigated. The energy of adhesion
by liquid bridging found that if the tip touches the substrate, the surface energy plus the deformation
energy has a minimum for a detachment length smaller than the beam length. Stiction can occur
during processing or during device operation. Various methods have been developed to avoid stiction
during processing. Carbon dioxide drying is used because, below the critical temperature of the
supercritical carbon dioxide, no liquid vapor interface exists that could cause contact. During device
operation, the fail-safe requires that these surfaces do not make contact or an adequate release force
can be applied. Surface energy is only partially successful in modifying these interactions and it is
important to limit the contact area. Specifically, dimples, bumps, sidewall spacers, or increased surface
roughness can define smaller contact areas.
Silicon Nitride
Stoichiometric silicon nitride has high tensile stress and this limits the maximum film thickness that can
be fabricated on a wafer.81 Stress relaxation occurs in silicon-rich nitride as a function of the film
stoichiometry and has been characterized by Gardemoers et al.,82 Chu et al.,83 French et al.,84 and
Habermehl.85 Figure 10.10(a) shows the intrinsic stress as a function of deposition conditions for silicon-
rich nitride growth at several different temperatures and pressures and Fig. 10.10(b) for PECVD mate-
rial.86 Other materials have been studied, including SiC87 and diamond-like carbon.88
Micromachining
TABLE 10.4 Materials Properties of LPCVD Deposited MEMS Materials
Material Growth Conditions Film Thickness Property Value Comments Ref.
Polysilicon
MUMPS process 3 µm Young’s modulus 169±6.15 GPa — 77
Tensile strength 1.20±0.15 GPa
Thick polysilicon 1100°C, SiH4/B2H6 or 610°C, 2.5-10 µm Young’s modulus 150±3- GPa 2.3±0.1 Undoped film 78
Sitty Fracture toughness MPa √m 280 MPa
Thin polysilicon 565°C, SiH4, 620°C, SiH4, 1 µm As-deposited residual stress
100 mTorr
CMOS 0.33 µm Young’s modulus 168±7 GPa 2.11±0.10 — 80
Tensile strength GPa
Young’s modulus 162.8±6 GPa — 79
Intrinsic stress –350±12 GPa As deposited
Intrinsicties 162.8±6 GPa After 1000°C anneal
Silicon Nitride
Standard process 800°C, SiCl2H2lNH3 — Intrinsic stress ~1.2 GPa 81
Si-rich, variable 800, 850°C 200, 410 mTorr ~0.1 µm Intrinsic stress (See Figure 10.10) — 82–84
stoichiometry SiCl2H2/ NH3
Silicon-rich, variable 850°C 200 mTorr 0.25–0.45 µm Young’s modulus 85
stoichiometry SiCl2H2/NH3
PECVD (190 GPa)
10-17
10-18 VLSI Technology
(a)
(b)
FIGURE 10.9 (a) Stress in fine-grained polysilicon as a function of post-deposition annealing temperature and time
(Guckel, H. et al., Sensors and Actuators A, 21, 346, 1990. With permission); (b) biaxial stress for polysilicon fabricated
in the MUMPS process. (Sharpe, W. N. et al., in Proceedings of the Tenth Annual Internations Workshop on Micro
Electro Mechanical Systems, Nagoya, Japan, January, 1997, IEEE, New Jersey, Catalog Number 97CH36021, 424. With
permission.)
Micromachining 10-19
(a)
(b)
FIGURE 10.10 (a) The effect of deposition parameters on the residual stress of LPCVD deposited silicon rich
silicon nitride where R is the ratio of dichlorosilone to ammonia gas flow (Gardeniers, J. G. E. et al., J. Vac. Sci. Tech.
A., 14, 2879, 1996. With permission.); (b) intrinsic stress of PECVD Si3N4 as a function of processing conditions.
(Classen, W. A. P. et al., J. Electrochem. Soc., 132, 893, 1985. With permission.)
10-20 VLSI Technology
(a) (b)
FIGURE 10.11 (a-b) SEM micrographs of devices fabricated by the SUMMIT process: (a) gears; (b) linear spring.
(c) (d)
FIGURE 10.11 (c-d) (c) Mechanism; (d) hook. (Courtesy of Sandia National Laboratories’ Intelligent Micromachine
Initiative; www.mdl.sandia.gov/Micromachine. With permission.)
Micromachining 10-21
FIGURE 10.12 Schematic diagram of processing steps in the SUMMIT process for polysilicon MEMS. (Courtesy
of Sandia National Laboratories’ Intelligent Micromachine Initiative; www.mdl.sandia.gov/Micromachine. With
permission.)
10-22 VLSI Technology
SCREAM processing utilizes the advantages of the properties of single-crystal silicon for producing a
wide range of elegant devices.93 This method was derived from a process to make isolated islands of
submicron silicon by local oxidation. Suspended high aspect ratio structures are fabricated by SF6 RIE
step, followed by sidewall oxidation and isotropic silicon etch to undercut the structure (see Fig. 10.13).
Both suspended structures and structures with metallized sides for electrostatic drives can be realized by
varying the width of the structure and processes, each with high out-of-plane stiffness, as defined by the
ratio of beam height to length, [h3/l3]. Examples of devices realized by this elegant process include tip-
on-tip sensors, microaccelerometers, electrostatic drives, torsional actuators, microloading machines, and
STM tips with integrated drive. In addition, beams filled with spin on glass isolation have been demon-
strated with high thermal isolation. The planarity of large aspect ratio structures has been investigated
by Saif and MacDonald.94
HEXSIL is an RIE-etched channel and fill process that utilizes polishing for planarization.95 The trench
controls the material that fills the grooves defined by RIE process. After the groove is coated with an
oxide layer, the body of the device is made from undoped polysilicon, followed by a doped layer, and
finally, Ni is electrolytically deposited into grooves to define highly conducting regions (see Fig. 10.14
for a process overview). The different groove width provide discrimination between different materials;
hence, three types of material combinations are defined. Once the sacrificial oxide is removed, the HEXIL
structure is released, micro-tweezers, and other structures have been defined by this method, as shown
in Fig. 10.14(b).
LIGA Process
LIGA is an acronym from the German Lithographie, Galvanoformung, und Abformung, denoting the
use of X-ray lithography from a synchrotron source, in thick PMMA layers to define structures with very
high aspect ratios, followed by nickel electroplating, and subsequent replication by injection molding.101
Because LIGA is based on X-ray radiation, it is not compatible with CMOS processing. The intensity of
the X-rays produces damage in the dielectric components of the CMOS circuit. An excellent review of
recent development in LIGA processing is given by Friedrich et al.51 Optical gratings have been made by
the LIGA process by Cox et al.;102 specifically, infrared tunable filters driven by magnetic actuators, features
30 µm in height, and a filter period of 8 to 17 µm. (See Fig. 10.17.)
Micromachining 10-23
FIGURE 10.13 Cross-sectional diagram of the SCREAM process for the formation of silicon cantilevers with
aluminum electrodes adjacent to each side of the beam. The undercut of the silicon sidewalls isolate the aluminum
from the substrate. (McDonald, N. C., Microelectronic Engineering, 32, 49, 1996. With permission.)
GaAs Micromachining
The properties of GaAs as a MEMS material have been investigated by Hjort et al.103 The key advantages
of GaAs are that it is a direct-bandgap semiconductor also having high electron mobility, so that opto-
electronic devices can be realized, and the piezoelectric properties are comparable to that of quartz.
Finally, electronic devices can be operated at temperatures up to 350°C. Although the mechanical strength
of the material is lower than silicon, the material can be bulk micromachined with HNO3/HF solutions.
Surface-type micromachining processes have also been developed, based on the advanced state-of-the-
10-24 VLSI Technology
(a)
(b)
FIGURE 10.14 (a) Cross-sectional schematic of the HEXIL process; (b) micro-tweezers produced by the HEXIL
process. (Keller, C., Microfabricated High Aspect Ratio Silicon Flexures, ISBN 0-9666376-0-7. With permission.)
Micromachining 10-25
FIGURE 10.15 Schematic representation of the process sequence for fabricating metallic electroplated microstruc-
tures using photosensitive polyimide. (Frazier, A. B. et al., Sensors and Actuators A., 45, 47, 1994. With permission.)
art in modulated material doping and selective etching of AlGaAs. Interdigitated electrostatic actuators
have been realized in addition to surface acoustic wave sensors (SAW) optical sensors, and piezoelectric
sensors (see later section on optical devices).
FIGURE 10.16 SEM photomicrograph of a high aspect ratio 100-micron thick SU-8 photoresist structure formed
by a single spin coating and contact lithography exposure. (Photo courtesy of Electronic Visions, Phoenix, Arizona.
With permission.)
FIGURE 10.17 Schematic diagram of the LIGA process modified for MEMS.
Micromachining 10-27
There have been several approaches for combining CMOS circuits with MEMS structures, summarized
as follows:
• Post-processing: protecting the CMOS circuit with a chemically resistant film(s) and carrying out
the micromachining after the circuits are complete and avoiding any high-temperature steps.
• Combined processing: integration in a custom MEMS/CMOS process or utilizing the CMOS layers
themselves for MEMS devices.
• Pre-processing: etching wells in the wafer of a depth equal to the total height for the formation
of the MEMS device. Fabrication of MEMS devices and protection with an encapsulation layer
that is planar with the silicon surface. CMOS circuit fabrication then follows, and removal of the
encapsulating film releases the MEMS structure.
Post-Processing
Micromachined thermally isolated regions have been developed by Parameswaran et al.106 in a CMOS-
compatible process for infrared emitter arrays. Post-processing was carried out following a commercial
Northern Telecom Canada Ltd. COMS3 DLM (3-µm 13 mask) process. Openings are defined in layers
so that the silicon surface is exposed for the EDP etching. The active devices, both p-MOS and n-MOS,
were tested after etching and there was no change in device performance.
Fedder et al.107 have demonstrated the fabrication of intricate structures with a standard CMOS process.
Structures are designed in the metal and polysilicon layers and aligned so that a post-processing dry etch
step defines the dimensions and a post-processing etch undercuts the structure. Releasing it from the
substrate is carried out by RIE etching (see Fig. 10.18). Electrostatic comb drives actuate microstructures
that are 107 µm wide and 109 µm long show a resonance amplitude of 1 µm with an ac drive voltage
of 11 V. The effective Young’s modulus of the structure was found to be 63 GPa. The design rules are as
follows. The scaling factor for the 0.8-µm process is λ = 0.4 µm. The minimum beam width is 3λ (1.2
µm), and the minimum gap is 3λ (1.2 µm); however, for holes, a minimum dimension of 4 µm is required
for release. The CMOS circuit is protected by metal-3 to prevent etching. The metal-1 and -2 collar is
inserted underneath the break in metal-3 to prevent the etch from reaching the surface and facilitating
electrical interconnects to the MEMS structure.
FIGURE 10.18 Example of the use of variable anisotropy dry etch on prefabricated CMOS integrated circuit using
the upper level of metallization as the mask: (1) CMOS cross-section, (2) anisotropic CHF3/O2 RIE process, (3)
anisotropic SF6/O2 RIE process, and (4) isotropic SF6/O2 RIE process. (Fedder, G. K. et al., in Proceedings of the
International Meeting on MicroElectroMechanical Systems, IEEE, p. 13, 1996. With permission.)
10-28 VLSI Technology
Finally, planarization techniques have been developed by Lee et al.108 to prepare a foundry-fabricated
chip for post-processing by other low-temperature methods, including electroforming, LIGA, and reactive
ion etching.
Mixed Processing
The surface micromachined accelerometer manufactured at analog devices utilizes an integrated process.
The BiCMOS process is interleaved with the micromachining so that the higher-temperature steps are
completed first; then the lower temperature steps and metallization complete the device fabrication.
A different approach has been taken by the group at the University of California at Berkeley, using
high-temperature metallization of tungsten and titanium silicide and TiN barrier layers to replace the
aluminum.109 A double polysilicon single metal, n-well CMOS technology is fabricated first, encapsulated
with PSG and low-stress nitride, as shown schematically in Fig. 10.19.
(a)
(b)
FIGURE 10.19 (a) Schematic cross-section of the modular integration of CMOS and microstructures technology
using post-IC MEMS fabrication with tungsten interconnect technology; (b) a cross-sectional schematic of the
subsurface, embedded MEMS integrated technology. (Sniegowski, J. J., in Microstructures and Microfabricated Systems-
IV, Vol. 98-14, Ed: P.J. Hesketh, H. Hughes, and W. E. Bailey, The Electrochemical Society, Pennington, New Jersey,
1998. With permission.)
Micromachining 10-29
Pre-Processing
Smith et al.110 pioneered the pre-processing of fabricating the MEMS device in a buried well and then
encapsulation with a protective passivation film, which is later be removed once the CMOS process is
complete. The key to this process is the use of CMP to planarize the surface after MEMS device fabrication
and before the CMOS fabrication is begun. The release etch must be highly selective to materials in the
MEMS structure and not damage the CMOS outer layers of material (see Fig. 10.19). This process has
been very successful in fabricating structures such as pressure sensors, electronic oscillators, microaccel-
erometers, and gyroscopes. Also, Gianchandani et al.111 have demonstrated pre-processing integration of
thick polysilicon microstructures with a CMOS process. Silicon-to-silicon bonding has been utilized for
sensor integration with a pre-etched sealed cavity process,112 shown in Fig. 10.19(c). The thin membrane
formed undergoes plastic deformation, and as a result, the proper design of the cavity geometry is critical
to control the gas pressures during bonding. Pressure sensors, accelerometers, and gas flow shear stress
sensors have been demonstrated with and without integrated electronics. Lowering the bonding temper-
ature is of key interest to allow more widespread use of this bonding method — because of its incom-
patibility with many materials and processes.
under investigation.116 The circuit is protected from the large electrostatic fields by shorting the gate
regions together with a polysilicon strip. After bonding, regions were opened up in this area to facilitate
etching. In addition, cavities were drilled ultrasonically in the Pyrex wafer to reduce the electric field
over the active circuits.
The key advantage of silicon-silicon direct bonding is that the same material is used so there are
minimal thermal stresses after bonding. The wafers must be flat, scrupulously clean, and in prime
condition to achieve a reliable bond. First, the wafers are chemically cleaned and surface-activated in a
nitric acid solution. Then the wafers are bonded at room temperature in a special jig that has been
demonstrated to improve the bonding yield, as shown in Fig. 10.21.117 A subsequent anneal step increases
the bonding strength through a chemical reaction that grows a very thin silicon dioxide layer at the
interface (Fig. 10.21(b)). The wafers can be inspected for voids utilizing an infrared microscope or an
ultrasonic microscope. High yield has been achieved and the community that developed silicon-on-
insulator technology have published conference proceedings on these methods.118
Other bonding methods are listed in Table 10.5; these include eutectic,119 low-temperature glass,120
glass frit,121 and borosilicate glass.122 Materials are selected to minimize the stresses in the bond by selecting
a match in the thermal expansion coefficients, or a compliant layer is utilized at the interface.
Components
In the first generation of microfabricated optical components, hybrid assembly into optical devices was
carried out rather than integrated functionality. Various optical components were reviewed by Motamedi
et al.,125 including diffractive optical components integrated with infrared detectors, refractive micro-optics,
and microlenses. However, the integration of optical components into a micro-optical bench offers several
advantages over guided wave approaches; in particular, high spatial bandwidth, independent optical routing
3-D interconnects, and optical signal processing. Moving the individual optical elements out of the plane
has greatly expanded the utility of this method.126 Micro-electrostatic deformable mirrors have also been
demonstrated as an effective method for reducing aberrations.127
Tunable semiconductor laser diodes have been demonstrated by Uenishi et al.128 with anisotropically
etched (110) silicon substrates and hybrid assembly. A cantilever 1.7 mm long and 8 µm wide defines a
(111) surface reflecting mirror normal to the substrate provided modulation from 856 to 853 nm, with
a drive of 12.5 V. The etching conditions in KOH solutions were optimized for minimum surface
roughness of the (111) surface.
External mirrors for edge emitting lasers can also be produced in GaAs by micromachining. Larson
et al.129 have demonstrated a Fabry-Perot mirror interferometer by combining a GaAs-AlAs vertical cavity
laser VCSEL with a suspended movable top mirror membrane. The bottom mirror is a 12.5 period
GaAs/AlAs distributed Bragg reflector of 640 Å/775 Å thickness with a center wavelength of 920 nm. The
GaAs laser had a center wavelength of 950 nm and a cavity of 2580 Å thick GaAs layer. The top electrode
was 2230 Å SiNxHy with a nominal 200-Å Au reflector. The air gap thickness is modulated around 3λ/4
with electrostatic means to provide a 40-nm tuning range with an 18-V drive. Figure 10.22(b) shows the
reflectance spectra from the device. Fabry-Perot tuning was also applied to a photodiode detector by Wu
et al.123 A DBR mirror is defined on top of a movable cantilever. A 30-nm tuning range was achieved
Micromachining 10-31
(a)
(b)
FIGURE 10.20 (a) Schematic diagram showing anodic bonding process and potential distribution; (b) thermal
expansion coefficient of Si and Pyrex glass as a function of temperature. (Peeters, E., Process Development for 3D
Silicon Microstructures with Application to Mechanical Sensors Design, Ph.D. thesis, Catholic University of Louvain,
Belgium, 1994. With permission.)
10-32 VLSI Technology
(a)
(b)
(c)
FIGURE 10.21 (a) Schematic diagram of set-up for direct silicon-to-silicon wafer bonding process (Cha, G. et al.,
in Proc. First Int. Symp. Semicond. Wafer Bonding Sci. Tech. Appl., Eds., Gösele, U. et al., The Electromechanical Society,
Pennington, NJ, p. 249, 1992 and Masgara, W. P. et al., J. Appl. Phys., 64, 4943, 1989. With permission.); (b) bond
strength versus anneal temperature for silicon-silicon direct bond (Mitani, K. and Gösele, U.M., J. Electron. Mat.,
21, 669, 1992. With permission.); (c) method for formation of silicon diaphragm by silicon to silicon bonding.
(Parameswaran, L. et al., in Meeting Abstracts of the 194th Meeting of the Electrochemical Society, Boston, Nov. 1-6th,
Abst #1144, 1998. With permission.)
Micromachining 10-33
(a)
(b)
FIGURE 10.22 (a) Schematic diagram of coupled-cavity microinterferometer; (b) membrane voltage and reflected
photocurrent traces for the device acting as an intensity modulator for an active wavelength of 933 nm. (Larson, M.
C. et al., IEEE Phot. Tech. Lett., 7, 382, 1995. With permission.)
with a 7-V drive and 17-dB extinction ratio. The DBR comprised a top reflector of 18 pairs n-doped
Al0.6Ga0.4As-Al0.1Ga0.9 As and a fixed portion was two pairs p+-doped Al0.6Ga0.4As-Al0.1Ga0.9As. The bottom
DBR was 13 pairs of n-doped AlAs-GaAs mirror grown onto an n+-doped GaAs substrate.
FIGURE 10.23 Schematic representation of variable diffraction grating. The value of γ will depend on the position
of the upper, poly-2 grating and the three positions span a full period as indicated by the solid lines, for the following
values of γ: (a) γ = 0, (b) γ = 2 µm, and (c) γ = 4 µm. (Sene, D. E. et al., in Proceedings of the Ninth Annual International
Workshop on Micro Electro Mechanical Systems, San Diego, CA, February 1996, 222. With permission.)
There are also 0.75-µm deep dimples in the upper electrode to prevent stiction. Thermally actuated
beams are used to assemble these structures (see Section 10.9).
Burns and Bright132 have developed microelectromechanical variable blaze gratings operated by adjust-
ing the blaze angle of each slat so that specular reflection of the incident light matches a particular grating
diffraction order. Figure 10.24 shows a grating element that was fabricated with polysilicon using the
MUMPS process surface micromachining available at MCNC.45 Both electrostatic and thermal actuators
were studied. Light beams of diameters greater than 1 mm and power levels of 1 W have been directed.
Measurements with 20 mW HeNe (632.8 nm) produced diffraction efficiency in the far field of 55%,
which agreed with model results. Devices with gold metallization demonstrate improved reflectivity;
however, they are not fully compatible with CMOS processing.
Scanning Mirrors
Miller et al.133 fabricated a magnetically actuated scanner with a 30-turn coil on an 11-µm thick permalloy
layer. The external magnetic field provided deflection while the coil provided fine control and/or fast
motion. Asada et al.134 fabricated optical scanners with bulk micromachining and a magnetic drive. The
electroplated copper used photoresist mold with a period of 50 µm. Coils formed on the x-axis and y-
axis plate of the Pyrex glass plate. Spring constants were evaluated for the x- and y-axes at 6.48 × 10–4
Nm and 12.8 × 10–4 Nm, respectively, and resonant frequencies of 380 Hz and 1450 Hz, respectively.
Judy and Muller135 demonstrated a torsional mirror scanner moved with a magnetic field. They electro-
plated a nickel mirror 450-µm square on a polysilicon flexure over a 10-turn coil. With a current of 500
mA and field of ~5 kA/m, the mirror moved more than 45°. Micromachined electromagnetic scanning
mirrors have also been fabricated and demonstrated by Miller and Tai.136 One advantage of magnetic
actuators is that both attractive and repulsive forces can be generated. The mirrors are permalloy coated
(Ni90Fe10) and formed on a silicon substrate with a 20-µm thick epitaxial layer for etch stop. Copper coils
are electroplated into a photoresist mold. The mirror is shown schematically in Fig. 10.25(a), and the
deflection as a function of the external magnetic field in Fig. 10.25(b). Utilizing these mirrors, holographic
Micromachining 10-35
(a)
(b)
(c)
FIGURE 10.24 (a) Schematic diagram of reflective blazed grating illuminated at normal incidence; (b) cross-
sectional view of the slat support posts and flexure used in the electrostatically actuated variable blaze grating; (c)
the embossing present in the cross-section view of the gold layer. (Burns, D. B. and Bright, V. M., Sensors and Actuators
A, 64, 7, 1998. With permission.)
10-36 VLSI Technology
(a)
(b)
FIGURE 10.25 (a) Schematic diagram and cross-section of the deflected magnetic micromirror; (b) change in
deflection angle from bias position for a variable coil current with external field of 994 Oe. (Miller, R. and Tai, Y.-
C., Opt. Eng., 36, 1399, 1997. With permission.)
data storage has been demonstrated. Scanners are widely used in printers, display devices, graphic storage
systems, and bar code readers.
Kiang et al.137 have developed polysilicon hinged structures for scanners which utilized an electrostatic
drive. The 200 × 250-µm mirror was rotated 12° with a drive voltage of 20 V, and the device had a
resonant frequency of 3 kHz.
Fischer et al.138 have utilized electrostatic means for mirror deflection with integrated p-well CMOS
drive circuits. Two types of torsional mirrors, comprising a polysilicon layer with double-beam suspension
and a reflecting area of 75 × 41 µm2, have been realized. The mirrors were integrated by post-processing
a layer of polysilicon at 630°C, implanting with phosphorus, dose 5 × 1015/cm2, and annealing at 900°C,
resulting in a resistivity of 100 Ω/sq. The electronics included a demultiplexer circuit for addressing the
mirrors and a drive circuit producing 30 V for the electrostatic deflection. Bühler et al.139 have also
developed an electrostatically driven mirror made of aluminum in arrays for low-cost applications. The
CMOS-compatible process consisted of modifying the second metal layer deposited process into two
successive passes. The first, of 1.1 µm, established a thick metal layer for the mirror plate and the second,
of 0.3 µm, a thin metal layer for the hinges. Deposition was carried out by sputtering at 250°C for
Micromachining 10-37
FIGURE 10.26 Perspective view of the ZnO-driven cantilever array. (Huang, Y. et al., in Digest of Technical Papers,
Solid-State Sensor and Actuator Workshop, Hilton Head, South Carolina, June 1996, 191. With permission.)
improved step coverage; however, a roughness of ~53 nm resulted. Smooth reflecting surface room-
temperature depositions were preferred, resulting in roughness ~12.5 nm. The mirrors were released by
sacrificial aluminum and oxide etching. They were deflected with a drive voltage of 11 V for a pixel area
of 30 × 40 µm2.
Ikeda et al.140 fabricated a scanning system that had a two-dimensional array with integrated photo-
detectors and piezoresistors. A bulk piezoelectric actuator moves the silicon nitride bridges with a
torsional spring scanning angle of 40° and 30° bending and twisting and a resonant frequency of 577 Hz
in bending and 637 Hz in torsional motion.
Huang et al.141 have demonstrated piezoelectrically actuated ZnO cantilevers for application in pro-
jection displays, as shown in Fig. 10.26 One of the key advantages of piezoelectrically controlled motion
is that the displacement is linearly proportional to the applied voltage. Although sputtered ZnO films
have a lower piezoelectric coefficient than PZT, the fabrication process is compatible with CMOS
processing. Calculations show that for a beam length of 150 µm, the tip deflection is 0.06°/V or 0.12
µm/V. The ZnO is fabricated with a sacrificial spin-on-glass process, the upper and lower electrodes
formed from aluminum. The release step involves a HF vapor etch at low concentration to avoid attack
of the Al and ZnO thin film. Tip displacements were measured with a laser interferometer and, in order
to distinguish between any thermal contribution to the measured deflections, a drive waveform of
unbiased square wave was selected. The frequency response was over 80 Hz with a 1 µm air gap and
limited to about 10 Hz with a 0.5-µm air gap, indicating the dominance of squeeze film damping. The
thermal deflection was about 2 to 3 orders of magnitude less than the piezoelectric response.
Spectrometer on a Chip
Surface micromachining has been demonstrated by Lin et al.142 for out-of-plane assembly of optical
elements. The hinge mechanism allows the plate to be moved to a vertical position and locked into place
with a spring latch (see Fig. 10.27(a)). Micro-Fresnel lenses with a 280-µm diameter and an optical axis
254 µm above the plane of the silicon have been realized. The slide latch precisely defines the angle of
the element (see Fig. 10.27(b)). It has a ‘V’ shape 2 µm wide in the center. In addition, rotating structures
can be realized, such as a rotating mirror. Surface micromachined free space optical components have
been demonstrated by Lee et al.143 for the collimation and routing of optical beams. Microgratings with
5-µm pitch are fabricated on flip-up structures metallized with a thin layer of aluminum. A diffraction
pattern was imaged with a CCD camera and beams directed to a second grating into the zero-order
beam. Recent progress in micro-optical systems is reviewed by Bright et al.,144 including mirrors, Fresnel
lenses, gratings, and larger systems. All of these structures were fabricated by surface micromachining in
the MCMC processes145 using an electrostatically actuated gold surfaced mirror.
Micromechanical Displays
Miniature display systems have been commercialized by Texas Instruments in projection television
systems.146 They offer the advantage of cold operation and high contrast (>100:1) compared to the
10-38 VLSI Technology
(a)
(b)
FIGURE 10.27 (a) Schematic diagram of the three-dimensional micro-optics element. After release etch, the micro-
optical plate can be rotated out of the substrate plane and locked by the spring latches (Bright, V. M. et al., IEICE
Trans. Electron., E80-C, 206, 1997. With permission.); (b) SEM micrograph of the micro-Fresnel lens in the micro-
XYZ stage integrated with eight scratch drive actuators. (Lee, S. S. et al., Appl. Phys. Lett., 67, 2135, 1995. With
permission.)
Micromachining 10-39
FIGURE 10.28 A two digital micro-mirror device pixels mirrors are shown as transparent for clarity in the diagram.
(Hornbeck, L. J., in Symposium Micromachining and Microfabrication, Proceedings of SPIE, Vol. 2783, Austin, TX,
1996, 2. With permission.)
cathode-ray tube (CRT). A CMOS-like process over a CMOS memory element defined aluminum
mirrors, each 16 × 16 µm2 in area, that can reflect light in two directions. The hinges and support structure
are positioned under the reflector element. The display element can be moved by up to +/-10° and at
speeds up to 10 µs, which make them suitable for standard rate NTSC video. Figure 10.28 shows the
structure of one element in the 124 × 124 elements. The underlying memory cell operates on 5 V. Eight-
bit pulse width modulation of the mirror state produces a gray scale or color image. The fabrication
process is compatible with CMOS processing; however, to date, only the display has been fabricated on
chip, and hybrid packaging is used for the drive electronics.
Linear Microvibromotor
The linear microvibromotor is based on impact momentum to produce small displacements. Each impact
from the comb drive produces a step of typically 0.27 µm. Although this is an impulsive drive, the
standard deviation between steps is 0.17 µm. A maximum speed to 1 mm/s has been demonstrated and
used for a slide-tilt mirror and alignment of beams in a fiber coupler.151
Scratch Drive
The scratch drive is based on applying pulses to a plate and allowing the successive bending and release
to produce lateral motion of the bushing to move out.152 During release, the non-symmetric functional
forces produce an incremental motion DX. Microactuators and XYZ stages have been developed for a
micro-optical bench.153 A comb drive is used to drive the torsional z actuator with displacements up to
140 µm. Figure 10.29(b) is a schematic diagram of the microactuator stage. The lower 45° mirror is
moved to achieve lateral adjustment of the beam. The translation stages are defined in the first (poly-1)
layer, and the second (poly-2) layer defines the optical elements. The scratch drive actuator is particularly
suited for this application because of the high forces and small step size (~10 nm) at moderate drive
voltages of 87 V. Two-dimensional optical beam scanning has been demonstrated of several mm in the
far field at a distance of 14 cm utilizing a HeNe laser source. A micro-Fresnel lens has been integrated
into the actuator with eight scratch drive actuators
Thermal Actuator
Thermal actuator arrays for positioning surface micromachined elements have been demonstrated, as
well as automated assembly of polysilicon mirrors and other elements with thermal actuators.154–156 The
thermal actuator was designed for vertical and horizontal motions. The horizontal actuator is shown
schematically in Fig. 10.29(c). These structures were fabricated with MUMPS processes.145 It comprises
a hot and a cold arm of polysilicon. Initially, the components are on the surface of the substrate; however
when current is passed, one side becomes hotter than the other. The deflection of up to 16 µm is produced
at moderate power levels of 16 mW and forces of 7 µN. In a second mode of operation if the actuator
is heated above that for maximum deflection the hot arm becomes shorter than before and a negative
deflection results with power off condition (see Fig. 10.29). The vertical actuator consists of two poly-
silicon beams separated by a 0.75-µm air gap. The lower arm is wider than the top one. When current
is applied, the upper arm becomes hotter, providing higher electrical and higher thermal resistance, and
thus a higher temperature driving the arm downward toward the substrate. Back-bending of the vertical
actuator is particularly useful for clamping components in automatic assembly operations without the
continuous application of current. These actuators are suitable for forming arrays of devices; designs of
Micromachining 10-41
linear motors have been described. A self-engaging locking mechanism is also described which takes
advantage of a tether from the upper polysilicon layer interacting with a key hole on a movable plate.
When the movable plate is rotated out of the plane of the wafer, the tether slides into the wide section
of the opening, which is wider than the tether. For example, the assembly of a polysilicon mirror 104 ×
108 µm is achieved with two vertical actuators and a linear motor. Bending of the actuators is achieved
with current levels of 4.2 mA at a voltage of ~14 V and the linear motor is operated with 24 mA at 5.5 V.156
10.10 Electronics
For electronic applications of MEMS, the compatibility of the micromachining processes with IC pro-
cessing is key for integration with active electronic components. There has been considerable work on
fabrication of passive components by micromachining, specifically capacitors, inductors, and microwave
transmission lines, and other components. The key advantages for passive component integration are
ease of manufacturability for the higher frequency range of 100 to 1000 GHz where characteristic
dimensions are mm to sub-mm range compatible with.micromachining. This offers the opportunity to
fabricate components and packaging in an integrated approach. Applications include test instruments,
communications systems, radar, and others.
FIGURE 10.29(a) Electron micrograph of an interdigitated electrostatic drive. (Courtesy of Sandia National Labo-
ratories’ Intelligent Micromachine Initiative; www.mdl.sandia.gov/Micromachine. With permission.)
10-42 VLSI Technology
FIGURE 10.29(b-c) (b) Scratch drive actuator. (Fukuta, Y. et al., in Proceedings of the 10th Annual International
Workshop on Micro Electro Mechanical Systems, Nagoya, Japan, IEEE, New Jersey, 1997, 477. With permission.); (c)
schematic diagram of the lateral thermal actuator. Typical dimensions are given in the text. (Comtois, J. H. and
Bright, V. M., in Digest of Technical Papers, Solid-State Sensor and Actuator Workshop, Hilton Head, South Carolina,
June 1996, 152. With permission.)
Micromachining
TABLE 10.6 Microrelays
Contact Off- Resistance/ Switching Insertion
Application Fabrication Process Drive On-Resistance Maximum Current Breakdown voltage Time Loss Ref.
Electrostatic
Automated test Bulk micromachining and <100 V <3 Ω — — <20 µs 172
equipment anodic bonding
Thermal
Switching MUMPS 7-12 V 2.4 Ω 80 mA — — — 178
Magnetic
Electrical control Polyimide mold and 180 mA 0.022 Ω 1.2 A — 0.5-2.5 ms — 179
circuits electroplated metals (33 mW)
10-43
10-44 VLSI Technology
Microwave Waveguides
Rectangular waveguides have been fabricated by McGrath et al.161 by a bulk micromachining process and
characterized over the frequency range 75 to 110 GHz. Slots are formed in a (110) silicon wafer, which
were subsequently coated with 250 Å Cr and 5000 Å Au to form a plating base for a further 3 µm of
electroplated Au. Losses measured in a 2.5-cm guide were comparable to commercial waveguides at about
0.024 dB/m. Active and passive components could be integrated into these structures.
Circuit components have also been fabricated by bulk micromachining with the added advantage of
an integrated package by Franklin-Drayton et al.162,163 and Katehi et al.164 A series open-end tuning stub
and a stepped impedance low-pass filter were realized for the frequency range 10 to 40 GHz. The method
of design is based upon a quasi-static model utilizing TEM or quasi-TEM approximation, following this
with a finite difference time-domain technique to evaluate the performance. The mesh was carefully
selected to reduce truncation errors and grid dispersion errors, typically less than 1/20 of the shortest
wavelength. Electrical conductors are assumed perfect conductors and, at dielectric interfaces, the average
of the two permitivities was taken. Metallization comprised Ti/Au/Ti with subsequent electroplating to
a final thickness of 3 µm Au. Alignment between cavities and waveguide structures was achieved via
windows etched through the wafer thickness. Figure 10.30(a) shows a five-section, stepped impedance
low-pass filter in which the 100- and 20-ohm impedance steps are formed by conductor widths of 20
µm and 380 µm, with slot widths of 210 µm and 30 µm, respectively. Figure 10.30(b) shows the integrated
packaging topology and micrographs of the fabricated structures.
Microwave transmission lines have also been fabricated by Milanovíc et al.165 with a commercial CMOS
process with post-processing micromachining. The transmission lines were designed to operate in TEM
mode with 50 and 120 Ω nominal characteristic impedance with standard layout tools. The post-
processing etch was used to remove the silicon from underneath the conductive aluminum transmission
lines to lower the losses. Figure 10.30(c) shows the simplified layout of the co-planar waveguides where
the open areas are shaded in black. The open areas are first etched with a xenon difluoride, followed by
anisotropic chemical etching with EDP. The cavities connect beneath the aluminum conductors, but
enough material remains for mechanical stability. A fully formed trench also lowers electromagnetic
coupling to the substrate. Measurements for test chip with three different lengths, 0.8 to 3.7 mm, with
open and short stubs were made between 1 and 40 GHz. Insertion loss was calculated based on trans-
mission line measurements, as shown in Fig. 10.30(d).
Micromachining 10-45
FIGURE 10.30(a) Integrated packaging. (Drayton, R. F. et al., IEEE Trans. Microwave Theory and Tech., 46, 900, 1998.
With permission.)
FIGURE 10.30(b) Microfabricated two-stage coupler. Chip measures 7.6 × 10 cm. Upper cavity shows probe windows
as dark region. Conductor is dark region in circuit layout. (Franklin-Drayton, R. et al., The International Journal of
Microcircuits and Electronic Packaging, 18, 19, 1995. With permission.)
Thermal Devices
A great deal of progress has been made in the integration of thermal sensors, infrared sensors, and gas
flow sensors with on-chip CMOS electronics. Baltes et al.167 describe the fabrication and operation of a
thermoelectric air-flow sensor and an infrared sensor, in addition to measurements of the thermophysical
properties of material components of CMOS electronics.
10-46 VLSI Technology
FIGURE 10.30(c) SEM micrograph of the 50 Ω transmission lines, of width 130 µm. (a) after CMOS fabrication;
(b) after isotropic etch; and (c) after combined etch. (Milanovic, V. et al., IEEE Trans. Microwave Theory and Techniq.,
45, 630 1997. With permission.)
Micromachining 10-47
FIGURE 10.30(d) Measured effective dielectric constant of transmission lines before and after etching. (Milanovic,
V. et al., IEEE Trans. Microwave Theory and Techniq., 45, 630 1997. With permission.)
FIGURE 10.31 Tuning fork oscillator integrated with CMOS electronics. (Courtesy of Sandia National Laboratories’
Intelligent Micromachine Initiative; www.mdl.sandia.gov/Micromachine and T. Roessig U.C. Berkeley. With permission.)
thermal resistance of 37,000 K/W in air. The cascade CMOS operational amplifier, followed by a source
follower to provide up to 50 mA of current for the heating element, operated from a 5-V supply. The
quiescent power consumption of the amplifier was 950 µW and the –3-dB frequency was 415 MHz. With
a sinusoidal input signal at 1 kHz, the measured dynamic range of the system was from 2.4 mV to 1.1
Micromachining 10-49
(a)
(b)
FIGURE 10.32 (a) Schematic diagram of a complete bandgap reference showing the PMOS heating transistors and
thermal control loop. The shaded regions are thermally separated isolated n-wells; (b) cross-sectional view of a
thermoelement for an RMS converter, at different stages in the fabrication process: (i) upon completion of the CMOS
process, and (ii) after the post processing step of etching in TMAH. (Reay, R. J. et al., IEEE J. Solid-State Circuits,
30,1374, 1995. With permission.)
Microrelays
An important illustrative example of MEMS process integration in which electronic and mechanical
function are combined is the microrelay. There has been considerable interest in relays and switches for
high-impedance isolation of circuit components, and for RF and microwave switching. There is insuffi-
cient space in this chapter to give a comprehensive overview of these activities; however, Table 10.6
summarizes some of the work that has been directed toward the success of these microdevices — grouped
10-50 VLSI Technology
by actuation method. These devices typically have lifetimes of greater than 106 cycles. Zavracky et al.170
and McGruer et al.171 have built electrostatic relays with multiple contacts to increase the maximum
current-carrying capacity. Micrographs of the electroplated thick film of the relay are shown in Fig. 10.33.
Other electrostatic designs demonstrate low power consumption, 172–175 and CMOS-compatible microre-
lays have been demonstrated by Grétillat et al.176 Novel latching surface micromachined devices have
been demonstrated and an example177 is shown in Fig. 10.34(a).178 Alternative actuation schemes are
thermal and magnetic. Finite element modeling of the actuator and the magnetic circuit has been carried
out by Taylor et al.179 to provide improved design methods for these devices (see Fig. 10.34(b)). The
thickness of the permalloy layer must be large enough to avoid saturation of the magnetic field. Minimum
switching current and optimum coil spacing for operation at under 100 mA were achieved in these
devices. The hold force is high — to provide low contact resistance. Contact resistance is a critical issue
and has been studied in macroscopic relays by Holm180 and Schimkat181 with forces in the µN range.
(a)
(b)
FIGURE 10.33 (a) Micrograph of an electrostatically actuated gold metal microrelay; (b) close up view of the
contact area. (McGruer, N. E. et al., in Digest of Technical Papers, Solid-State Sensor and Actuator Workshop, Hilton
Head, South Carolina, June 1998, 132. With permission.)
Micromachining 10-51
FIGURE 10.34(a) Bistable action in the relay frame hold the device in the open or closed state without actuation.
(Kruglick, E. J. J. and Pister, K. S. J., in Digest of Technical Papers, IEEE Solid-State Sensor and Actuator Workshop,
Hilton Head, SC, 1998, 333. With permission.)
FIGURE 10.34(b) Schematic top view of the magnetic microrelay, illustrating the relative positions of the upper
moveable plate, contact, side cores, and coil. The conductor width in the coil is 80 µm. (Taylor, W. P. et al., J.
Microelectro. Mech. Syst., 7, 181, 1998. With permission.)
FIGURE 10.35 Structure of the backshooter microsystem ink-jet print head (not to scale) illustration: 1 - substrate,
6 - field oxide, 7 - gate oxide, 11 - etch stop layer, 12 - PECVD SiO2, 13 - BSG, 14 - first Al layer, 15 - undoped silica
glass, 16 - heater layer, 17 - second Al layer, 18 - thermal throttle layer PECVD Si3N4, 19 - galvanic adhesive layer
Ti/Cu, 20 - carrier layer Ni/ASu, 21 - thermal SiO2. Elements a - bond pad (Al), b - heating element, c - nozzle, d -
p-MOS transistor, e - NMOS transistor, f - ink-jet chamber, g - vapor bubble formed. (Krause, P. et al., Proceedings
of Transducers 95, Stockholm, Sweden, 1995. With permission.)
of pH, CO2, and O2 in vivo is an example of this approach. Here, the device was fabricated by bulk
micromachining on a thin silicon piece approximately 350 µm wide and bonded to an associated interface
circuit chip that was made at an IC foundry.
ISFET
The chemically selective FET developed by Janata185 and Bergveld186 demonstrates specific analyte selec-
tivity based on an FET structure with the gate coated with a chemically sensitive layer exposed to the
solution. The sensing mechanism is based on a variety of surface-specific interactions.187 These devices
may be configured as gas-sensitive devices, for hydrogen detection,188 ion-selective devices,189 enzyme
FETs, and most recently, suspended gate structures. Figure 10.36 shows a schematic diagram of an ISFET.
The important characteristic of these sensors is that the gate potential and, hence, the channel threshold
voltage are defined by the potential applied at the reference electrode and the interfacial potentials. This
potential is related to the activities of participating ions rather than their concentrations. Hydrogen ion
sensitivity is intrinsic to the dielectric material coating the gate. Bousse190 has developed an OH site-
binding theory to account for the pH dependence of the FET for oxide and nitride gates. The most stable
gate dielectric choices are TaO2 and Al2O3. Advanced concepts for back-side contact FETs are reviewed
by Cane et al.191 One of the advantages of ISFET technology is that it can be made compatible with
CMOS processing. An integrated CHEMFET, demonstrated by Domanský et al.,192 is capable of mea-
surement of work function and bulk resistance changes. Here, a carbon black/organic polymer composite
film for the detection of solvents covers the gate, as shown in Fig. 10.36(b).
(a)
FIGURE 10.36(a) Schematic diagram of an ISFET. (Janata, J., in Solid State Chemical Sensors, J. Janata and R. J.
Huber, Eds., Academic Press, New York, 1985. With permission.)
10-54 VLSI Technology
(b)
(c)
FIGURE 10.36(b-c) (b) Carbon black impregnated gate FET. (Domanský, K. et al., in Digest of Technical Paper, IEEE
Solid-State Sensors and Actuators Workshop, Hilton Head, SC, 1998, 187. With permission.); and (c) suspended gate
FET. (Mosowicz, M., and Janata, J., in Chemical Sensor Technology, T. Seiyama, Ed., Elsevier, New York, 1988. With
permission.)
Chemically sensitive layers are, in general, not process compatible with CMOS circuit fabrication.
Approaches that have been made in this area include fabrication of the electronics first, followed by deposition
of the chemically sensitive membranes while the CMOS circuit is covered with a passivation coating.
Hydrogen Sensor
The Pd gate MOS hydrogen sensitive FET was invented by Lundström et al.188 The device is shown
schematically in Fig. 10.37(a). Upon exposure to hydrogen, dipoles are created at the SiO2/Pd interface
producing a shift in the threshold voltage. A hydrogen chemical sensor has been successfully integrated
with electronics components at Sandia National Laboratories (Rodriguez et al.193). This sensor utilizes
two Pd/Ni layers, one as a chemiresistor and the second as the gate of an FET. Figure 10.37(b) shows a
picture of the sensor with integrated heaters and temperature sensors. The FET shown in Fig. 10.37(b)
is more sensitive at low concentration ranges and has a logarithmic response; however, the conductimetric
sensor has a square-root dependence on the hydrogen concentration. The sensors are operated at an
elevated temperature of approximately 100°C to increase the reaction kinetics and improve reversibility.
Typical response data are shown in Fig. 10.37(c) with a 1% hydrogen concentration, resulting in a response
time of a few seconds. The sensor combination has an exceptionally wide dynamic range of six orders
of magnitude, and response time was within 5 seconds. Heating is achieved through two power transistors
and temperature monitoring with an array of nine p/n junction diodes. Typical die size is 270 × 120 mils.
Devices have been demonstrated with stabilities of over 60 days and show reversible behavior. Sensors
are being commercialized for detection of hydrogen in aerospace applications. Advanced versions of this
sensor have also been produced with fully integrated op-amps and control electronics, including analog
capacitors, high-value polysilicon resistors, current mirrors, and operational amplifiers.
Micromachining 10-55
Gas Sensors
Microhotplates have been developed by Suehle et al.194 for tin oxide chemical sensors. These devices
are conductimetric sensors for reducing gases and operate at elevated temperatures, typically ~350°C.
A suspended sandwich structure of CVD oxides, encapsulating a polysilicon heater, and integrated
with an aluminum layer to provide thermal diffusion, is shown in Fig. 10.38. Post-processing was
carried out after a standard CMOS process by EDP etching with added aluminum hydroxide to ensure
passivation of any exposed Al conductors. Heating current (mA) was provided to the polysilicon layer
and temperature sensing from van der Pauw aluminum layer with a temperature coefficient of
resistance typically 0.003667/°C. The hotplates were effectively thermally isolated, showing efficiency
of 8°C/mW in air, thermal time constant of 0.6 ms, and maximum operating temperature of 500°C.
(a)
(b)
FIGURE 10.37(a-b) (a) Pd-gate FET. (Lundström, I. and Svensson, C., in Solid State Chemical Sensors, J. Janata
and R. J. Huber, Eds., Academic Press, New York, 1985. With permission.); (b) Photograph of the robust hydrogen
sensor with integrated temperature sensors, Pd gate FET, chemiresistor, and heater elements. (Rodriguez, J. L. et
al., IEDM Tech. Digest, IEEE, San Francisco, CA, Dec. 1992, 521–524. With permission.)
10-56 VLSI Technology
(c)
FIGURE 10.37(c) Response of sensor to hydrogen. (Rodriguez, J. L. et al., IEDM Tech. Digest, IEEE, San Francisco,
CA, Dec. 1992, 521–524. With permission.)
(a)
(b)
FIGURE 10.38 (a) Schematic diagram of a single microhot plate and functional cross-section of component parts;
(b) static response at 130°C of a Pt/SnO2 microsensor to on/off CO exposures, into dry air, of increasing concentra-
tions from 5 to 45 ppm. (Suehle, J. S. et al., IEEE Elec. Dev. Lett., 14, 118 1993. With permission.)
Micromachining 10-57
SnO2 was deposited onto the hotplate by reactive sputter deposition in ultrahigh vacuum; and by
heating the platform during deposition, selective control of the local material properties was achieved
(such as grain size and the conductivity). After deposition, annealing was also carried out selectively
in situ on the hotplates. The selectivity of these devices can be further modified by addition of catalytic
metals such as Pt, Pd, or Ir. Semancik and Cavicchi195 have demonstrated kinetic sensing on micro-
hotplates by modulation of the sensor temperature to enhance analyte discrimination. Microhotplates
were also fabricated with tungsten metallization so they could operate up to 800°C. The response of
a Pt-doped SnO2 sensor operating at 130°C to CO gas is shown in Fig. 10.38(b). The stability of high-
temperature micromachined TiOx gas sensors has been investigated by Patel et al.196 for measurements
of hydrogen and propylene in the presence of oxygen. The temperature played a key role in defining
the sensor response to hydrogen at 100°C and propylene when above 350°C.
Artificial Nose
Microfabrication technology lends itself to the construction of arrays of sensors with differing chemical
selectivities. Capacitive-based gas sensors having selectivity to different classes of chemical species197 along
(a)
(b)
FIGURE 10.39 (a) Schematic diagram of boron doped etch stopped neural probe. (Najafi, K., Handbook of Microli-
thography, Micromachining, and Microfabrication, Vol. 2: Micromachining and Microfabrication, Ed. P. Rai-Choudhury,
SPIE, Washington, 1997, 517. With permission.); (b) schematic diagram of the neural interface structure. (Akin, T.
and Najafi, K., IEEE Trans. Biomed. Eng., 41, 305, 1994. With permission.)
10-58 VLSI Technology
with pattern recognition198 have been demonstrated as a viable scheme for the realization of the electronic
nose. The polymer coatings produce characteristic dielectric constant, mass, or conductivity changes
when the analyte is adsorbed. This work on chemiresistor arrays has also been integrated with CMOS
interface circuits for applications in food quality and odor identification.
Neural Probes
Najafi199 has reviewed his extensive work on neural probes with integrated electronics. The early design
involved four masks and had a high yield. A boron diffusion defined the thickness of the structure. Three-
dimensional multielectrode systems were later developed to improve electrode positioning. Each array
of neural probes is inserted into a silicon machined substrate and electrical connections are made between
the probe and support chip by electroplating nickel. On the chip, preamplifiers are followed by analog
multiplexers and a broad-band output buffer to drive the external data line. Later developments included
a NMOS and CMOS integrated circuit with ten recording sites of gold electrodes on 100-µm centers.
The circuit operated with a 5-V supply and consumes 5 mW. A 32-electrode version also has an integrated
multiplexing for 32-to-8 switching array. Preamp specifications were 150 to 300 V/V, –3 dB bandwidth
100 Hz to 10 kHz. Akin and Najafi200 have developed novel sieve structures for stimulation electrodes.
They include a silicon ribbon cable that allows connections with minimal mechanical hindrance of the
implant while maintaining electrical connections. Neural probes for recording brain activity have also
been fabricated by Kewley et al.,201 with integration of the buffer electronics with the probe tip electrode.
The advantage of a dry-etch process is a small, well-defined tip radius of 0.25 µm in this case. He integrated
18-channel preamplifiers in a MOSIS 2-µm, low-noise analog process, each having a total gain of 150
V/V. Probe tips of iridium were fabricated with PECVD layers of silicon nitride low-stress material over
the electrodes, achieving a parasitic capacitance of 20 pF and an electrode capacitance of 40 pF; stable,
low-leakage current of less than 0.25 pA at a 5-V bias in buffered saline solutions, in addition to
maintaining a well-adhered film necessary to maintain the tip electrode integrity.
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11
Microelectronics
Packaging
11.1 Introduction
Packaging of electronic circuits is the science and the art of establishing interconnections and a suitable
operating environment for predominantly electrical circuits. It supplies the chips with wires to distribute
signals and power, removes the heat generated by the circuits, and provides them with physical support
and environmental protection. It plays an important role in determining the performance, cost, and
reliability of the system. With the decrease in feature size and increase in the scale of integration, the
delay in on-chip circuitry is now smaller than that introduced by the package. Thus, the ideal package
would be one that is compact, and should supply the chips with a required number of signal and power
connections, which have minute capacitance, inductance, and resistance. The package should remove the
heat generated by the circuits. Its thermal properties should match well with semiconductor chips to
avoid stress-induced cracks and failures. The package should be reliable, and it should cost much less
than the chips it carries1 (see Table 11.1).
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 11-1
11-2 VLSI Technology
logic circuits and/or bits of storage that must be packaged, interconnected, supplied with electric power,
kept within a proper temperature range, mechanically supported, and protected against the environment.
Thus, IC packages are designed to accomplish the following three basic functions:5
• Enclose the chip within a protective envelope to protect it from the external environment
• Provide electrical connection from chip to circuit board
• Dissipate heat generated by the chip by establishing a thermal path from a semiconductor junction
to the external environment
To execute these functions, package designers start with a fundamental concept and, using principles
of engineering, material science, and processing technology, create a design that encompasses:
1. Low lead capacitance and inductance
2. Safe stress levels
3. Material compatibility
4. Low thermal resistance
5. Seal integrity
6. High reliability
7. Ease of manufacture
8. Low cost
Success in performing the functions outlined depends on the package design configuration, the choice
of encapsulating materials, and the operating conditions.6,7 Package design is driven by performance,
cost, reliability, and manufacturing considerations. Conflicts between these multiple criteria are common.
The design process involves many tradeoff analyses and the optimization of conflicting requirements.
While designing the package for an application, the following parameters are considered.
Number of Terminals
The total number of terminals at packaging interfaces is a major cost factor. Signal interconnections and
terminals constitute the majority of conducting elements. Other conductors supply power and provide
ground or other reference voltages.
The number of terminals supporting a group of circuits is strongly dependent on the function of this
group. The smallest pinout can be obtained with memory ICs because the stream of data can be limited
to a single bit. Exactly the opposite is the case with groups of logic circuits which result from a random
partitioning of a computer. The pinout requirement is one of the key driving parameters for all levels of
packaging: chips, chip carriers, cards, modules, cables, and cable connectors.
(b)
FIGURE 11.2 Steady-state heat flow and thermal resistance in a multilayer structure (a) path of heat flow; (b)
equivalent electrical circuit based on thermal resistance.
Microelectronics Packaging 11-5
in analogy with electric circuits. If there are parallel paths for heat flow, the thermal resistances are
combined in exactly the same manner as electrical resistors in parallel.
Rθcs, the conductive thermal resistance, is mainly a function of package materials and geometry. With
the higher power requirements, one must consider the temperature dependence of materials selected in
design. Tj depends on package geometry, package orientation in the application, and the conditions of
the ambient in the operating environment. The heat sink is responsible for getting rid of the heat of the
environment by convection and radiation. Because of all the many heat transfer modes occurring in a
finned heat sink, the accurate way to obtain the exact thermal resistance of the heat sink would be to
measure it. However, most heat sink manufacturers today provide information about their extrusions
concerning the thermal resistance per unit length.
Reliability
The package should have good thermomechanical performance for better reliability. A variety of materials
of widely differing coefficients of thermal expansion (CTEs) are joined to create interfaces. These inter-
faces are subject to relatively high process temperatures and undergo many temperature cycles in their
useful life as the device is powered on and off. As a result, residual stresses are created in the interfaces.
These stresses cause reliability problems in the packages.15,16
Testability
Implicit in reliability considerations is the assumption of a flawless product function after its initial
assembly — a zero defect manufacturing. Although feasible in principle, it is rarely practiced because of
the high costs and possible loss of competitive edge due to conservative dimensions, tolerances, materials,
and process choices. So, several tests are employed to assess the reliability of the packages.17,18
Plastic Packaging
Plastic is a generic term for a host of man-made organic polymers. Polymer materials are relatively porous
structures, which may allow absorption or transport of water molecules and ions.19 The aluminum
metallization is susceptible to rapid corrosion in the presence of moisture, contaminants, and electric
fields. So, plastic packages are not very reliable. Impurities from the plastic or other materials in the
construction of the package can cause threshold shifts or act as catalysts in metal corrosion. Fillers can
also affect reliability and thermal performance of the plastic package.
Ceramic Packaging
Pressed ceramic technology packages are used mainly for economically encapsulating ICs and semi-
conductor devices requiring hermetic seals. Hermeticity means that the package must pass both gross
and fine leak tests and also exclude environmental contaminants and moisture for a long period of
time. Further, any contaminant present before sealing must be removed to an acceptable level before
or during the sealing process.20 Silicon carbide (SiC), aluminum nitride, beryllia (BeO), and alumina
11-6 VLSI Technology
Metals
Coefficient of Thermal
Expansion (CTE) Thermal Conductivity Specific Electrical
Metals (10–6 K–1) (W/cm-K) Resistance 10–6Ω-cm
Aluminum 23 2.3 2.8
Silver 19 4.3 1.6
Copper 17 4.0 1.7
Molybdenum 5 1.4 5.3
Tungsten 4.6 1.7 5.3
Substrates
Coefficient of Thermal
Expansion (CTE) Thermal Conductivity
Insulating Substrates (10–6 K–1) (W/cm-K) Dielectric Constant
Alumina (Al2O3) 6.0 0.3 9.5
Beryllia (BeO) 6.0 2.0 6.7
Silicon carbide (SiC) 3.7 2.2 42
Silicon dioxide (SiO2) 0.5 0.01 3.9
Semiconductors
Coefficient of Thermal
Expansion (CTE) Thermal Conductivity
Semiconductors (10–6 K–1) (W/cm-K) Dielectric Constant
Silicon 2.5 1.5 11.8
Germanium 5.7 0.7 16.0
Gallium arsenide 5.8 0.5 10.9
(Al2O3) are some of the ceramics used in electronic packaging. In comparison with other ceramics,
SiC has a thermal expansion coefficient closer to silicon, and as a result less stress is generated between
the dice and the substrate during temperature cycling. In addition, it has a very high thermal conduc-
tivity. These two properties make SiC a good packaging substrate and a good heat sink that can be
bonded directly to silicon dice with little stress generation at elevated temperatures. Its high dielectric
constant, however, makes it undesirable as a substrate to carry interconnections. Alumina and BeO
have properties similar to SiC.21
FIGURE 11.4 A generic schematic diagram showing the difference between the surface-mount technology (upper)
and through hole mounting (lower).
(a) Dual in-line package (DIP). (b) Quad flat package (QFD). (c) Pin grid array package (PGA).
Surface-Mounted Packages
Surface mounting solves many of the shortcomings of through-the-board mounting. In this technology,
a chip carrier is soldered to the pads on the surface of a board without requiring any through holes. The
smaller component sizes, lack of through holes, and the possibility of mounting chips on both sides of
the PC board improve the board density. This reduces package parasitic capacitances and inductances
associated with the package pins and board wiring. Various types of surface-mount packages are available
on the market and can be divided into the following categories. (See Fig. 11.6.)
(a) Small outline package (SOP). (b) Plastic-leaded chip carriers (PLCC). (c) Leadless ceramic chip
carriers (LCCC).
Flip-Chip Packages
The length of the electrical connections between the chip and the substrate can be minimized by placing
solder bumps on the dice, flipping the chips over, aligning them with the contacts pads on the substrate,
and reflowing the solder balls in a furnace to establish the bonding between the chips and the package.
This method provides electrical connections with minute parasitic inductance and capacitance. In addi-
tion, contact pads are distributed over the entire chip surface. This saves silicon area, increases the
maximum I/O and power/ground terminals available with a given die size, and provides more efficiently
routed signal and power/ground interconnections on the chips.24 (See Fig. 11.7.)
Silicon-on-Silicon Hybrid
A silicon substrate can also be used as an interconnection medium to hold multi-chips as an alternative
to ceramic substrates. This is called silicon-on-silicon packaging or, sometimes, hybrid wafer-scale
integration. Thin-film interconnections are fabricated on a wafer and separately processed, and test
dice are mounted on this silicon substrate via wire bonding, TAB, or solder bumps. Using this
technique, chips fabricated in different technologies can be placed on the same hybrid package. The
silicon substrate can also potentially contain active devices that serve as chip-to-chip drivers, bus and
I/O multiplexers, and built-in test circuitry.29
FIGURE 11.8 A generic schematic diagram of an MCM, showing how bare dice are interconnected to an MCM
substrate using different interconnection technologies.
Microelectronics Packaging 11-11
itself does not cause electronic problems when trapped in an electronic package, because it is a poor
electrical conductor. However, water can dissolve salts and other polar molecules to form an electro-
lyte, which, together with the metal conductors and the potential difference between them, can create
leakage paths as well as corrosion problems. Moisture is contributed mainly by the sealing ambient,
the absorbed and dissolved water from the sealing materials, lid and the substrate, and the leakage
of external moisture through the seal. No material is truly hermetic to moisture. The permeability
to moisture of glasses, ceramics, and metals, however, is very low and is orders of magnitude lower
than for any plastic material. Hence, the only true hermetic packages are those made of metals,
ceramics, and glasses. The common feature of hermetic packages is the use of a lid or a cap to seal
in the semiconductor device mounted on a suitable substrate. The leads entering the package also
need to be hermetically sealed.
Wire Bonding
Wire bonding (see Fig. 11.10) is a method used to connect a fine wire between an on-chip pad and a
substrate pad. This substrate may simply be the ceramic base of a package or another chip. The common
materials used are gold and aluminum. The main advantage of wire bonding technology is its low cost;
but it cannot provide large I/O counts, and it needs large bond pads to make connections. The connections
have relatively poor electrical performance.
Tape-Automated Bonding
In tape-automated bonding (TAB) technology, a chip with its attached metal films is placed on a
multilayer polymer tape. The interconnections are patterned on a multilayer polymer tape. The tape is
positioned above the “bare die” so that the metal tracks (on the polymer tape) correspond to the bonding
sites on the die (Fig. 11.11). TAB technology provides several advantages over wire bonding technology.
It requires a smaller bonding pad, smaller on-chip bonding pitch, and a decrease in the quantity of gold
used for bonding.30 It has better electrical performance, lower labor costs, higher I/O counts and lighter
weight, greater densities, and the chip can be attached in a face-up or face-down configuration. TAB
technology includes time and cost of designing and fabricating the tape and the capital expense of the
11-12 VLSI Technology
TAB bonding equipment. In addition, each die must have its own tape patterned for its bonding config-
uration. Thus, TAB technology has typically been limited to high-volume applications.
determined by the physical parameters such as interconnect width, thickness, length, spacing, and resis-
tivity; by the thickness of the dielectric; and by the dielectric constant.
Resistance refers to both dc and ac. The dc resistance of an interconnect is a property of its cross-
sectional area, length, and material resistivity. In addition, the ac resistance depends on the frequency of
the signal and is higher than the dc resistance because of the skin effect. Resistance in the power
distribution path results in attenuation of input signals to the device and output signals from the device.
This has the effect of increasing the path delay.
Capacitance of an interconnect is a property of its area, the thickness of the dielectric separating it
from the reference potential, and the dielectric constant of the dielectric. It is convenient to consider this
as two parts: capacitance with respect to ground, and capacitance with respect to other interconnections.
The capacitance with respect to ground is referred to as the load capacitance. This is seen as part of the
load by the output driver and thus can slow down the rise time of the driver. Interlead capacitance couples
the voltage change on the active interconnect to the quiet interconnect.32 This is referred to as crosstalk.
Inductance can be defined only if the complete current path is known. In the context of component
packages, the inductance of an interconnect should be understood as part of a complete current loop.
Thus, if the placement of the package in the system alters the current path in the package, the package
inductance will vary. Total inductance consists of self-inductance and mutual inductance. Mutual induc-
tance between two interconnects generates a voltage in one when there is current change in the other.
Inductive effects are the leading concern in the design of power distribution paths in high-performance
packages. They are manifested as “ground bounce” noise and “simultaneous switching” noise.
In wireless applications, the trend is to integrate multiple modules on a single chip.37 So, the thermal
management of the whole chip becomes crucial. The IC package must have good thermal properties.
Metal as a material shows optimal properties concerning thermal conductivity, electromagnetic shielding,
mechanical and thermal stability. For thermal expansion, best match to semiconductor and ceramic
material can be achieved with molybdenum, tungsten, or special composites like kovar. Ceramic materials
are applied, both as parts of the package as well as for subsystem-carrying RF transmission lines. To this
end, and to provide electromagnetic shielding, these materials partly have to be metallized. Aluminum
nitride, beryllia, aluminum silicon carbide, and CVD diamond show best thermal conductivity and are
therefore applied in high-power applications,38,39 while alumina is well known for standard microwave
applications.40
Integration of passive components is a major challenge in wireless packages. More and more efforts
are being made to integrate passive components, power devices on a chip, with the other mixed signal
circuits.41 The size of the package becomes an issue. Micromachining technology provides a way to make
miniature packages that conform to RF circuits, while providing physical and electrical shielding. Con-
formal packages made by applying micromachining technology provide the capability to isolate individual
circuit elements and improve circuit performance by eliminating the radiation and cross-coupling
between the adjacent circuits.42,43
At high frequencies, interconnections need to be carefully designed. Microstrip interconnects and co-
planar waveguides are mostly used for microwave packaging.44 Flip-chip packaging has tremendous
potential for future RF packaging.45
References
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Reinhold, New York, 1989.
2. Bakoglu, H. B., Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, New York, 1990.
3. Tummala, R. R., “Electronic Packaging in the 1990s — A Perspective from America,” IEEE Trans.
Components, Hybrids, Manuf. Technol., vol. 14, no. 2, pp. 262, June 1991.
4. Wessely, H., “Electronic Packaging in the 1990s — A Perspective from Europe,” IEEE Trans.
Components, Hybrids, Manuf. Technol., vol. 14, no. 2, pp. 272, June 1991.
Microelectronics Packaging 11-15
5. Mones, A. H. and Spielberger, R. K., “Interconnecting and Packaging VLSI Chips,” Solid State
Technology, pp. 119-122, Jan. 1984.
6. Kakei, M., “Low Stress Molding Compounds for VLSI Devices,” Nikkei Microdevices, 1984.
7. Lyman, J., “VLSI Packages are Presenting Diversified Mix,” Electronics, pp. 67-73, Sept. 1984.
8. Bakoglu, H. B., “Packaging for High-Speed System,” IEEE International Solid-State Circuits Con-
ference (ISSCC’98), pp. 100-101, San Francisco, Feb. 1988.
9. Kaupp, H. R., “Characteristics of Microstrip Transmission Line,” IEEE Trans. Computers, EC-16,
pp. 185, April 1967.
10. Trivedi, M. and Shenai, K., “Framework for Power Package Design and Optimization,” Intl. Work-
shop on Integrated Power Packaging (IWIPP’98), 1998, Chicago, IL.
11. Khandelwal, P., Trivedi, M., and Shenai, K., “Thermal Issues in LDMOSFET’s Packages,” European
Solid-State Device Research Conference (ESSDRC), 1998.
12. Manchester, K. and Bird, K., “Thermal Resistance: A Reliability Consideration,” IEEE Trans. Com-
ponents, Hybrids, Manuf. Technol., vol. 31, no. 4, pp. 550, Dec. 1980.
13. Chu, R. C., Hwang, U. P., and Simons, R. E., “Conduction Cooling for LSI Packages, A One-
Dimensional Approach,” IBM Journal of Research and Development, vol. 26, no. 1, pp. 45-54, Jan. 1982.
14. Mohan, N., Undeland, T. M., and Robbins, W. P., Power Electronics: Converters, Applications, and
Design, John Wiley & Sons, 1996.
15. Fukuzawa, I., “Moisture Resistance Degradation of Plastic LSIs by Reflow Soldering,” Proc. Inter-
national Reliability Physics Symposium, pp. 192, 1985.
16. Lau, J. H., Solid Joint Reliability: Theory and Applications, Van Nostrand Reinhold, New York, 1991.
17. Gallace, L. J. and Rosenfield, M., “Reliability of Plastic Encapsulated Integrated Circuit in Moisture
Environments,” RCA Review, vol. 45, no. 2, pp. 95-111, June 1984.
18. Lau, J. H., “Thermal Stress Analysis of SMT PQFP Packages and Interconnections,” J. Electronic
Packaging, Trans. ASME, vol. 2, pp. 111, March 1989.
19. Kawai, S., “Structure Design of Plastic IC Packages,” Proc. SEMI Tech. Symposium, pp. 349, Nov.
1988.
20. White, M. L., “Attaining Low Moisture Levels in Hermetic Packages,” Proc. 20th International
Reliability Physics Symposium, pp. 253, 1982.
21. Sepulveda, J. L. and Siglianu, R., “BeO Packages House High-Power Components,” Microwaves &
RF, pp. 111-124, March 1998.
22. Fehr, G., Long, J., and Tippetts, A., “New Generation of High Pin Count Packages,” Proc. IEEE
Custom Integrated Circuits Conference (CICC’85), pp. 46-49, 1985.
23. Sudo, T., “Considerations of Package Design for High Speed and High Pin Count CMOS Devices,”
Proc. 39th Electronic Components and Technology Conference, 1989.
24. Midford, T. A., Wooldridge, J. J., and Sturdivant, R. L., “The Evolution of Packages for Monolithic
Microwave and Millimeter Wave Circuits,” IEEE Trans. Antennas and Propagation, vol. 43, no. 9,
pp. 983, Sept. 1995.
25. Yamaji, Y., Juso, H., Ohara, Y., Matsune, Y., Miyata, K., Sota, Y., Narai, A., and Kimura, T.,
“Development of Highly Reliable CSP,” Proc. 47th Electronic Components and Technology Conference,
pp. 1022-1028, 1997.
26. Su, L. S., Louis, M., and Reber, C., “Cost Analysis of Chip Scale Packaging,” Proc. 21st IEEE/CPMT
Intl. Electronics Manufacturing Technology Symposium, pp. 216-223, 1997.
27. Lyman, J., “Multichip Modules Aim at Next Generation VLSI,” Electronic Design, pp. 33-34, March
1989.
28. Barlett, C. J., Segelken, J. M., and Teneketgen, N. A., “Multichip Packaging Design for VLSI Based
Systems,” IEEE Trans. Components, Hybrids, Manuf. Technol., vol. 12, no. 4, pp. 647-653, Dec. 1987.
29. Spielberger, R. K., Huang, C. D., Nunne, W. H., Mones, A. H., Fett, D. C., and Hampton, F. L.,
“Silicon-on-Silicon Packaging,” IEEE Trans. Components, Hybrids, Manuf. Technol., vol. 7, no. 2,
pp. 193-196, June 1984.
11-16 VLSI Technology
30. Andrews, W., “High Density Gate Arrays Tax Utility, Packaging, and Testing,” Computer Design,
pp. 43-47, Aug. 1988.
31. Fujimoto, H., “Bonding of Ultrafine Terminal-Pitch LSI by Micron Bump Bonding Method,” Proc.
IMC, p. 115, 1992.
32. Dang, R. L. M. and Shigyo, N., “Coupling Capacitance for Two-Dimensional Wires,” IEEE Electron
Device Letters, vol. EDL-2, pp. 196-197, Aug. 1981.
33. Jackson, R. W., “A Circuit Topology for Microwave Modeling of Plastic Surface Mount Packages,”
IEEE Trans. Microwave Theory and Techniques, vol. 44, pp. 1140-1146, 1997.
34. Gupta, R., Allstot, D. J., and Meixner, R., “Parasitic-Aware Design and Optimization of CMOS RF
Integrated Circuits,” IEEE MTT-S International Symposium, vol. 3, pp. 1867-1870, 1998.
35. Perugupalli, P., Xu, Y., and Shenai, K., “Measurement of Thermal and Packaging Limitations in
LDMOSFETs for RFIC Applications,” IEEE Instrumentation and Measurement Technology Confer-
ence (IMTC), pp. 160-164, May 1998.
36. Raid, S. M., Su, W., Salma, I., Riad, A. E., Rachlin, M., Baker, W., and Perdue, J., “Plastic Packaging
Modeling and Characterization at RF/Microwave Frequencies,” Proc. 3rd International Symposium
on Advanced Packaging Materials, p. 147, Mar. 1997.
37. Bugeau, J. L., Heitkamp, K. M., and Kellerman, D., “Aluminum Silicon Carbide for High Perfor-
mance Microwave Packages,” IEEE MTT-S International Symposium, vol. 3, pp. 1575-1578, 1995.
38. Gomes-Casseres, M. and Fabis, P. M., “Thermally Enhanced Plastic Package Using Diamond for
Microwave Applications,” IEEE MTT-S International Symposium, vol. 1, pp. 227-230, 1996.
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Electrical Performance of Electronic Packaging, pp. 139-242, 1994.
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Electronics Conference, vol. 1, pp. 106-113, 1995.
41. Drayton, R. F. and Katehi, L.P.B., “Micromachined Conformal Packages for Microwave and Milli-
meter-Wave Applications,” IEEE MTT-S International Symposium, vol. 3, pp. 1387-1390, 1995.
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for High Performance Circuits and Antennas,” IEEE MTT-S International Symposium, vol. 3, pp.
1615-1618, 1996.
43. Wein, D. S., “Advanced Ceramic Packaging for Microwave and Millimeter Wave Applications,”
IEEE Trans. Antennas and Propagation, vol. 43, pp. 940-948, Sept. 1995.
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Millimeter-Wave Packaging,” IEEE MTT-S International Symposium, vol. 2, pp. 987-990, 1997.
12
Multichip Module
Technologies
12.1 Introduction
From the pioneering days to its current renaissance, the electronics industry has become the largest and
most pervasive manufacturing industry in the developed world. Electronic products have the hallmark
of innovation, creativity, and cost competitiveness in the world market place. The way the electronics
are packaged, in particular, has progressed rapidly in response to customers’ demands in general for
diverse functions, cost, performances, and robustness of different products. For practicing engineers,
there is a need to access the current state of knowledge in design and manufacturing tradeoffs.
Thus arises a need for electronics technology-based knowledge to optimize critical electronic design
parameters such as speed, density, and temperature, resulting in performance well beyond PC board
design capabilities. By removing discrete component packages and using more densely packed intercon-
nects, electronic circuit speeds increase. The design challenge is to select the appropriate packaging
technology, and to manage any resulting thermal problems.
The expanding market for high-density electronic circuit layouts calls for multi-chip modules (MCMs)
to be able to meet the requirements of fine track and gap dimensions in signal layers, the retention of
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accurately defined geometry in multilayers, and high conductivity to minimize losses. Multi-chip module
technologies fill this gap very nicely. This chapter provides engineers/scientists with an overview of
existing MCM technologies and briefly explains similarities and differences of existing MCM technolo-
gies. The text is reinforced with practical pictorial examples, omitting extensive development of theory
and details of proofs.
The simplest definition of a multi-chip module (MCM) is that of a single electronic package containing
more than one integrated circuit (IC) die.1 An MCM combines high-performance ICs with a custom-
designed common substrate structure that provides mechanical support for the chips and multiple layers
of conductors to interconnect them.
One advantage of this arrangement is that it takes better advantage of the performance of the ICs than
it does interconnecting individually packaged ICs because the interconnect length is much shorter. The
really unique feature of MCMs is the complex substrate structure that is fabricated using multilayer
ceramics, polymers, silicon, metals, glass ceramics, laminates, etc. Thus, MCMs are not really new. They
have been in existence since the first multi-chip hybrid circuit was fabricated. Conventional PWBs
utilizing chip-on-board (COB), a technique where ICs are mounted and wire-bonded directly to the
board, have also existed for some time. However, if packaging efficiency (also called silicon density),
defined as the percentage of area on an interconnecting substrate that is occupied by silicon ICs, is the
guideline used to define an MCM, then many hybrid and COB structures with less than 30% silicon
density do not qualify as MCMs. In combination with packaging efficiency, a minimum of four conductive
layers and 100 I/O leads has also been suggested as criteria for MCM classification.1
A formal definition of MCMs has been established by the Institute for Interconnecting and Packaging
Electronic Circuits (IPC). They defined three primary categories of MCMs: MCM-L, MCM-C, and
MCM-D.
It is important to note that these are simple definitions. Consequently, many IC packaging schemes,
which technically do not meet the criteria of any of the three simple definitions, may incorrectly be
referred to as MCMs. However, when these simple definitions are combined with the concept of packaging
efficiency, chip population, and I/O density, there is less confusion about what really constitutes an MCM.
The fundamental (or basic) intent of MCM technology is to provide an extremely dense conductor matrix
for the interconnection of bare IC chips. Consequently, some companies have designated their MCM
products as high-density interconnect (HDI) modules.
MCM-L
Modules constructed of plastic laminate-based dielectrics and copper conductors utilizing advanced
forms of printed wiring board (PWB) technologies to form the interconnects and vias are commonly
called “laminate MCMs,” or MCM-Ls.2
Advantages
Economic Ability to fabricate circuits on large panels with a multiplicity
of identical patterns. Reduces manufacturing cost. Quick
response to volume orders.
Multichip Module Technologies 12-3
Disadvantages
Technological More limited in interconnect density relative to advanced
MCM-C and MCM-D technologies. Copper slugs and cut-
outs are used in MCM-Ls for direct heat transfer. This
degrades interconnection density.
MCM-L development has involved evolutionary technological advances to shrink the dimensions of
interconnect lines and vias. From a cost perspective, it is desirable to use conventional PWB technologies
for MCM-L fabrication. This is becoming more difficult as the need for multi-chip modules with higher
interconnect density continues.
As MCM technologies are being considered for high-volume consumer products applications, a focus
on containing the cost of high-density MCM-Ls is becoming critical.
The most useful characteristic in assessing the relative potential of MCM-L technology is intercon-
nection density,3,4 which is given by:
The above formula measures how much of the surface of the board can be used for chip mounting pads
versus how much must be avoided because of interconnect traces and holes/pads.
MCM-C
These are modules constructed on co-fired ceramic or glass-ceramic substrates using thick-film
(screen printing) technologies to form the conductor patterns using fireable metals. The term “co-
fired” implies that the conductors and ceramic are heated at the same time. These are also called
thick-film MCMs.
Ceramic technology for MCMs can be divided into four major categories
• Thick-film hybrid process
• High-temperature co-fired alumina process (HTCC)
• Low-temperature co-fired ceramic/glass based process (LTCC)
• High Tc aluminum nitride co-fired substrate (AIN)
Thick-film hybrid technology produces by the successive deposition of conductors, dielectric, and/or
resistor patterns onto a base substrate.5 The thick-film material, in the form of a paste, is screenprinted
onto the underlying layer, then dried and fired. The metallurgy chosen for a particular hybrid construction
depends on a number of factors, including cost sensitivity, conductivity requirements, solderability, wire
bondability, and more. A comparative summary of typical ceramic interconnect properties is compiled
in Table 12.1.
Thick-Film Metallization
The greensheet is cast, dried, stripped from the carrier film, and blanked into defect-free sheets, typically
200 mm2. The greensheet is then processed through punching, screening, and inspection operations.
HTCC in Summary
• Electrical performance characteristics include 50-ohm impedance, low conductor resistance, abil-
ity to integrate passive components such as capacitors and inductors, the ability to achieve high
wiring density (ease of increasing the number of wiring at low cost), the ability to support high-
speed simultaneous switching drivers, and the ease of supporting multiple reference voltages.
• Inherent thermal performance characteristics superior to MCM-L and MCM-D.
• Time-demonstrated reliability.
MCM-D
Modules are formed by the deposition of thin-film metals and dielectrics, which may be polymers or
inorganic dielectrics. These are commonly called thin-film MCMs.
Here, the focus will be on materials to fabricate the high-density MCM-D interconnect. The materials
of construction can be categorized as the thin-film dielectric, the substrate, and the conductor metallization.
chips need that heat conducting medium. It is informative to state that high-density, large-area processing
has generated interest in glass as a carrier material.
Metallic substrates have been used to optimize the thermal and mechanical requirements while min-
imizing substrate raw material and processing costs. Metallic sandwiches such as Cu/Mo/Cu can be
tailored to control CTE and thermal properties. 5%Cu/Mo/5%Cu is reported to have a thermal conduc-
tivity (TC) of 135 W/mK, a CTE of 5.1 ppm, an as-manufactured surface finish of 0.813 µm, and a
camber of 0.0005 in/in.
Aluminum
Aluminum is a low-cost material that has adequate conductivity and can be deposited and patterned by
typical IC techniques. It is resistant to oxidation. It can be sputtered or evaporated, but cannot be
electroplated.
Copper
Copper has significant conductivity over aluminum and is more electromigration-resistant. It can be
deposited by sputtering, evaporation, electroplating, or electroless plating. Copper rapidly oxidizes,
forming a variety of oxides that can have poor adhesion to polymer dielectrics and copper itself.
Gold
Gold is used in thin-film structures to minimize via contact resistance problems caused by oxidation of
Cu and Al. Gold can be deposited by sputtering, evaporation, electroplating, or electroless plating. Cost
is high with excellent resistivity characteristic. Adhesion is poor and so it requires a layer (50 to 200 nm)
of Ti or Ti/W.
would like to get a feel of what technologies are viable in the MCM technology domain. Here, it is
important to mention that a lot of current space electronic flight projects use MCM technologies for
their final deliverables. Project Cassini, for example, used MCM hybrids in telecommunication subas-
semblies. On this note, take a look at some of the examples of MCM technologies currently on the market.
Chip-on-Board
Chip-on-board substrate technology (Fig. 12.1) has low set-up and production costs and utilizes Rigid
FR-406, GETEK, BT Epoxy, or other resin boards.3 Assembly techniques used are direct die attach/wire
bonding techniques, combined with surface-mount technologies.
Chip-on-Flex
Chip-on-Flex substrate technologies18,19 (Fig. 12.2) are excellent for high-frequency, space-constrained
circuit implementation. In creating this particular technology, the manufacturer needs Kapton or an
equivalent flex-circuit base material with board stiffeners. Here, the die can be wire-bonded, with “glob-
top” protection, while other discretes can be surface mounted. Integral inductors can be incorporated
(e.g., for load matching).
Thick-Film Ceramic
This technology is the most versatile technology, with low-to-medium production costs. The 1-GHz
attenuator above demonstrates the versatility of thick film on ceramic substrate technology (Fig. 12.3),
which utilizes both standard and custom ICs, printed resistors, and capacitors actively trimmed to 0.25%
with extremely stable capacitors formed between top plate and ground plane on the other side of substrate.
Thick-film thermistor here senses overheating resistor and protects the remainder of the circuit.
Co-Fired Ceramic
Co-fired ceramic MCM substrate technologies (low- or high-temperature co-fired multilayer ceramic)
(Fig. 12.4) are particularly suited for high-density digital arrays. Despite its high set-up and tooling costs,
up to 14 co-fired ceramic layers are available from this particular manufacturer. In this technology, many
package styles are available, including DIP, pin-grid array, and flat pack.
Thin-Film Ceramic
For thin-film ceramic technologies (see Fig. 12.5), here the outlined technology features include:
Surface-Mount Assembly
The surface-mount assembly technique can be categorized under lowest-cost, fastest turnaround assembly
method, using pre-packaged components soldered to glass-epoxy board, flex circuit, or thick-film ceramic
substrate. Many package styles are available, such as SIP and DIP. Pins may be attached as in-line leads,
90° leads, etc.19
TABLE 12.3 Thick-Film Specifications
Sheet Resistivity per
Printed Component Square Typical Values Comments
Chip-and-Wire Assembly
In order to minimize interconnect electronic circuit parasitics, a high-density layout is one of the assembly
techniques recommended as a solution. The highlight of this technique is epoxy attachment/wire bonding
of integrated circuits and components (e.g., capacitors) to a glass-epoxy board (chip-on-board). Of
course, another way is attachment to a thick- or thin-film ceramic substrate. Currently, many package
styles are available and can be listed as follows:19,20
• Epoxy seal, using a B-stage ceramic lid epoxies to the substrate (quasi-hermetic seal)
• Encapsulation, in which bare semiconductor die are covered with a “glob top” (low-cost seal)
• Metal (typically Kovar) package with Kovar lid either welded or soldered to the package (hermetic seal)
• Leads are typically plug-in type, SIP, DIP, PGA, etc.
Mixed Technologies
Another category of assembly technique recognized as “mixed technologies” combines chip-and-wire
with surface-mount assembly techniques on a single substrate, which may be a glass-epoxy board or
ceramic substrate. Heat sink/heat spreaders are available in a variety of materials.
The Maxtek module shown in Fig. 12.7 includes a 4-layer, 20-mil-thick glass-epoxy board mounted
to a beryllium copper heat spreader.
Selectively gold plated for wire bonding pads and pads at each end for use with elastomeric connectors,
• Three methods of IC die attach
• Epoxied directly to glass-epoxy board
• Epoxied directly to the BeCu heat spreader through a cutout in the board
• Epoxied to the head spreader, through a cutout, via a thermally conductive submount, to electri-
cally isolate the die from the heat spreader
• Solder-mounted resistors and capacitors
• 50-ohm differential signal lines
• IC die may be “glob topped” or covered in either a ceramic or plastic lid for protection
Special Modules
Under special modules we can emphasize and highlight technologies of complex assemblies of mixed-
technology substrates, flexible circuits, and/or electromechanical components. (See Fig. 12.8.) Com-
plex assemblies of mixed-technology substrates often utilize a B-stage epoxy lid or glob top over
chip-and-wire circuitry. These technologies enable designers to provide integrated solution complex
system problems as in a module shown on page 22 which is CRT Driver System capable of displaying
4 million pixels with 1.5-ns rise and fall times. The circuit incorporates a thin-film MCM connected
by a special high-frequency connector to an FR-4 board with thick-film ceramic low-inductance load
resistor and flex circuit with an integral impedance-matching inductor, connecting directly to the
CRT.19,20
The design engineer of an MCM chip should work with the customer to partition the circuit and
optimize the design to be implemented in MCM technology. Application of technologies for placement,
routing, via minimization, tree searching, and layer estimation will be important to assess at this point.
The general function, purpose, and configuration of the active elements, interconnects, and assembly
technology should also be assessed, along with key materials and critical properties, representative
manufacturing-process flows, potential failure mechanisms, qualification procedures, and design for
testability.
Note that two concepts must be carefully examined for successful MCM production. An MCM design
is initiated by selecting appropriate technologies from the many options available. The basic choices are
for substrate technology and assembly techniques. Design tradeoffs are analyzed, and a preliminary
specification is completed. Following circuit simulation, prototypes are produced and tested. When the
application requires it, an ASIC can be designed to be included in the MCM.
12-12 VLSI: Technology
12.12 Summary
In summary, it is customary to give an answer to the fundamental question: What can multi-chip modules
do for you?… and here is the answer …
MCMs optimize critical design parameters such as speed, density, and temperature, resulting in
performance well beyond PC board design capabilities. By removing discrete component packages and
using more densely packed interconnects, circuit speeds increase. The design challenge is to select the
appropriate packaging technology, and to manage any resulting thermal problems.20
MCM technologies found their way and are utilized in the wireless, fiber, and instrumentation markets
and in space and military programs; and in the real world, they stand in the forefront of best merchant-
market technology.
References
1. W. D. Brown, ELEG 5273 Electronic Packaging, University of Arkansas.
2. P. E. Garrou and I. Turlik, Multichip Module Technology Handbook, McGraw-Hill, 1998.
3. J. H. Reche, “High Density Multichip Interconnect for Advanced Packaging,” Proc. NEPCON West,
1989, 1308
4. N. G. Koopman, T. C. Reiley, and P. A. Totta, “Chip and Package Interconnections,” in Microelec-
tronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989, 361.
5. D. Suranayana et al., “Flip Chip Solder Bump Fatigue Life Enhanced by Polymer Encapsulation,”
Proc. 40th ECTC, 1990, 338
6. J. G. Aday, T. G. Tessier, H. Crews, and J. Rasul, “A Comparative Analysis of High Density PWB
Technologies,” Proc. Int. MCM Conference, Denver, 1996, 239.
7. J. G. Aday, T. G. Tessier, and H. Crews, “Selecting Flip Chip on Board Compatible High Density
PWB Technologies,” Int. J. Microcircuits and Electronic Packaging, vol. 18, No. 4, 1995, 319.
8. Y. Tsukada, S. Tsuchida and Y. Mashimoto, “Surface Laminar Circuitry Packaging,” Proc. 42nd
ECTC, 1992, 22.
9. M. Moser and T. G. Tessier, “High Density PCBs for Enhanced SMT and Bare Chip Assembly
Applications,” Proc. Int. MCM Conference, Denver, 1995, 543.
10. E. Enomoto, M. Assai, Y. Sakaguchi, and C. Ohashi, “High Density Printed Wiring Boards Using
Advanced Fully Additive Processing,” Proc. IPC, 1989, 1.
11. C. Sullivan, R. Funer, R. Rust, and M. Witty, “Low Cost MCM-L for Vehicle Application,” Proc.
Int. MCM Conf., Denver, 1996, 142.
12. W. Schmidt, “A Revolutionary Answer to Today’s and Future Interconnect Challenge,” Proc. Printed
Circuit World Convention VI, San Francisco, CA, 1994, T12-1.
13. D. P. Seraphim, D. E. Barr, W. T. Chen, G. P. Schmitt, and R. R. Tummala, “Printed Circuit Board
Packaging,” in Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989, 853.
14. M. J. Begay, and R. Cantwell, “MCM-L Cost Model and Application Case Study,” Proc. Int. MCM
Conference, Denver, 1994, 332.
15. Compositech Ltd., 120 Ricefield Lane, Hauppauge, NY 11788-2071.
16. H. Holden, “Comparing Costs for Various PWB Build Up Technologies,” Proc. Int. MCM Confer-
ence, Denver, 1996, 15.
17. J. Diekman and M. Mirhej, “Nonwoven Aramid Papers: A New PWB Reinforcement Technology,”
Proc. IEPS, 1990, 123.
18. J. Fjelstad, T. DiStefano, and K. Karavakis, “Multilayer Flexible Circuits with Area Array Intercon-
nections for High Performance Electronics,” Proc. 2nd Int. FLEXCON, 1995, 110.
19. Maxtek, Web site reference: http://www.maxtek.com.
20. J. J. Licari and L. R. Enlow, Hybrid Microcircuit Technology Handbook, July 1988, 25.
13
Channel Hot Electron
Degradation-Delay in
MOS Transistors Due to
Deuterium Anneal
Isik C. Kizilyalli
Lucent Bell Laboratories 13.1 Introduction ......................................................................13-1
13.2 Post-Metal Forming Gas Anneals
Karl Hess in Integrated Circuits ........................................................13-2
University of Illinois at 13.3 Impact of Hot Electron Effects
Urbana-Champaign on CMOS Development ...................................................13-3
Joseph W. Lyding 13.4 The Hydrogen/Deuterium Isotope
University of Illinois at
Effect and CMOS Manufacturing....................................13-4
Urbana-Champaign 13.5 Summary..........................................................................13-12
13.1 Introduction
Hydrogen-related degradation by hot electrons in MOS transistors has been long known and is well
documented.1 It has recently been discovered that the degradation exhibits a giant isotope effect if
hydrogen is substituted by deuterium.2–4 The isotope effect can delay the channel hot-electron degradation
by factors of 10 to 100 and, with the current definition of lifetime, even much beyond that. It therefore
must be an effect different to the known kinetic isotope effect and the standard changes in reaction
velocity of a factor of three or so when hydrogen is substituted by deuterium.
Deuterium is a stable and abundantly available isotope of hydrogen. It is contained at a level larger
than 10–4 in all natural water sources. Its mass is roughly twice that of hydrogen, while all its electronic
energy levels and the related chemistry are identical to that of hydrogen.
The difference in channel hot-electron degradation and lifetime must therefore be due to the mass
difference. There are several possible explanations of the giant isotope effect in degradation.4 The
most probable explanation at low supply voltages (VDD < 3.3 V) is the one first advanced in Ref. 5.
This explanation concerns the dynamics of hydrogen (deuterium) desorption from an Si-H (Si-D)
bond at the silicon–silicon dioxide interface under extreme non-equilibrium conditions — which is
the central cause of the particular degradation discussed here. There are other forms of degradation
known that show no, or a much lesser, isotope effect and are not discussed here. According to Ref.
5, the heated electrons (with a typical energy of several electron volts) excite local vibrations of the
Si–H bond. These vibrations have a very long lifetime of the order of nanoseconds or longer because
the vibrational energy of the Si–H is mismatched to the bulk vibrations in both silicon and silicon
dioxide. Therefore, a high probability exists that other hot electrons will collide with the Si–H and
cause further vibrational excitation until, finally, desorption is accomplished. One vibrational mode
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13-2 VLSI Technology
of Si–D, on the other hand, virtually matches a bulk silicon vibrational energy. Therefore, the local
Si–D vibrations are short lived and it is much less likely that Si–D is excited so much that deuterium
will desorb. The basic science of these processes has meanwhile been investigated (e.g., by scanning
tunneling microscopy) and is consistent with the above description.4 Similar desorption processes
are known from photochemistry, where the energy is provided by photons, and the new aspect here
is only the energy supply by the channel electrons and the extent of the isotope effect due to the
special interface properties. While these considerations apply only under extreme non-equilibrium
conditions, there are also in-equilibrium isotopic differences between the Si–H and Si–D bond, again
due to their vibrational differences.
The question that appears under the initial equilibrium conditions, before the degradation occurs, is
the following. Since many processing steps in MOS technology introduce hydrogen in one form or
another, and since hydrogen densities in the silicon dioxide will be of the order of 1018 cm–3 whether
desired or not, how can the hydrogen be effectively replaced by deuterium? An elementary proof 6 shows
that the equilibrium population of the silicon bond by H or D also depends on the vibrational properties.
Because of the higher vibrational energy of some of the Si-H vibrational modes (compared to deuterium),
hydrogen is less likely to saturate the bond. In fact, if H and D are present at the same density at the
interface, then (around the usual anneal temperature of 425°C) the deuterium is about 10 times more
likely to populate the silicon bond than hydrogen.6
From these facts, it is evident that a relatively simple substitution of hydrogen by deuterium can lead
to very beneficial delays of hot-electron degradation. In the following, we first describe the necessity to
anneal the silicon–silicon dioxide interface with H or D; then we describe the advantages of D for hot
electron degradation and the introduction of D by post-metal anneal procedures. Finally, we describe
confirmations and extensions to more complex introductions of D.
P b + H 2 → P bH + H (13.1)
where PbH is the passivated dangling bond. These measurements indicate that for the oxides grown on
Si-<111>, the density of the interface trap states in the middle of the forbidden gap decreases from
1011–1012 cm–2 eV–1 to about 1010 cm–2 eV–1 after the post-metal anneal process step. The Si-<100>/SiO2
material system, which is technologically more significant, exhibits the same qualitative behavior. The
necessity of post-metallization anneal processing for CMOS technologies is demonstrated in Figs. 13.1
and 13.2 where the measured NMOS threshold voltage (Vth) and transconductance (g sub m) distribu-
tions of a wafer annealed in forming gas (10% H2) is compared with an untreated wafer. The high mean
value and variation of the threshold voltage and reduced channel mobility across the untreated wafer is
a clear indication of the unacceptable levels of interface trap density for CMOS circuit operation and
stability. As described above, MOS transistors under bias can degrade as a result of channel hot (large
kinetic energy) carriers (electrons and holes) stimulating the desorption of the hydrogen that is passi-
vating the dangling bonds at the Si/SiO2 interface. These concerns are exacerbated with the ever-ongoing
scaling efforts for high-performance transistors and added dielectric/metallization (and hence plasma
process damage) layers in integrated circuits.
Channel Hot Electron Degradation-Delay in MOS Transistors 13-3
FIGURE 13.1 Histogram demonstrating the effects of hydrogen anneals on the threshold voltage Vth of NMOS
transistors.
FIGURE 13.2 Same as Fig. 13.1 but for the transconductance gm.
oxide (e.g., |VG|>>VD).12 Threshold voltage shifts in MOS capacitor structures are observed. The damage
induced in this degradation mode is due to both charge trapping within the oxide and the creation of
Si/SiO2 interface trap states. Our initial studies have not identified a clear isotope effect for this mode of
stress test. In this article, only the second stress configuration, namely the channel hot carrier aging of
NMOS transistors, where we have discovered the large isotope effect, is discussed. In this mode of
accelerated stress, threshold voltage instability and channel transconductance degradation in MOS
transistors13 is induced with the aid of hot carriers (electrons and holes with large kinetic energy) using
the source-drain electric field. That is, the Si/SiO2 interface is degraded by hot carriers that are traversing
the device while they gain kinetic energy from the source-drain electric field. The device is biased to
maximize the substrate current (e.g., VG ≈ 1/2VD). The transistor aging is accelerated by stressing the
device using a drain voltage (VD) which is much larger than the intended operating voltage. The hot
carrier lifetime of the transistor is estimated by extrapolating the accelerated stress test results to operating
voltage (peak substrate current specification) conditions. DC, AC, or pulsed DC waveforms are most
commonly used. This mode of accelerated stress tests performed on NMOS transistors typically results
in localized oxide damage, which has been identified as Si/SiO2 interface trap states.14,15 The asymmetry
of the current–voltage characteristics under source-drain reversal indicates that the damaged region is
located near the drain end of the transistor where the electric fields are the largest due to the pinch-off
effect. Moreover, it has been suggested that the generation of the interface trap states is due to hot carrier-
stimulated hydrogen desorption and depassivation of the silicon dangling bonds. Channel hot-carrier
degradation in MOS transistors manifests itself in the form of threshold voltage (Vth)) instability,
transconductance (gm = dIDS/dVGS) degradation, and a change in the subthreshold slope (SI = d lnIDS
/dVGS at VGS < Vth) over time.
Various technological advances have been made to address the problem of MOS transistor degradation
due to channel hot carriers. Most significant and lasting progress in fabrication technology to alleviate the
channel hot carrier problem has been the development of lightly doped source-drain (LDD) and gate
sidewall spacer processes.15–17 The lightly doped drain region is used to reduce the strength of the electric
field at the gate-end of the drain. Such advances have been integrated in all submicron CMOS technologies
at the cost of added process complexity and intricate device design.18 Unfortunately, processing requirements
for good short channel behavior and high performance, namely, shallow source-drain junctions, reduced
overlap capacitance, and low source-access resistance, are all at odds with hot carrier immune device design.
A reasonable argument (now it appears that this was merely wishful thinking) had been that the hot
carrier degradation effect can be scaled away by reducing the supply voltage (constant field scaling).
However, this does not appear to be the case since device feature size scaling accompanies supply voltage
scaling in VLSI CMOS technologies to achieve improved performance and increased packing density.
Gate oxide thickness is also reduced to maintain the device current density at low supply voltage operation.
Takeda et al. have observed device degradation in a no-LDD NMOS transistor structure with gate lengths
of 0.3 µm at 2.5 V.19 Chung et al. observed hot carrier degradation for a 0.15-µm gate length transistor
(with no LDD regions) at 1.8 V.20 Current state-of-the-art high-performance 1.5- and 1.8-V sub-0.18-
µm CMOS technology with good quality gate oxide exhibits hot carrier degradation effects and requires
precise drain engineering.21,22 Circuit solutions to alleviate hot carrier degradation effects in transistors,
although proposed, involve further circuit design and layout complications.23 Hot carrier-induced tran-
sistor degradation will continue to be a major roadblock for satisfying market demand for high-perfor-
mance CMOS circuits such as the Lucent-DSP shown in Fig. 13.3 with transistor gate lengths phase-
shifted down to 0.1 µm and operated at a large range of supply voltages (1.0 to 1.8 V).
FIGURE 13.3 High-performance CMOS circuit with 0.1-µm gate length operated in a range of 1.0 V to 1.8 V of
supply voltages.
CMOS scaling is enabled by eliminating the undesirable effects of channel hot carriers. The giant
hydrogen/deuterium isotope effect that has been discovered and reported by Lyding, Hess, and Kizilyalli2,3
in NMOS transistors is the extremely significant increase in time-dependent channel hot carrier transistor
(reliability) lifetime in devices that have been annealed with deuterium instead of hydrogen, as shown
in Figs. 13.4 and 13.5. In the fabrication sequence, deuterium is introduced, instead of hydrogen, to the
Si/SiO2 interface via a low-temperature (400–450°C) post-metallization anneal process. Figure 13.6 shows
the transfer characteristics of uncapped NMOS and PMOS transistors annealed in deuterium and hydro-
gen ambients at 400°C and 1 hour. Prior to hot electron stress, transistors annealed in either ambient
are electrically identical. This results in indistinguishable device function prior to hot carrier stress.
Indistinguishable device function prior to hot carrier stress is also demonstrated in two experiments
shown in Table 13.1. This is an expected result since the chemistry of deuterium and hydrogen is virtually
identical. These results prove that deuterium and hydrogen are equally effective in reducing the interface
trap charge density which results in equivalent device function. Deuterium can be substituted for hydro-
gen (at least in post-metal anneal processes) in semiconductor manufacturing.
Although devices annealed either in deuterium or hydrogen appear to be identical in pre-stress
electrical tests, they exhibit markedly different degradation dynamics. The observed improvement in the
degradation rates (lifetimes) in the transistors is a result of the large difference in the desorption rates
of the two isotopes, as described in the introduction and in detail in Refs. 4 and 5.
The large hydrogen/deuterium isotope effect in NMOS transistors has been subsequently observed
and verified by other laboratories.24–27 Studies also indicate that transistors annealed in deuterium are
much more resilient against plasma process-induced damage (as quantified by Si/SiO2 interface trap
generation and gate oxide leakage).28 Furthermore, stability of PMOS transistors;29 hydrogenated (deu-
terated) amorphous silicon-based solar cells and TFTs;30–32 hydrogen (deuterium) terminated, porous-
silicon light-emitting devices;33 and ultra-thin oxides for non-volatile memory devices34 have been found
to improve with the isotopic substitution against degradation due to light and field exposure.
13-6 VLSI Technology
FIGURE 13.4 Transconductance channel hot-electron accelerated stress degradation with hydrogen and deuterium
anneal and a significant degradation delay due to the presence of deuterium.
FIGURE 13.5 Same as Fig. 13.4 but for the threshold voltage.
For reasons outlined above, there is a strong motivation to introduce the deuterium anneal process
to CMOS manufacturing. However, two further obstacles need to be removed for transfer of process to
the factory floor. First, all modern CMOS technologies require a minimum of three levels of dielec-
tric/metal interconnect process. Anneal processes that are found to be effective for improving channel
Channel Hot Electron Degradation-Delay in MOS Transistors 13-7
FIGURE 13.6 Subthreshold current IDS as a function of gate voltage VG for both hydrogen and deuterium anneal
before degradation. No difference is shown within the experimental accuracy.
hot carrier reliability in one-level of metal/dielectric structures (e.g., 400°C for 0.5 hr and 10% D2/
90% N2) may be ineffective for multi-level metal/dielectric structures. The deuterium anneal process
needs to be (and in some cases has been) optimized for multi-level interconnect. Second, the benefits of
the deuterium anneal should be still evident subsequent to the final SiN cap wafer passivation process.
The test vehicle used for the experiments to surmount these challenges is a development version of
Lucent Technologies 0.35 µm 3.3 V transistors with a 65 Å gate oxide, very shallow arsenic implanted
MDD regions, TEOS spacers, and three dielectric (doped and undoped plasma enhanced TEOS) and
metal levels (Ti/TiN/AlCuSi/TiN).35 The deuterium (5–100% D2) anneal process was performed after the
third layer of metal had been patterned. The deuterium anneal temperatures vary between 400 to 450°C
and anneal times of 1/2 to 5 hours are considered. Accelerated hot carrier DC stress experiments are
performed on NMOS transistors at peak substrate current conditions. In Fig. 13.7, the time-dependent
deviation of Vth is shown with the deuterium anneal conditions as a parameter. Table 13.2 summarizes
the results of all stress experiments (VDS = 5 V and VGS = 2 V), assuming a degradation criteria of δVth
= 200 mV. The degradation dynamics of Si and ID,SAT are plotted in Figs. 13.8 and 13.9. Degradation in
the transistor I–V characteristics is accompanied by an increase in the interface trap density (Dit) as
extracted (Fig. 13.10) from charge-pump current measurements. Figure 13.11 shows hot electron deg-
radation lifetime versus substrate current with 20% gm (transconductance) degradation as the lifetime
criteria. For a peak substrate current specification of ISUB = 2000 nA/µm, the extrapolated lifetime for
the hydrogen and deuterium annealed device is 0.06 years and 4 years, respectively. The hot carrier
lifetime (reliability) of transistors increases continuously and dramatically with increases in deuterium
anneal times and temperatures. Negligible improvement is observed for short (1/2 hour) and low con-
centration (<10% D2) anneal conditions. The 400°C, 2-hour process results in a four-fold improvement
in lifetime over the standard hydrogen process, while the 450°C, 3-hour deuterium anneal process yields
nearly a factor of 50 improvement. Hence, whenever the deuterium content in the wafer is increased,
large corresponding improvements in transistor lifetimes are measured. For longer (450°C, and 5-hour)
13-8 VLSI Technology
FIGURE 13.7 Degradation improvements by deuterium anneal after three levels of metallization for various tem-
peratures and times. Only one hydrogen curve is shown; annealing with hydrogen gives identical results over wide
ranges of temperature and time.
TABLE 13.2 Relative Hot Carrier Reliability (Lifetime) Improvement and D2 Anneals
Temperature Time Ambient N2 Pre-anneal Lifetime
425°C 2 hr 10%H2/90%N2 No 1.0
400°C 1/2 hr 5%D2/95%N2 No 1.0
400°C 1 hr 5%D2/95%N2 No 1.0
400°C 1 hr 10%D2/90%N2 No 1.0
400°C 2 hr 100%D2 Yes 3.8
400°C 3 hr 100%D2 No 5.5
425°C 3 hr 100%D2 No 12.5
450°C 2 hr 100%D2 Yes 36.0
450°C 3 hr 20%D2/80%N2 No 37.5
450°C 3 hr 100%D2 No 62.5
450°C 5 hr 100%D2 No 80.0
anneals, the lifetime improvement asymptotically reaches a factor of about 80 to 100 over the standard
process, corresponding to similar findings in basic experiments using scanning tunneling microscopy.4
In Fig. 13.12, it is demonstrated that the benefits of the deuterium anneal are still observed even if the
post-metal anneal is followed by an SiN caps process. Similar findings for higher levels of metallization
were made by other groups (see Ref. 27). For ultimate stability against further processing, and to avoid
the complicated diffusion through many layers of metallization, it may be necessary to introduce the
deuterium in a layer close to the device that can act as a reservoir and is activated in any temperature
increase (anneal). A convincing proof of this possibility has been given.36
Figure 13.13 shows a hydrogen and deuterium profile as measured by surface ion mass spectroscopy
for a successfully treated transistor. A deuterium peak concentration at the interface is a typical necessity
for successful anneal. The absolute concentrations may vary according to experimental conditions.
These experiments prove that one can substitute deuterium for hydrogen in a CMOS manufacturing
process with no penalty, yet with a 50 to 100-fold improvement in channel hot carrier lifetime. For
Channel Hot Electron Degradation-Delay in MOS Transistors 13-9
FIGURE 13.10 Interface trap density Dit extracted from charge-pump current measurements vs. stress time with
hydrogen and deuterium anneal as indicated.
FIGURE 13.11 Channel hot electron lifetime (20% gm degradation as lifetime limit) vs. substrate current for both
hydrogen and deuterium anneal with extrapolations to actual operating conditions (dashed vertical line).
completeness, other transistor structures with varying design considerations have been evaluated and
summarized elsewhere.37,38 Transistor parameters that were explored include: (1) gate oxide thickness tox
= 50–115 Å, (2) LDD implant species arsenic and phosphorus, (3) gate stack structure of n+-polysilicon
Channel Hot Electron Degradation-Delay in MOS Transistors 13-11
FIGURE 13.12 As in Fig. 13.11 but after final SiN cap process.
and polycide (n+-polysilicon/WSi), and (4) an experimental 0.25-µm 3.3-V CMOS39 process with 4 levels
of metal. In all cases, the large isotope effect is observed. Clearly, the hydrogen/deuterium isotope effect
is a general property of the semiconductor device wear-out.
It is important to correlate the observed improved hot carrier reliability to the location and quantity
of deuterium in the wafer. Secondary ion mass spectroscopy (SIMS) analysis through the first interlevel
oxide and silicon was performed on two uncapped (it is well known that Six Ny is a barrier for deuterium)
samples as shown in Fig. 13.13. The first wafer was annealed in forming gas (10% molecular hydrogen),
while the other sample was annealed in forming gas comprising 10% molecular deuterium. A Cameca
IMS-2f system with oxygen primary beam 60 µm2 was used for analysis. 180+ was monitored to locate
the SiO2/Si interface. The 2D+ concentration is inferred from the difference between the 2H+ profiles for
wafers annealed in deuterium and hydrogen. Deuterium was not detected under large areas of (200 times
200 µm2) polysilicon in wafers that were annealed in deuterium and were not capped with SixNy. This
indicates the finite lateral diffusion length of deuterium in the transistor gate oxide and channel region.
Deuterium is detected in the interlevel oxide at concentrations of 1019 cm–3 and was found to accumulate
at Si/SiO2 interfaces with a surface concentration of 1014 cm–2. This SIMS study suggests that deuterium
diffuses rapidly through the interlevel oxides and the gate sidewall spacers to passivate the interface states
in the transistor channel region. However, the exact lateral spread (reach) of diffused deuterium in the
transistor-channel and gate-oxide region is not certain.
The question still remains regarding the purity, specification limits, as well as cost for implementing
deuterium gas in semiconductor manufacturing. Deuterium is a stable isotope of hydrogen and is
present as D2O. Deuterium gas is produced by electrolysis of pure D2O. Tritium is a radioactive isotope
of hydrogen and has a lifetime of 12.3 years. Because of the nature of the electrolysis, the molar
concentration of tritium in the gas will be essentially the same as the feed heavy water with the tritium
gas being in the form of DT rather than pure T2. If the tritium content in the feed water is 50 nCi/kg,
the expected concentration in the gas would be about 45 pCi/L (1.65 Bq/L). The tritium content in
heavy water varies from 5 nCi/kg (virgin heavy water) to 50 Ci/kg (heavy water used in nuclear reactors).
The limit of tritium in deuterium gas suitable for CMOS manufacturing is estimated as follows. When
13-12 VLSI Technology
FIGURE 13.13 Typical results for hydrogen and deuterium concentrations measured after anneals by secondary
ion mass spectroscopy (SIMS).
1014 deuterium atoms are placed in a single chip, 3 × 10–9 Bq/L of tritium are also incorporated. This
implies that one tritium decay event would occur approximately every 370 days, much below the rate
of other radioactive events occurring in chip technology and operation. In addition, this is only a β-
decay with usually negligible consequences. Since it is very difficult to measure tritium gas at these
low concentrations, specifications should be placed on the tritium content for the heavy water used
in the electrolytic production process (which is straightforward). A suggested upper limit could be
6000 nCi/kg that results in 1 tritium event/month per chip.40 The substitution of deuterium for
hydrogen adds 0.1% to the total wafer cost.
13.5 Summary
It has been demonstrated that the replacement of hydrogen by deuterium in CMOS technology can lead
to significant delays in channel hot electron degradation. Increases in hot electron lifetime of a factor of
10 to 100 and beyond have been shown by simple post-metal anneals in deuterium atmosphere for several
levels of metallization. Deuterium has also been proven beneficial for the reliability of other devices such
as deuterated amorphous thin-film silicon devices of various kinds. Since deuterium and hydrogen have
the same electronic energy levels, deuterium- and hydrogen-treated devices are indistinguishable in terms
of their normal pre-stress electronic characteristics. Deuterium only delays degradation due to its higher
mass and different vibrational properties.
Acknowledgments
K. H. and J. W. Lyding acknowledge financial support from the Office of Naval Research under the
MURI program.
Channel Hot Electron Degradation-Delay in MOS Transistors 13-13
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14
Materials
14.1 Introduction
Very-high-speed digital integrated circuit design is a multidisciplinary challenge. First, there are several
IC technologies available for very-high-speed applications. Each of these claims to offer unique benefits
to the user. In order to choose the most appropriate or cost-effective technology for a particular appli-
cation or system, the designer must understand the materials, the devices, the limitations imposed by
process on yields, and the thermal limitations due to power dissipation.
Second, very-high-speed digital ICs present design challenges if the inherent performance of the devices
is to be retained. At the upper limits of speed, there are no digital circuits, only analog. Circuit design
techniques formerly thought to be exclusively in the domain of analog IC design are effective in optimizing
digital IC designs for highest performance.
Finally, system integration when using the highest-speed technologies presents an additional challenge.
Interconnections, clock and power distribution both on-chip and off-chip require much care and often
restrict the achievable performance of an IC in a system.
The entire scope of very-high-speed digital design is much too vast to present in a single tutorial
chapter. Therefore, we must focus the coverage in order to provide some useful tools for the designer.
We will focus primarily on compound semiconductor technologies in order to restrict the scope. Silicon
IC design tutorials can be found in other chapters in this handbook. This chapter gives a brief introduction
to compound semiconductor materials in order to justify the use of non-silicon materials for the highest-
speed applications. The transport properties of several materials are compared. Second, a technology-
independent description of device operation for high-speed or high-frequency applications will be given
in Chapter 15. The charge control methodology provides insight and connects the basic material prop-
erties and device geometry with performance. Chapter 16 describes the design basics of very-high-speed
ICs. Static design methods are illustrated with compound semiconductor circuit examples, but are based
on generic principles such as noise margin. The transient design methods emphasize analog circuit
techniques and can be applied to any technology.
Finally, Chapter 17 describes typical circuit design approaches using FET and bipolar device technol-
ogies and presents applications of current interest.
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 14-1
14-2 VLSI Technology
elements such as C, Si, and Ge are used as dopants, as are several group TABLE 14.1 Column III, IV,
II and VI elements such as Be or Mg for p-type and Te and Se for n- and V Elements Associated with
type. Binary semiconductors such as GaAs and InP can be grown in Compound Semiconductors
large single-crystal ingot form using the liquid-encapsulated Czochral-
B C N
ski method1 and are the materials of choice for substrates. At the Al Si P
present time, GaAs wafers with a diameter of 100 and 150 mm are Ga Ge As
most widely used. InP is still limited to 75 mm diameter. In Sn Sb
Three or four elements are often mixed together when grown as
thin epitaxial films on top of the binary substrates. The alloys thus
formed allow electronic and structural properties such as bandgap and lattice constant to be varied as
needed for device purposes. Junctions between different semiconductors can be used to further control
charge transport as discussed in Section 14.4.
FIGURE 14.1 Electron velocity versus electric field for several n-type semiconductors.
Materials 14-3
TABLE 14.2 Comparison of Mobilities and Peak Velocities of Several n- and p-type Semiconductors
EG εr Electron Mobility Hole Mobility Peak Electron Velocity
Semiconductor (eV) (cm2/V-s) (cm2/V-s) (cm/s)
Note: In bandgap energy column, the symbol “D” indicates direct bandgap; otherwise, it is indirect bandgap.
T = 300 K and “weak doping” limit.
On the other hand, as also shown in Table 14.2, p-type III-V semiconductors have rather poor hole
mobility when compared with elemental semiconductor materials such as silicon or germanium. Holes
also reach their peak velocities at much higher electric fields than electrons. Therefore, p-type III-V
materials needed for the base of a bipolar transistor, for example, are used, but their thickness must be
extremely small to avoid degradation in transit time. Lateral distances must also be small to avoid excessive
series resistance. CMOS-like complementary FET technologies have also been developed,2 but their
performance has been limited by the poorer speed of the p-channel devices.
14.4 Heterojunctions
In the past, most semiconductor devices were composed of a single
semiconductor element, such as silicon or gallium arsenide, and
employed n- and p-type doping to control charge transport.
Figure 14.2(a) illustrates an energy band diagram of a semiconductor
with uniform composition that is in an applied electric field. Electrons
will drift downhill and holes will drift uphill in the applied electric
field. The electrons and/or holes could be produced by doping or by
ionization due to light. In a heterogeneous semiconductor as shown
in Fig. 14.2(b), the bandgap can be graded from wide bandgap on the
left to narrow on the right by varying the composition. In this case,
even without an applied electric field, a built-in quasi-electric field is
produced by the bandgap variation that will transport both holes and
electrons in the same direction.
The abrupt heterojunction formed by an atomically abrupt transi-
tion between AlGaAs and GaAs, shown in the energy band diagram
of Fig. 14.3, creates discontinuities in the valence and conduction
bands. The conduction band energy discontinuity is labeled ∆EC and
the valence band discontinuity, ∆EV . Their sum equals the energy
bandgap difference between the two materials. The potential energy FIGURE 14.2 (a) Homogeneous
steps caused by these discontinuities are used as barriers to electrons semiconductor in uniform electric
or holes. The relative sizes of these potential barriers depend on the field, and (b) Heterogeneous semi-
composition of the semiconductor materials on each side of the het- conductor with graded energy gap.
erojunction. In this example, an electron barrier in the conduction No applied electric field.
band is used to confine carriers into a narrow potential energy well
with triangular shape. Quantum well structures such as these are used
14-4 VLSI Technology
to improve device performance through two-dimensional charge transport channels, similar to the role
played by the inversion layer in MOS devices. The structure and operation of heterojunctions in FETs
and BJTs will be described in Chapter 15.
The overall principle of the use of heterojunctions is summarized in a Central Design Principle:
“Heterostructures use energy gap variations in addition to electric fields as forces acting on holes
and electrons to control their distribution and flow.” 3,4
The energy barriers can control motion of charge both across the heterojunction and in the plane of the
heterojunction. In addition, heterojunctions are most widely used in light-emitting devices, since the
compositional differences also lead to either stepped or graded index of refraction, which can be used
to confine, refract, and reflect light. The barriers also control the transport of holes and electrons in the
light-generating regions.
Figure 14.4 shows a plot of bandgap versus lattice constant for many of the III-V semiconductors.3
Consider GaAs as an example. GaAs and AlAs have the same lattice constant (approximately 0.56 nm)
but different bandgaps (1.4 and 2.2 eV, respectively). An alloy semiconductor, AlGaAs, can be grown
epitaxially on a GaAs substrate wafer using standard growth techniques. The composition can be selected
by the Al-to-Ga ratio, giving a bandgap that can be chosen across the entire range from GaAs to AlAs.
Since both lattice constants are essentially the same, very low lattice mismatch can be achieved for any
FIGURE 14.4 Energy bandgap versus lattice constant for compound semiconductor materials.
Materials 14-5
composition of AlxGa1-xAs. Lattice matching permits low defect density, high-quality materials to be
grown that have good electronic and optical properties. It quickly becomes apparent from Fig. 14.4,
however, that a requirement for lattice matching to the substrate greatly restricts the combinations of
materials available to the device designer. For electron devices, the low mismatch GaAs/AlAs alloys,
GaSb/AlSb alloys, Al.48In.52As/InP/Ga.47In.53As, and GaAs/In.49Ga.51As combinations alone are available.
Efforts to utilize combinations such as GaP on Si or GaAs on Ge that lattice match have been generally
unsuccessful because of problems with interface structure, polarization, and autodoping.
For several years, lattice matching was considered to be a necessary condition if mobility-damaging
defects were to be avoided. This barrier was later broken when it was discovered that high-quality
semiconductor materials could still be obtained although lattice-mismatched if the thickness of the
mismatched layer is sufficiently small.5,6 This technique, called pseudomorphic growth, opened another
dimension in III-V device technology, and allowed device structures to be optimized over a wider range
of bandgap for better electron or hole dynamics and optical properties.
Two of the pseudomorphic systems that have been very successful in high-performance millimeter-
wave FETs are the InAlAs/InGaAs/GaAs and InAlAs/InGaAs/InP systems. The InxGa1-x As layer is respon-
sible for the high electron mobility and velocity which both improve as the In concentration x is increased.
Up to x = 0.25 for GaAs substrates and x = 0.80 for InP substrates have been demonstrated and result
in great performance enhancements when compared with lattice-matched combinations.
References
1. Ware, R., Higgins, W., O’Hearn, K., and Tiernan, M., Growth and Properties of Very Large Crystals
of Semi-Insulating Gallium Arsenide, presented at 18th IEEE GaAs IC Symp., Orlando, FL, 54, 1996.
2. Abrokwah, J. K., Huang, J. H., Ooms, W., Shurboff, C., Hallmark, J. A. et al., A Manufacturable
Complementary GaAs Process, presented at IEEE GaAs IC Symposium, San Jose, CA, 127, 1993.
3. Kroemer, H., Heterostructures for Everything: Device Principles of the 1980s?, Japanese J. Appl.
Phys., 20, 9, 1981.
4. Kroemer, H., Heterostructure Bipolar Transistors and Integrated Circuits, Proc. IEEE, 70, 13, 1982.
5. Matthews, J. W. and Blakeslee, A. E., Defects in Epitaxial Multilayers. III. Preparation of Almost
Perfect Layers, J. Crystal Growth, 32, 265, 1976.
6. Matthews, J. W. and Blakeslee, A. E., Coherent Strain in Epitaxially Grown Films, J. Crystal Growth,
27, 118, 1974.
15
Compound
Semiconductor Devices
for Digital Circuits
15.1 Introduction ......................................................................15-1
15.2 Unifying Principle for Active Devices: Charge
Control Principle...............................................................15-1
15.3 Comparing Unipolar and Bipolar Transistors ................15-6
Charge Transport in Semiconductors • Field-Effect
(Unipolar) Transistor • Bipolar Junction Transistors
(Homojunction and Heterojunction) • Comparing
Parameters
15.4 Typical Device Structures ...............................................15-13
Donald B. Estreich FET Structures • FET Performance • Heterojunction Bipolar
Hewlett-Packard Company Structures • HBT Performance
15.1 Introduction
An active device is an electron device, such as a transistor, capable of delivering power amplification by
converting dc bias power into time-varying signal power. It delivers a greater energy to its load than if
the device were absent. The charge control framework1-3 discussed below presents a unified understanding
of the operation of all electron devices and simplifies the comparison of the several active devices used
in digital integrated circuits.
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© 2003 by CRC Press LLC 15-1
15-2 VLSI Technology
FIGURE 15.1 Generic charge control device consisting of three electrodes embedded around a charge transport
region.
electrode and the collecting electrode forms a feedback or output capacitance, say Co . Time variation of
QC leads to the modulation of the current flow between emitting and collecting electrodes.
The generic structure in Fig. 15.1 could represent any one of a number of active devices (e.g., vacuum
tubes, unipolar transistors, bipolar transistors, photoconductors, etc.). Hence, charge control analysis is
very broad in scope, since it applies to all electronic transistors.
Starting from the charge control principle, we associate two characteristic time constants with an active
device, thereby leading to a first-order description of its behavior. Application of a potential difference
between the emitting and collecting electrodes, say VCC , establishes an electric field in the transport region.
Electrons in the transport region respond to the electric field and move across this region with a transit
time τr . The transit time1 is the first of the two important characteristic times used in charge control
modeling. With charge –Q in the transit region, the static (dc) current Io between emitting and collecting
electrodes is
Io = –Q/τr = Qc/τ r (15.1)
A simple interpretation of τr is as follows: τr is equal to the length l of the transport region, divided by
the average velocity of transit (i.e., τr = l/〈v〉). From this perspective, a charge of –Q (coulombs) is swept
out of the collecting electrode every τr seconds.
Now consider Fig. 15.2, showing the common-emitting electrode connection of the active device of
Fig. 15.1 connected to input and output (i.e., load) resistances, say Rin and RL , respectively. The second
characteristic time of importance can now be defined: It is the lifetime time constant, and we denote it by τ.
It is a measure of how long a charge placed on the control electrode will remain on the control terminal.
The lifetime time constant is established in one of several ways, depending on the physics of the active device
and/or its connection. The controlling charge may “leak away” by (1) discharging through the external resistor
Rin as typically happens with FET devices, (2) recombining with intermixed oppositely charged carriers within
the device (e.g., base recombination in a bipolar transistor), or (3) discharging through an internal shunt
leakage path within the device. The dc current flowing to replenish the lost control charge is given by
The static (dc) current gain GI of a device is defined as the current delivered to the output, divided by
the current replenishing the control charge during the same time period. Where in τ seconds charge –Q
is both lost and replenished, charge Qc times the ratio τ/τr has been supplied to the output resistor RL .
In symbols, the static current gain is
1The transit time τr is best interpreted as an average transit time per carrier (electron). We note that 1/τr is
common to all devices — it is related to a device’s ultimate capability to process information.
Compound Semiconductor Devices for Digital Circuits 15-3
FIGURE 15.2 Generic charge control device of Fig. 15.1 connected to input and output resistors, Rin and RL ,
respectively, with bias voltage and input signal applied.
⎛ ∂Io ⎞ ⎛ ∂I ⎞ ⎛ ∂Q ⎞
gm = ⎜ ⎟ =⎜ o⎟ ⋅⎜ ⎟ (15.4)
⎝ ∂v in ⎠ v ⎝ ∂Q ⎠ ⎝ ∂v in ⎠
o
The first partial derivative on the right-hand side of Eq. 15.4 is simply (1/τr), and the second partial
derivative is Ci . Hence, the transconductance gm is the ratio
Ci
gm = (15.5)
τi
A physical interpretation of gm is the ratio of the work required to introduce a charge carrier to the
average transit time of a charge carrier in the transport region. The transconductance is one of the most
commonly used device parameters in circuit design and analysis.
In addition to Ci , another capacitance, say Co , is introduced and associated with the collecting electrode.
Capacitance Co accounts for charge on the collecting electrode coupled to either static charge in the
transport region or charge on the control electrode. A non-zero Co indicates that the coupling between
the controlling electrode and the charge in transit is less than unity (i.e., ⎮–Q⎮ < ⎮QC⎮).
For small-signal analysis the capacitance parameters are usually taken at fixed numbers evaluated about
the device’s bias state. When using charge control in the large-signal case, the capacitance parameters
15-4 VLSI Technology
FIGURE 15.3 Two-port, small-signal, admittance charge control model with the emitting electrode selected as the
common terminal to both input and output.
must include the voltage dependencies. For example, the input capacitance Ci can be strongly dependent
upon the control electrode to emitting electrode and collecting electrode potentials. Hence, during the
change in bias state within a device, the magnitude of the capacitance Ci is time varying. This variation
can dramatically affect the switching speed of the active device. Parametric dependencies on the instan-
taneous bias state of the device are at the heart of accurate modeling of large-signal or switching behavior
of active devices.
We introduce the small-signal admittance charge control model shown in Fig. 15.3. This model uses the
emitting electrode as the common terminal in a two-port connection. The transconductance gm is the
magnitude of the real part of the forward admittance yf and is represented as a voltage-controlled current
source positioned from collecting-to-emitting electrode. The input admittance, denoted by yi , is equiv-
alent to (Ci /τ), where τ is the control charge lifetime time constant. Parameter yi can be expressed in the
form (gi + sCi) where s = jω. An output admittance, similarly denoted by yo, is given by (Co/τr) where τr
is the transit time and, in general yo = (go + sCo). Finally, the output-to-input feedback admittance yr is
included using a voltage-controlled current source at the input. Often, yr is small enough to approximate
as zero (the model is then said to be unilateral).
Consider the frequency dependence of the dynamic (ac) current gain Gi. The low-frequency current
gain is interpreted as follows: an incremental charge qc is introduced on the control electrode with lifetime
τ. This produces a corresponding incremental charge –q in the transport region. Charge –q is swept
across the transport region every transit time τr seconds. In time τ, charge –q crosses the transit region
τ/τr times, which is identically equal to the low-frequency current gain.
The lifetime τ associated with the control electrode arises from charge “leaking off ” the controlling
electrode. This is modeled as an RC time constant at the input of the equivalent circuit shown in
Fig. 15.4(a) with τ equal to ReqCi . Req is the equivalent resistance presented to capacitor Ci . That is, Req
is determined by the parallel combination of 1/gi and any external resistance at the input. The break
frequency ωB associated with the control electrode is
1 1
ωB = = (15.6)
τ ReqCi
When the charge on the control electrode varies at a rate ω less than ωB , Gi is given by τ/τr because
charge “leaks off ” the controlling electrode faster than 1/ω. Alternatively, when ω is greater than ωB , Gi
Compound Semiconductor Devices for Digital Circuits 15-5
(a)
(b)
FIGURE 15.4 (a) Small-signal admittance model with output short-circuited, and (b) magnitude of the small-
signal current gain Gi plotted as a function of frequency. The unity current gain crossover (i.e., Gi = 1) defines the
parameter fT (or ωT).
decreases with increasing ω because the applied signal charge varies upon the control electrode more
rapidly than 1/τ. In this case, Gi is inversely proportional to ω, that is,
1 ω
Gi = = T (15.7)
ωτ r ω
where ωT is the common-emitter unity current gain frequency. At ω = ωT ( = 2πfT), the ac current gain
equals unity, as illustrated in Fig. 15.4(b).
Consider the current gain-bandwidth product Gi ∆f. A purely capacitive input impedance cannot define
a bandwidth. However, a finite real impedance always appears at the input terminal in any practical
application. Let Ri be the effective input resistance of the device (i.e., Ri will be equal to (1/gi) in parallel
with the external resistance Rin). Since the input current is equal to qc /τ and the output current is equal
to q/τr , the current gain-bandwidth product becomes
q τr ω
Gi ⋅ ∆f = (15.8)
q c τ 2π
1 ω
Gi ⋅ ∆f = = T = fT (15.9)
2πτ r 2π
fT (or ωT) is a widely quoted parameter used to compare or “benchmark” active devices. Sometimes, fT
(or ωT) is interpreted as a measure of the maximum speed a device can drive a replica of itself. It is easy
to compute and historically has been easy to measure with bridges and later using S-parameters. However,
fT does have interpretative limitations because it is defined as current into a short-circuit output. Hence,
it ignores input resistance and output capacitance effects upon actual circuit performance.
Likewise, voltage and power gain expressions can be derived. It is necessary to define the output
impedance before either can be quantified. Let Ro be the effective output resistance at the output terminal
15-6 VLSI Technology
of the active device. Assuming both the input and output RC time constants to be identical (i.e., RiCi =
RoCo), the voltage gain Gv can be expressed in terms of Gi as
Ro C
G v = Gi = Gi i (15.10)
Ri Co
where Ro is the parallel equivalent output resistance from all resistances at the output node.
The power gain Gp is computed from the product of Gi ⋅Gv along with the power gain-bandwidth
product. These results are listed in Table 15.1 as summarized from Johnson and Rose.1 These simple
expressions are valid for all devices as interpreted from the charge control perspective. They provide for
a first-order comparison, in terms of a few simple parameters, among the active devices commonly
available. From an examination of Table 15.1, it is evident that maximizing Ci and minimizing τr leads
to higher transconductance, higher parametric gains, and greater frequency response. This is an important
observation in understanding how to improve upon the performance of any active device.
Whereas fT has limitations, the frequency at which the maximum power gain extrapolates to unity,
denoted by ωmax , is often a more useful indicator of device performance. The primary limitation of ωmax
is that it is very difficult to calculate and is usually extrapolated from S-parameter measurements in which
the extrapolation is approximate at best.
1 ω
Current amplification Gi ⇔ T
ωτ r ω
1 Ci ω C
Voltage amplification Gv ⇔ T i
ωτ r Co ω Co
1 Ci ω2 C
Power amplification Gp = GiGv ⇔ T2 i
ω τ Co
2 2
r ω Co
Gi⋅∆f 1
Current gain-bandwidth product ⇔ ωT
τr
Gv⋅∆f 1 Ci C
Voltage gain-bandwidth product ⇔ ωT i
τ r Co Co
1 Ci C
Power gain-bandwidth product Gp⋅∆f2 ⇔ ω T2 i
τ r2 Co Co
Note: Table assumes RiCi = RoCo. (After Johnson and Rose (Ref. 1),
March 1959. © 1959 IEEE, reproduced with permission of IEEE.)
Compound Semiconductor Devices for Digital Circuits 15-7
electrode and transport region — in unipolar devices, they are physically separated, whereas in bipolar
devices, they are merged into the same physical region (i.e., base region). Before reviewing the physical
operation of each, transport in semiconductors is briefly reviewed.
FIGURE 15.5 (a) Conceptual view of a field-effect transistor with the channel sandwiched between source and
drain ohmic contacts and a gate control electrode in close proximity; and (b) cross-sectional view of the FET with
a depletion layer shown such as would be present in a compound semiconductor MESFET.
time variation of the drain current (and the source current also). Therefore, transconductance gm is the
natural parameter to describe the FET from this viewpoint.
Fig. 15.6(a) shows the ID-VDS characteristic of the n-channel FET in the common-source connection
with constant electron mobility and a long channel assumed. Two distinct operating regions appear in
Fig. 15.6(a) — the linear (i.e., non-saturated) region, and the saturated region, separated by the dashed
parabola. The origin of current saturation corresponds to the onset of channel pinch-off due to carrier
exclusion at the drain end of the channel. Pinch-off occurs when the drain voltage is positive enough to
FIGURE 15.6 (a) Field-effect transistor drain current (ID) versus drain-to-source voltage (VDS) characteristic with
the gate-to-source voltage (VGS) as a stepped parameter; (b) ID versus VGS “transfer curve” for a constant VDS in the
saturated region of operation, revealing its “square-law” behavior; (c) transconductance gm versus VGS for a constant
VDS in saturated region of operation corresponding to the transfer curve in (b). These curves assume constant mobility,
no velocity saturation, and the “long-channel FET approximation.”
Compound Semiconductor Devices for Digital Circuits 15-9
deplete the channel completely of electrons at the drain end; this corresponds to a gate-to-source voltage
equal to the pinch-off voltage, denoted as –Vp in Figs. 15.6(b) and (c). For constant VDS in the saturated
region, the ID vs. VGS transfer curve approximates “square law” behavior; that is,
2
⎡ V ⎤
I D = I D,sat = I DSS ⎢1 − GS ⎥ for − VP ≤ VGS ≤ ϕ
( )
(15.11)
⎢⎣ − VP ⎥⎦
where IDSS is the drain current when VGS = 0, and ϕ is a built-in potential associated with the gate-to-
channel junction or interface (e.g., a metal-semiconductor Schottky barrier as in the MESFET). The
symbol ID,sat denotes the drain current in the saturated region of operation. Transconductance gm is linear
with VGS for the saturation transfer characteristic of Eq. (15.11) and is approximated by
∂I D D ⎡ V ⎤
gm = ≅ 2 DSS ⎢1 − GS ⎥ for − VP ≤ VGS ≤ ϕ
( )
(15.12)
∂VGS VP ⎢ − VP ⎥⎦
⎣
Equations 15.11 and 15.12 are plotted in Figs. 15.6(b) and (c), respectively.
FIGURE 15.7 (a) Conceptual view of a bipolar junction transistor with the base region sandwiched between emitter
and collector regions. Structure is representative of a compound semiconductor heterojunction bipolar transistor.
(b) Simplified cross-sectional view of a vertically structured BJT device with primary electron flow represented by
large arrow.
FIGURE 15.8 The bandgap diagram for an HBT AlGaAs/GaAs device with the wider bandgap for the AlGaAs
emitter (solid line) compared with a homojunction GaAs BJT emitter (dot-dash line). The double dot-dashed line
represents the Fermi level in each region.
Compound Semiconductor Devices for Digital Circuits 15-11
Jn
Jp
(
∝ exp − ∆E g kT ) (15.13)
For example, ∆Eg equal to 8kT gives an exponential factor of approximately 8000, thereby leading to an
emitter efficiency of nearly unity, as desired. The use of the emitter-base band discontinuity is a very
efficient way to hold high emitter efficiencies.
In bipolar devices, the collector current IC is given by the exponential of the base-emitter forward
voltage VBE normalized to the thermal voltage kT/q
(
IC = IS exp qVBE kT ) (15.14)
The saturation current IS is given by a quantity that depends on the structure of the device; it is inversely
proportional to the base doping charge QBASE and proportional to the device’s area A, namely
qADni2
IS = (15.15)
Q BASE
where the other symbols have their usual meanings (D is the minority carrier diffusion constant in the
base, ni is the intrinsic carrier concentration of the semiconductor, and q is the electron’s charge).
A typical collector current versus collector-emitter voltage characteristic, for several increasing values
of (forward-biased) emitter-base voltages, is shown in Fig. 15.9(a). Note the similarity to Fig. 15.6(a),
FIGURE 15.9 (a) Collector current (IC) versus collector-to-emitter voltage (VCE) characteristic curves with the base-
to-emitter voltage (VBE) as stepped parameter; (b) IC versus VBE “transfer curve” for a constant VCE in saturated region
of operation shows exponential behavior; and (c) transconductance gm versus VBE for a constant VCE in the saturated
region of operation corresponding to the transfer curve in (b).
15-12 VLSI Technology
with the BJT having a quicker turn-on for low VCE values compared with the softer knee for the FET.
The transconductance of the BJT and HBT is found by taking the derivative of Eq. 15.14, thus
gm =
∂IC qI
(
= S exp qVBE kT
∂VBE kT
) (15.16)
Both IC and gm are of exponential form, as observed in Fig. 15.13; Eqs. 15.14 and 15.16 are plotted in
Figs. 15.9(b) and (c), respectively. The transconductance of the BJT/HBT is generally much larger than
that of the best FET devices (this can be verified by comparing Eq. (15.12) with Eq. (15.16) with typical
parameter values inserted). This has significant circuit design advantages for the BJT/HBT devices over
the FET devices because high transconductance is needed for high current drive to charge load capacitance
in digital circuits. In general, higher gm values allow a designer to use feedback to a greater extent in
design and this provides for greater tolerance to process variations.
Comparing Parameters
Table 15.2 compares some of the more important features and parameters of the BJT/HBT device
with the FET device. For reference, a common-source FET configuration is compared with a common-
emitter BJT/HBT configuration. One of the most striking differences is the input impedance param-
eter. A FET has a high input impedance at low to mid-range frequencies because it essentially is a
capacitor. As the frequency increases, the magnitude of the input impedance decreases as 1/ω because
a capacitive reactance varies as ⏐Cgs /ω⏐. The BJT/HBT emitter-base is a forward-biased pn junction,
which is inherently a low impedance structure because of the lowered potential barrier to carriers.
The BJT/HBT input is also capacitive (i.e., a large diffusion capacitance due to stored charge), but a
large conductance (or small resistance) appears in parallel assuring a low input impedance even at
low frequencies.
BJT/HBT devices are known for their higher transconductance gm , which is proportional to collector
current. An FET’s gm is proportional to the saturated velocity vsat and its input capacitance Cgs . Thus,
device structure and material parameters set the performance of the FET whereas thermodynamics play
the key role in establishing the magnitude of gm in a BJT/HBT.
Thermodynamics also establishes the magnitude of the turn-on voltage (this follows simply from
Eq. 15.14) in the BJT/HBT device. For digital circuits, turn-on voltage (or threshold voltage) is important
in terms of repeatability and consistency for circuit robustness. The BJT/HBT is clearly superior to the
FET in this regard because doping concentration and physical structure establish an FET’s turn-on voltage.
In general, these variables are less controllable. However, the forward turn-on voltage in the AlGaAs/GaAs
HBT is higher (~1.4 V) because of the band discontinuity at the emitter–base heterojunction. For InP-
based HBTs, the forward turn-on voltage is lower (~0.8 V) than that of the AlGaAs/GaAs HBT and
comparable to the approximate 0.7 V found in silicon BJTs. This is important in digital circuits because
reducing the signal swing allows for faster circuit speed and lowers power dissipation by allowing for
reduced power supply voltages.
For BJT/HBT devices, current gain (often given the symbol of β or hFE ) is a meaningful and important
parameter. Good BJT devices inject little current into the emitter and, hence, operate with low base
current levels. The current gain is defined as the collector current divided by the base current and is
therefore a measure of the quality of the device (i.e., traps and defects, both surface and bulk, degrade
the current gain due to higher recombination currents). At low to mid-range frequencies, current gain
is not especially meaningful for the high input impedance FET device because of the capacitive input.
The intrinsic gain of an HBT is higher because of its higher Early voltage VA. The Early voltage is a
measure of the intrinsic output conductance of a device. In the HBT, the change in the collector voltage
has very little effect on the modulation of the collector current. This is true because the band discontinuity
dominates the establishment of the current collected at the collector–base junction. A figure of merit is
the intrinsic voltage gain of an active device, given by the product gmVA , and the HBT has the highest
values compared to silicon BJTs and compound semiconductor FETs.
It is important to have a dynamic figure of merit or parameter to assess the usefulness of an active
device for high-speed operation. Both the unity current gain cutoff frequency fT and maximum frequency
of oscillation fmax have been discussed in the charge control section above. Both of these figures of merit
are used because they are simple and can generally be correlated to circuit speed. The higher the value
of both parameters, the better the high-speed circuit performance. This is not the whole story because
in digital circuits other factors such as output node-to-substrate capacitance, external load capacitances,
and interconnect resistance also play an important role in determining the speed of a circuit.
Generally, 1/f noise is much higher in FET devices than in the BJT/HBT devices. This is usually of
more importance in analog applications and oscillators however. Thermal behavior in high-speed devices
is important as designers push circuit performance. Bipolar devices are more susceptible to thermal
runaway than FETs because of the positive feedback associated with a forward-biased junction (i.e., a
smaller forward voltage is required to maintain the same current at higher temperatures). This is not
true in the FET; in fact, FETs generally have negative feedback under common biases used in digital
circuits. Both GaAs and InP have poorer thermal conductivity than silicon, with GaAs being about one-
third of silicon and InP being about one-half of silicon.
Finally, circuits built on GaAs or InP semi-insulating substrates are susceptible to backgating. Back-
gating is similar to the backgate-bias effects in MOS transistors, only it is not as predictable or repeatable
as the well-known backgate-bias effect is in silicon MOSFETs on silicon lightly doped substrates. Inter-
connect traces with negatively applied voltages and located adjacent to devices can change their threshold
voltage (or turn-on voltage). It turns out that HBT devices do not suffer from backgating, and this is
one of their advantages. Of course, semi-insulating substrates are nearly ideal for microstrip transmission
lines on top of the substrates because of their very low loss. Silicon substrates are much more lossy in
comparison and this is a decided advantage in GaAs and InP substrates.
FET Structures
In the silicon VLSI world, the MOSFET (metal-oxide-semiconductor field-effect transistor) dominates. This
device forms a channel at the oxide–semiconductor interface upon applying a voltage to the gate to attract
carriers to this interface.17 The thin layer of mobile carriers forms a two-dimensional sheet of carriers.
One of the limitations with the MOSFET is that the oxide–semiconductor interface scatters the carriers
in the channel and degrades the performance of the MOSFET. This is evident in Fig. 14.1 where the
lower electron velocity at the Si-SiO2 interface is compared with electron velocities in compound semi-
conductors. For many years, device physicists have looked for device structures and materials which
increase electron velocity. FET structures using compound semiconductors have led to much faster devices
such as the MESFET and the HEMT.
The MESFET (metal-semiconductor FET) uses a thin doped channel (almost always n-type because
electrons are much more mobile in semiconductors) with a reverse-biased Schottky barrier for the gate
control.9 The cross-section of a typical MESFET is shown in Fig. 15.10(a). A recessed gate is used along
with a highly doped n+ layer at the surface to reduce the series resistance at both the source and drain
connections. The gate length and electron velocity in the channel dominate in determining the high-
speed performance of a MESFET. Much work has gone into developing processes that form shorter gate
structures. For digital devices, lower breakdown voltages are permissible, and therefore shorter gate
lengths and higher channel doping are more compatible with such devices. For a given semiconductor
material, a device’s breakdown voltage BVGD times its unity current gain cutoff frequency fT is a constant.
Therefore, it is possible to tradeoff BVGD for fT in device design. A high fT is required in high-speed digital
circuits because devices with a high fT over their logic swing will have a high gm /C ratio for large-signal
operation. A high gm /C ratio translates into a device’s ability to drive load capacitances.
It is also desirable to maximize the charge in the channel per unit gate area. This allows for higher
currents per unit gate width and greater ability to drive large capacitive loads. The higher current per
FIGURE 15.10 Typical FET cross-sections for (a) GaAs MESFET device with doped channel, and (b) AlGaAs/GaAs
HEMT device with single quantum well containing and two-dimensional electron gas.
Compound Semiconductor Devices for Digital Circuits 15-15
unit gate width also favors greater IC layout density. In the MESFET, the doping level of the channel sets
this limit. MESFET channels are usually ion-implanted and the added lattice damage further reduces the
electron mobility.
To achieve still higher currents per gate width and even higher figures of merit (such as fT and fmax),
the HEMT (high electron mobility transistor) structure has evolved.10,16 The HEMT is similar to the
MESFET except that the doped channel is replaced with a two-dimensional quantum well containing
electrons (sometimes referred to as a 2-D electron gas). The quantum well is formed by a discontinuity
in conduction band edges between two different semiconductors (such as AlGaAs and GaAs in Fig. 14.3).
From Fig. 14.4 we see that GaAs and Al0.3Ga0.7 As have nearly identical lattice constants but with somewhat
different bandgaps. One compound semiconductor can be grown (i.e., using molecular beam epitaxy or
metalo-organic chemical vapor deposition techniques) on a different compound semiconductor if the
lattice constants are identical. Another example is Ga0.47In0.53 As and InP, where they are lattice matched.
The difference in conduction band edge alignment leads to the formation of a quantum well. The greater
the edge misalignment, the deeper the quantum well can be, and generally the greater the number of
carriers the quantum well can hold. The charge per unit area that a quantum well can hold directly
translates into greater current per unit gate width. Thus, the information in Fig. 14.4 can be used to
bandgap engineer different materials that can be combined in lattice matched layers.
A major advantage of the quantum well comes from being able to use semiconductors that have higher
electron velocity and mobility than the substrate material (e.g., GaAs) and also avoid charge impurity
scattering in the quantum well by locating the donor atoms outside the quantum well itself.
Figure 15.10(b) shows a HEMT cross-section where the dopant atoms are positioned in the wider bandgap
AlGaAs layer. When these donors ionize, electrons spill into the quantum well because of its lower energy.
Higher electron mobility is possible because the ionized donors are not located in the quantum well
layer. A recessed gate is placed over the quantum well, usually on a semiconductor layer such as the
AlGaAs layer in Fig. 15.10(b), allowing modulation of the charge in the quantum well.
There are only a few lattice-matched structures possible. However, semiconductor layers for which the
lattice constants are not matched are possible if the layers are thin enough (of the order of a few
nanometers). Molecular beam epitaxy and MOCVD make it possible to grow layers of a few atomic
layers. Such structures are called pseudomorphic HEMT (PHEMT) devices.10,16 This gives more flexibility
in selecting quantum well layers which hold greater charge and have higher electron velocities and
mobilities. The highest performance levels are achieved with pseudomorphic HEMT devices.
FET Performance
All currently used FET structures are n-channel because hole velocities are very low compared with
electron velocities. Typical gate lengths range from 0.5 microns down to about 0.1 microns for the fastest
devices. The most critical fabrication step in producing these structures is the gate recess width and depth.
The GaAs MESFET (ca. 1968) was the first compound semiconductor FET structure and is still used
today because of its simplicity and low cost of manufacture. GaAs MESFET devices have fT values in the
20 GHz to 50 GHz range corresponding to gate lengths of 0.5 microns down to 0.2 microns, and gm
values of the order of 200 to 400 mS/mm, respectively. These devices will typically have IDSS values of
200 to 400 mA/mm, where parameter IDSS is the common-source, drain current with zero gate voltage
applied in a saturated state of operation.
In comparison, the first HEMT used an AlGaAs/GaAs material structure. These devices are higher
performance than the GaAs MESFET (e.g., given an identical gate length, the AlGaAs/GaAs HEMT has
an fT about 50% to 100% higher, depending on the details of the device structure and quality of material).
Correspondingly higher currents are achieved in the AlGaAs/GaAs HEMT devices.
Higher performance still is achieved using InP based HEMTs. For example, the
In0.53Ga0.47 As/In0.52 Al0.48 As on InP lattice-matched HEMT have reported fT numbers greater than 250 GHz
with gate lengths of the order of 0.1 microns. Furthermore, such devices have IDSS values approaching
1000 mA/mm and very high transconductances of greater than 1500 mS/mm.16,18 These devices do have
15-16 VLSI Technology
low breakdown voltages of the order of 1 or 2 V because of the small bandgap of InGaAs. Changing the
stoichiometric ratios to In0.15Ga0.85 As/In0.15 Al0.30 As on a GaAs substrate produces a pseudomorphic HEMT
structure. The In0.15Ga0.85As is a strained layer when grown on GaAs. The use of strained layers gives the
device designer more flexibility in accessing a wider variety of quantum wells depths and electronic
properties.
HBT Performance
Typical current gain values in production-worthy HBT devices range from 50 at the low range to 150 at
the high range. Cutoff frequency fT values are usually quoted under the best (i.e., peak) bias conditions.
For this reason fT values must be carefully interpreted because in digital circuits, the bias state varies
widely over the entire switching swing. For this reason, probably an averaged fT value would be better,
but it is difficult to determine. Typical fT values for HBT processes in manufacturing (say 1998) are in
FIGURE 15.11 Cross-section of an HBT device with carbon-doped p+ base and an InGaP emitter.14 Note the
commonly used mesa structure, where selective layer etching is required to form contacts to the base and collector
regions.
Compound Semiconductor Devices for Digital Circuits 15-17
the 50 to 150 GHz range. For example, for the HBT example in Fig. 15.11 with a 2 µm × 2 µm emitter
fT is approximately 65 GHz at a current density of 0.6 mA/µm2 and its dc current gain is around 50. Of
course, higher values for fT have been reported for R&D or laboratory devices. In HBT devices, the
parameter fmax is often lower than its fT value (e.g., for the device in Fig. 15.11, fmax is about 75 GHz).
Base resistance (refer to Table 15.2 for equation) is the dominant limiting factor in setting fmax. The best
HBT devices have fmax values only slightly higher than their fT values. In comparison, MESFET and HEMT
devices typically have higher fmax /fT ratios, although in digital circuits this may be of little importance.
Where the HBT really excels is in being able to generate much higher values of transconductance. This
is a clear advantage in driving larger loading capacitances found in large integrated circuits. Biasing the
HBT in the current range corresponding to the highest transconductance is essential to take advantage
of the intrinsically higher transconductance.
References
1. Johnson, E. O. and Rose, A., Simple General Analysis of Amplifier Devices with Emitter, Control,
and Collector Functions, Proc. IRE, 47, 407, 1959.
2. Cherry, E. M. and Hooper, D. E., Amplifying Devices and Low-Pass Amplifier Design, John Wiley &
Sons, New York, 1968, Chap. 2 and 5.
3. Beaufoy, R. and Sparkes, J. J., The Junction Transistor as a Charge-Controlled Device, ATE Journal,
13, 310, 1957.
4. Shockley, W., Electrons and Holes in Semiconductors, Van Nostrand, New York, 1950.
5. Ferry, D. K., Semiconductors, Macmillan, New York, 1991.
6. Lundstrom, M., Fundamentals of Carrier Transport, Addison-Wesley, Reading, MA, 1990.
7. Sze, S. M., Physics of Semiconductor Devices, second ed., John Wiley & Sons, New York, 1981.
8. Yang, E. S., Fundamentals of Semiconductor Devices, McGraw-Hill, New York, 1978, Chap. 7.
9. Hollis, M. A. and Murphy, R. A., Homogeneous Field-Effect Transistors, High-Speed Semiconductor
Devices, Sze, S. M., Ed., Wiley-Interscience, New York, 1990.
10. Pearton, S. J. and Shah, N. J., Heterostructure Field-Effect Transistors, High-Speed Semiconductor
Devices, Sze, S. M., Ed., Wiley-Interscience, 1990, Chap. 5.
10a. Kroemer, H., Heterostructure Bipolar Transistors and Integrated Circuits, Proc. IEEE, 15, 13, 1982.
11. Muller, R. S. and Kamins, T. I., Device Electronics for Integrated Circuits, second ed., John Wiley &
Sons, New York, 1986, Chap. 6 and 7.
12. Gray, P. E., Dewitt, D., Boothroyd, A. R., and Gibbons, J. F., Physical Electronics and Circuit Models
of Transistors, John Wiley & Sons, New York, 1964, Chap. 7.
13. Asbeck, P. M., Bipolar Transistors, High-Speed Semiconductor Devices, S. M. Sze, Ed., John Wiley &
Sons, New York, 1990, Chap. 6.
14. Low, T. S. et al., Migration from an AlGaAs to an InGaP Emitter HBT IC Process for Improved
Reliability, presented at IEEE GaAs IC Symposium Technical Digest, Atlanta, GA, 153, 1998.
15. Jalali, B. and Pearson, S. J., InP HBTs Growth, Processing and Applications, Artech House, Boston,
1995.
16. Nguyen, L. G., Larson, L. E., and Mishra, U. K., Ultra-High-Speed Modulation-Doped Field-Effect
Transistors: A Tutorial Review, Proc. IEEE, 80, 494, 1992.
17. Brews, J. R., The Submicron MOSFET, High-Speed Semiconductor Devices, Sze, S. M., Ed., Wiley-
Interscience, New York, 1990, Chap. 3.
18. Nguyen, L. D., Brown, A. S., Thompson, M. A., and Jelloian, L. M., 50-nm Self-Aligned-Gate
Pseudomorphic AlInAs/GaInAs High Electron Mobility Transistors, IEEE Trans. Elect. Dev., 39,
2007, 1992.
16
Logic Design Principles
and Examples
16.1 Introduction
The logic circuits used in high-speed compound semiconductor digital ICs must satisfy the same essential
conditions for design robustness and performance as digital ICs fabricated in other technologies. The
static or dc design of a logic cell must guarantee adequate voltage and/or current gain to restore the
signal levels in a chain of similar cells. A minimum noise margin must be provided for tolerance against
process variation, temperature, and induced noise from ground bounce, crosstalk, and EMI so that
functional circuits and systems are produced with good electrical yield. Propagation delays must be
determined as a function of loading and power dissipation.
Compound semiconductor designs emphasize speed, so logic voltage swings are generally low, τr low
so that transconductances and fT are high, and device access resistances are made as low as possible in
order to minimize the lifetime time constant τ. This combination makes circuit performance very sensitive
to parasitic R, L, and C, especially when the highest operation frequency is desired. The following sections
will describe the techniques that can be used for static and dynamic design of high-speed logic.
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 16-1
16-2 VLSI Technology
FIGURE 16.1 Typical voltage transfer characteristic for the logic inverter shown in Fig. 16.2.
Ratioed logic implies that the logic high and low voltages VOH and VOL shown in Fig. 16.1 are a function
of the widths W1 and WL of the FETs in the circuit shown in Fig. 16.2. In III-V technologies, this circuit
is implemented with either MESFETs or HEMTs. The circuit in Fig. 16.2 is called Direct Coupled FET
Logic or DCFL.
The logic levels of non-ratioed logic are independent of device widths. Non-ratioed logic typically
occurs when the switching transistors do not conduct any static current. This is typical of logic families
such as static CMOS or its GaAs equivalent CGaAs2 which make use of complementary devices. Dynamic
logic circuits such as precharged logic1 and pass transistor logic2,3 also do not require static current in
pull-down chains. Such circuits have been used with GaAs FETs in order to reduce static power dissipation.
They have not been used, however, for the highest speed applications.
FIGURE 16.3 Drain current versus drain-source voltage characteristic of J1. The active load, J2, is also shown
superimposed over the J1 characteristics as a load line. Two load lines corresponding to wide and narrow J2 widths
are shown. In addition, the gate current IG of J3 versus Vout limits the logic high voltage.
current available to drive any load capacitance, so the inverter with load line 1 will therefore be slower
than the one with load line 2. There is therefore a tradeoff between speed and logic swing. So far, the
analysis of this circuit is the same as that of an analogous nMOS E/D inverter.
In the case of DCFL logic inverters implemented with GaAs-based FETs, the Schottky barrier gate
electrode of the next stage will limit the maximum value of VOH to the forward voltage drop across the
gate-source diode. This is shown by the gate diode IG–VGS characteristic also superimposed on Fig. 16.3.
VOH is given by the point of intersection between the load current IDD and the gate current IG, because
a logic high output requires that the switch transistor J1 is off. VOH will therefore also depend on the
load transistor current. Effort must be made not to overdrive the gate since excess gate current will flow
through the internal parasitic source resistance of the driven device J3, degrading VOL of this next stage.
FIGURE 16.4 Schematic of differential pair J1,J2 used as a source-coupled FET logic (SCFL) cell.
16-4 VLSI Technology
(b)
(a)
(c)
FIGURE 16.6 (a) Schematic of source follower, (b) load-line analysis of source follower, and (c) source follower
buffer between SCFL stages.
Logic Design Principles and Examples 16-5
full range from VOL to VDD. If VGS1 remains nearly constant, then Vout follows Vin , hence the name of the
circuit. Since the input voltage to the source follower stage is Vin = VGS1 + Vout, a small change in VGS1
would produce an incremental voltage gain close to unity. If the output resistance is low, then the
characteristic curves will slope upward and a larger range of VGS1 will be necessary to traverse the output
voltage range. This condition would produce a low voltage gain. Small signal analysis shows that
1
Av = (16.1)
⎡
⎢⎣ ( )
1 + 1 g m1 rds1 rds 2 ⎤
⎥⎦
The buffering effect of the source follower is accomplished by reducing the capacitive loading on the
drain nodes of the differential amplifier because the input impedance of a source follower is high. Since
the output tries to follow the input, the change in VGS will be less than that required by a common source
stage. Therefore, the input capacitance is dominated by CGD , typically quite small for compound semi-
conductor FETs biased in saturation. The effective small-signal input capacitance is
FIGURE 16.7 Voltage transfer characteristics of an inverter pair connected in a loop. Noise margins are shown as
VNH and VNL.
reset. This would constitute a logic failure. Therefore, we must insist that any viable logic circuit provide
noise margins well in excess of ambient noise levels in the circuit.
The static noise margin defined above utilized a dc voltage source VN in series with logic inverters to
represent static noise. This source might represent a static offset voltage caused by IR drop along IC
power and ground distribution networks. The DCFL inverter, for example, would experience a shift in
VTH that is directly proportional to a ground voltage offset. This shift would skew the noise margins. The
smallest noise margin would determine the circuit electrical yield. The layout of the power and ground
distribution networks must consider this problem. The width of power and ground buses on-chip must
be sufficient to guarantee a maximum IR drop that does not compromise circuit operation. It is important
to note that this width is frequently much greater than what might be required by electromigration limits.
It is essential that the designer consider IR drop in the layout. Some digital IC processes allow the topmost
metal layer to form a continuous sheet, thereby minimizing voltage drops.
The static noise voltage source VN might also represent static threshold voltage shifts on the active
devices due to statistical process variation or backgating effects. Therefore, the noise margin must be
several times greater than the variance in device threshold voltages provided by the fabrication process
so that electrical yields will not be compromised.5
The above definition of maximum width noise margin has assumed a steady-state condition. It does
not account for transient noise sources and the delayed response of the logic circuit to noise pulses.
Unfortunately, pulses of noise are quite common in digital systems. For example, the ground potential
can often be modified dynamically by simultaneous switching events on the IC chip.6 Any ground
distribution bus can be modeled as a transmission line with impedance Z0 where
Lo
Z0 = (16.3)
Co
Here, Lo is the equivalent series inductance per unit length and Co the equivalent shunt capacitance per
unit length. Since the interconnect exhibits a series inductance, there will be transient voltage noise ∆V
induced on the line by current transients as predicted by
dI
∆V = L (16.4)
dt
This form of noise is often called ground bounce. The ground bounce ∆V is particularly severe when
many devices are being switched synchronously, as would be the case in many applications involving
Logic Design Principles and Examples 16-7
flip-flops in shift registers or pipelined architectures. The high peak currents that result in such situations
can generate large voltage spikes. For example, output drivers are well-known sources of noise pulses on
power and ground buses unless they are carefully balanced with fully differential interconnections and
are powered by power and ground pins separate from the central logic core of the IC.
Designing to minimize ground bounce requires minimization of inductance. Bakoglu6 provides a good
discussion of power distribution noise in high-speed circuits. There are several steps often used to reduce
switching noise. First, it is standard practice to make extensive use of multiple ground pins on the chip
to reduce bond-wire inductance and package trace inductance when conventional packaging is used.
Bypass capacitance off-chip can be useful if it can be located inside the package and can have a high
series resonant frequency. On-chip bypass capacitance is also helpful, especially if enough charge can be
supplied from the capacitance to provide the current during clock transitions. The objective is to provide
a low impedance between power and ground on-chip at the clock frequency and at odd multiples of the
clock frequency. Finally, as mentioned above, high-current circuits such as clock drivers and output
drivers should not share power and ground pins with other logic on-chip.
Crosstalk is another common source of noise pulses caused by electromagnetic coupling between
adjacent interconnect lines. A signal propagating on a driven interconnect line can induce a crosstalk
voltage and current in a coupled line. The duration of the pulse depends on the length of interconnect;
the amplitude depends on the mutual inductance and capacitance between the coupled lines.7
In order to determine how much noise is acceptable in a logic circuit, the noise margin definition can
be modified to accommodate the transient noise pulse situation. The logic circuit does not respond
instantaneously to the noise pulse at the input. This delay in the response is attributed to the device and
interconnect capacitances and the device current limitations which will be discussed extensively in
Section 16.3. Consider the device input capacitance. Sufficient charge must be transferred during the
noise pulse to the input capacitance to shift the control voltage either above or below threshold. In
addition, this voltage must be maintained long enough for the output to respond if a logic upset is to
occur. Therefore, a logic circuit can withstand a larger noise pulse amplitude than would be predicted
from the static noise margin if the pulse width is much less than the propagation delay of the circuit.
This increased noise margin for short pulses is called the dynamic noise margin (DNM). The DNM
approaches the static NM if the pulse width is wide compared with the propagation delay because the
circuit can charge up to the full voltage if not constrained by time.
The DNM can be predicted by simulation. Figure 16.8(a) shows the loop connection of the set-reset
NOR latch similar to that which was used for the static NM definition in Fig.10.7. The inverter has been
modified to become a NOR gate in this case. An input pulse train V1(t) of fixed duration but with
FIGURE 16.8 (a) Set-reset latch used to describe dynamic noise margin simulation, and (b) plot of the pulse
amplitude applied to the set input in (a) that results in a logic upset.
16-8 VLSI Technology
gradually increasing amplitude can be applied to the set input. The latch was initialized by applying an
initial condition to the reset input V2(t). The output response is observed for the input pulse train. At
some input amplitude level, the output will be set into the opposite state. The latch will hold this state
until it is reset again. The cross-coupled NOR latch thus becomes a logic upset detector, dynamically
determining the maximum noise margin for a particular pulse width. The simulation can be repeated
for other pulse widths, and a plot of the pulse amplitude that causes the latch to set for each pulse
duration can be constructed, as shown in Fig. 16.8(b). Here, any amplitude or duration that falls on or
above the curve will lead to a logic upset condition.
Power Dissipation
Power dissipation of a static logic circuit consists of a static and a dynamic component as shown below.
PD = VDD I DD + C L ∆V 2 fη (16.5)
In the case of DCFL, the current IDD from the pull-up transistor J2 is relatively constant, flowing either
in the pull-down (switch) device J1 or in the gate(s) of the subsequent stage(s). Taking its average value,
the static power is VDD I DD . The dynamic power CL∆V2fη depends on the frequency of operation f, the
load capacitance CL, and the duty factor η. η is application dependent. Since the voltage swing is rather
small for the DCFL inverter under consideration (about 0.6 V for MESFETs), the dynamic power will
not be significant unless the load capacitance is very large, such as in the case of clock distribution
networks. The VDD power supply voltage is traditionally 2 V because of compatibility with the bipolar
ECL VTT supply, but a VDD as low as 1 V can be used for special low-power applications. Typical power
dissipation per logic cell (inverter, NOR) depends on the choice of supply voltage and on IDD. Power is
typically determined based on speed and is usually in the range of 0.1 to 0.5 mW/gate. DCFL logic circuits
are often used when the application requires high circuit density and very low power.
dV
I = CL (16.6)
dt
Logic Design Principles and Examples 16-9
is relevant when circuit performance is dominated by wiring or fan-out capacitance. This will be the case
if the delay predicted by Eq. 16.6 due to the total loading capacitance, CL, significantly exceeds the intrinsic
delay of a basic inverter or logic gate. To apply this approach, determine the average current available
from the driving logic circuit for charging (ILH) and discharging (IHL) the load capacitance. The logic
swing ∆V is known, so low-to-high (tPLH) and high-to-low (tPHL) propagation delays can be determined
from Eq. 16.6. These delays represent the time required to charge or discharge the circuit output to 50%
of its final value. Thus, tPLH is given by
C L ∆V
t PLH = (16.7)
2I LH
where ILH is the average charging current during the output transition from VOL to VOL + ∆V/2. The net
propagation delay is given by
t PLH + t PHL
tP = (16.8)
2
At this limit, where speed is dominated by the ability to drive load capacitance, we see that increasing
the currents will reduce tP . In fact, the product of power (proportional to current) and delay (inversely
proportional to current) is nearly constant under this situation. Increases in power lead to reduction of
delay until the interconnect distributed RC delays or electromagnetic propagation delays become com-
parable to tP .
The equation also shows that small voltage swing ∆V is good for speed if the noise margin and drive
current are not compromised. This means that the devices must provide high transconductance.
For example, the DCFL inverter of Fig. 16.2 can be analyzed. Figure 16.9 shows equivalent circuits that
represent the low-to-high and high-to-low transitions. The current available for the low-to-high transi-
FIGURE 16.9 (a) Equivalent circuit for low-to-high transition; and (b) Equivalent circuit for high-to-low transition.
16-10 VLSI Technology
tion, IPLH , shown in Fig. 16.9(a), is equal to the average pullup current, IDD . If we assume that VOL = 0.1 V
and VOH = 0.7 V, then the ∆V of interest is 0.6 V. This brings the output up to 0.4 V at V50% . In this range
of Vout, the active load transistor J2 is in saturation at all times for VDD > 1 V, so IDD will be relatively
constant, and all of the current will be available to charge the capacitor.
The high-to-low transition is more difficult to model in this case. Vout will begin at 0.7 V and discharge
to 0.4 V. The discharge current through the drain of J1 is going to vary with time because the device is
below saturation over this range of Vout. Looking at the Vin = 0.7 V characteristic curve in Fig. 16.3, we
see that its ID–VDS characteristic is resistive. Let’s approximate the slope by 1/Ron. Also, the discharge
current IPHL is the difference between IDD and ID1 = Vout /Ron , as shown in Fig. 16.9(b). The average current
available to discharge the capacitor can be estimated by
VOH + V50%
I HL = − I DD (16.9)
2Ron
C L ∆V
t PHL = (16.10)
2I HL
FIGURE 16.10 (a) Monotonic step response of a network; (b) corresponding impulse response. The delay tD is
defined as the centroid of the impulse response.
∞ ∞
∫ tf (t )dt ∫ tf (t )e − st ⎡ d
dt ⎤
⎢− F s ⎥ ()
tD = 0
= lim 0
= ⎢ ds ⎥
()
∞
(16.11)
s →0 ∞ ⎢ F s ⎥
∫ f (t )dt
0
∫ ()
0
f t e − st dt ⎣ ⎦ s =0
Fortunately, the integration never needs to be performed. tD can be obtained directly from the network
function F(s) as shown. But, the network function must be calculated from the large-signal equivalent
circuit of the device, including all important parasitics, driving impedances, and load impedances. This
is notoriously difficult if the circuit includes a large number of capacitances or inductances.
Fortunately, in most cases, circuits of interest can be subdivided into smaller networks, cascaded, and
the presumed linearity of the circuits can be employed to simplify the task. In addition, the evaluation
of the function at s = 0 eliminates many terms in the equations that result. In particular, Tien10 shows
that two corollaries are particularly useful in cascading circuit blocks:
1. If the network function F(s) = A(s)/B(s), then
⎡ d ⎤ ⎡d ⎤
⎢− A s ⎥
t D = ⎢ ds
() ⎢ Bs
⎥ + ⎢ ds
( ) ⎥⎥
() ( ) ⎥⎦
(16.12)
⎢ As ⎥ ⎢ Bs
⎣ ⎦ s =0 ⎣ s =0
⎡ d ⎤ ⎡ d ⎤ ⎡ d ⎤
⎢− A s ⎥
t D = ⎢ ds
() ⎢− B s ⎥
⎥ + ⎢ ds
()
⎢− C s ⎥
⎥ + ⎢ ds ⎥
()
() () ()
(16.13)
⎢ As ⎥ ⎢ Bs ⎥ ⎢ Cs ⎥
⎣ ⎦ s =0 ⎣ ⎦ s =0 ⎣ ⎦ s =0
This shows that the total delay is just the sum of the individual delays of each circuit block. When
computing the network functions, care must be taken to include the driving point impedance of the
16-12 VLSI Technology
previous stage and to represent the previous stage as a Thevenin-equivalent open-circuit voltage source.
A good description and illustration of the use of this approach in the analysis of bipolar ECL and CML
circuits can be found in Ref. 10.
Risetime: the standard definition of risetime is the 10 to 90% time delay of the step response of a
network. While convenient for measurement, this definition is analytically unpleasant to derive for any-
thing except simple, first-order circuits. Elmore demonstrated that the standard deviation of the impulse
response could be used to estimate the risetime of a network.8 This definition provides estimates that are
close to the standard definition. The standard deviation of the impulse response can be calculated using
⎡∞ ⎤
R
⎢ ∫ ()
T = 2π ⎢ t 2 f t dt − t D2 ⎥
2
⎥
(16.14)
⎣0 ⎦
Since the impulse response frequently resembles the Gaussian function, the integral is easily evaluated.
Once again, the integration need not be performed. Lee11 has pointed out that the transform techniques
can also be used to obtain the Elmore risetime directly from the network function F(s).
2
⎡ d2 ⎤ ⎡d ⎤
⎢ 2F s ⎥() ⎢ F s () ⎥
TR2 = 2π ⎢ ds ⎥ − 2π ⎢ ds ⎥
() ()
(16.15)
⎢ F s ⎥ ⎢ F s ⎥
⎣ ⎦ s =0 ⎣ ⎦ s =0
This result can also be used to show that the risetimes of cascaded networks add as the square of the
individual risetimes. If two networks are characterized by risetimes TR1 and TR2 , the total risetime TR,total
is given by the RMS sum of the individual risetimes
()
F s =
bns + bn−1s
n
a
n −1
0
+ L + b1s + 1
(16.17)
The denominator comes from the product of n factors of the form (τjs + 1), where τj is the time constant
associated with the j-th pole in the transfer function. The b1 coefficient can be shown to be equal to the
sum
Logic Design Principles and Examples 16-13
b1 = ∑τ j =1
j (16.18)
of the time constants and b2 the product of all the time constants. Often, the first-order term dominates
the frequency response. In this case, the 3-dB bandwidth is then estimated by ω3dB = 1/b1. The higher-
order terms are neglected. The accuracy of this approach is good, especially when the circuit has a
dominant pole. The worst error would occur when all poles have the same frequency. The error in this
case is about 25%. Much worse errors can occur however if the poles are complex or if there are zeros
in the transfer function as well. We will discuss this later.
Elmore has once again provided the connection we need to obtain delay and risetime estimates from
the transfer function. The Elmore delay is given by
D = b1 − a1 (16.19)
where a1 is the corresponding coefficient of the first-order zero (if any) in the numerator. The risetime
is given by
In Eq. 16.20, a2 and b2 correspond to the coefficients of the second-order zero and pole, respectively.
At this point, it would appear that we have gained nothing since finding that the time constants
associated with the poles and zeros is well known to be difficult. Fortunately, it is possible to obtain the
b1 and b2 coefficients directly by a much simpler method: open-circuit time constants. It has been shown
that11,12
n n
b1 = ∑R C = ∑τ
j =1
jo j
j =1
jo (16.21)
that is, the sum of the time constants τjo , defined as the product of the effective open-circuit resistance
Rjo across each capacitor Cj when all other capacitors are open-circuited, equals b1 . These time constants
are very easy to calculate since open-circuiting all other capacitors greatly simplifies the network by
decoupling many other components. Dependent sources must be considered in the calculation of the Rjo
open-circuit resistances. Note that these open-circuit time constants are not equal to the pole time
constants, but their sum gives the same result for b1. It should also be noted that the individual OCTCs
give the time constant of the network if the j-th capacitor were the only capacitor. Thus, each time
constant provides information about the relative contribution of that part of the circuit to the bandwidth
or the delay.11 If one of these is much larger than the rest, this is the place to begin working on the circuit
to improve its speed.
The b2 coefficient can also be found by a similar process,14 taking the sum of the product of time
constants of all possible pairs of capacitors. For example, in a three-capacitor circuit, b2 is given by
where the Rjsi resistance is the resistance across capacitor Cj calculated when capacitor Ci is short-circuited
and all other capacitors are open-circuited. The superscript indicates which capacitor is to be shorted.
So, R3s2 is the resistance across C3 when C2 is short-circuited and C1 is open-circuited. Note that the first
time constant in each product is an open-circuit time constant that has already been calculated. In
16-14 VLSI Technology
addition, for any pair of capacitors in the network, we can find an OCTC for one and a SCTC for the
other. The order of choice does not matter because
FIGURE 16.12 (a) Large-signal half-circuit model of ECL inverter; and (b) large-signal equivalent circuit of (a).
Logic Design Principles and Examples 16-15
the half-circuit approximation has been used in Fig. 16.12(a) due to the inherent symmetry of differential
circuits.16 The hybrid-pi BJT model shown in Fig. 16.12(b) has been used with several simplifications.
The dynamic input resistance, rπ , has been neglected because other circuit resistances are typically much
smaller. The output resistance, ro , has also been neglected for the same reason. The collector-to-substrate
capacitance, CCS , has been neglected because in III-V technologies, semi-insulating substrates are typically
used. The capacitance to substrate is quite small compared to other device capacitances. Retained in the
model are resistances Rbb , the extrinsic and intrinsic base resistance, and REX , the parasitic emitter
resistance. Both of these are very critical for optimizing high-speed performance.
In the circuit itself, RIN is the sum of the driving point resistance
from the previous stage, probably an emitter follower output, and Rbb1
of Q1. RL is the collector load resistor, whose value is determined by
half of the output voltage swing and the dc emitter current, ICS. RL =
∆V/2ICS. The REX of the emitter follower is included in REF .
We must calculate open-circuit time constants for each of the four
capacitors in the circuit. First consider C1 , the base-emitter diffusion
and depletion capacitance of Q1 . C2 is the collector-base depletion
capacitance of Q1. C3 and C4 are the corresponding base-emitter and
base-collector capacitances of Q2 . Figure 16.13 represents the equiva- FIGURE 16.13 Equivalent large-
lent circuit schematic when C2 = C3 = C4 = 0. A test source, V1, is signal half-circuit model for calcu-
placed at the C1 location. R1o = V1 /I1 is determined by circuit analysis lation of R1o .
to be
RIN + REX
R1o = (16.24)
1 + G M 1REX
Table 16.1 shows the result of similar calculations for R2o , R3o , and R4o . The b1 coefficient (first-order
estimate of tD) can now be found from the sum of the OCTCs:
Considering the results in Table 16.1, one can see that there are many contributors to the time constants and
that it will be possible to determine the dominant terms after evaluating the model and circuit parameters.
Next, estimates must be made of the non-linear device parameters, GMi and Ci . The large signal
transconductances can be estimated from
∆I C
GM = (16.26)
∆VBE
()
∆VBE = VT ln 2 = 0.7VT = 17.5mV (16.27)
−m
⎛ V⎞
( ) ()
C V = C 0 ⎜1 − ⎟
⎝ φ⎠
(16.28)
where C(0) is the capacitance at zero bias, φ is the built-in voltage, and m the grading coefficient. An
equivalent large-signal capacitance can be calculated by
Q2 − Q1
C= (16.29)
V2 − V1
Qi is the charge at the initial (1) or final (2) state corresponding to the voltages Vi . Q2 – Q1 = ∆Q and
V2
∫()
∆Q = C V dV
V1
(16.30)
CD = G M τ f (16.31)
b2 = R1oC1R21 sC2 + R1oC1R13sC3 + R1oC1R14 sC4 + R2oC2 R32sC3 + R2oC2 R42sC4 + R3oC3R43sC4 (16.32)
R2s1 will be calculated to illustrate the procedure. The remaining short-circuit equivalent resistances are
shown in Table 16.2. Referring to Fig. 16.14, the equivalent circuit for calculation of R2s1 is shown. This
is the resistance seen across C2 when C1 is shorted. If C1 is shorted, V1 = 0 and the dependent current
source is dead. It can be seen from inspection that
⎛ 1 ⎞
⎜ G ′ RIN RL ⎟ + Rbb + REF
R 2 ⎝ M1 ⎠
3s
1 + G M 2REF
⎛ 1 ⎞
R24s ⎜ G ′ RIN RL ⎟ + Rbb
⎝ M1 ⎠
R34s (R L )
+ Rbb REF
References
1. Yuan, J.-R. and Svensson, C., High-Speed CMOS Circuit Technique, IEEE J. Solid-State Circuits,
24, 62, 1989.
2. Weste, N. H. E. and Eshraghian, K., Principles of CMOS VLSI Design – A Systems Perspective,
second ed., Addison-Wesley, Reading, MA, 1993.
3. Rabaey, J. M., Digital Integrated Circuits: A Design Perspective, Prentice-Hall, New York, 1996.
4. Hill, C. F., Noise Margin and Noise Immunity in Logic Circuits, Microelectronics, 1, 16, 1968.
5. Long, S. and Butner, S., Gallium Arsenide Digital Integrated Circuit Design, McGraw-Hill, New
York, 1990, Chap. 3.
6. Bakoglu, H. B., Circuits, Interconnections, and Packaging, Addison-Wesley, Reading, MA, 1990,
Chap. 7.
7. Long, S. and Butner, S., Gallium Arsenide Digital Integrated Circuit Design, McGraw-Hill, New
York, 1990, Chap. 5.
16-18 VLSI Technology
8. Elmore, W. C., The Transient Response of Damped Linear Networks with Particular Regard to
Wideband Amplifiers, J. Appl Phys., 19, 55, 1948.
9. Ashar, K. G., The Method of Estimating Delay in Switching Circuits and the Fig. of Merit of a
Switching Transistor, IEEE Trans. Elect. Dev., ED-11, 497, 1964.
10. Tien, P. K., Propagation Delay in High Speed Silicon Bipolar and GaAs HBT Digital Circuits, Int.
J. High Speed Elect., 1, 101, 1990.
11. Lee, T. H., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge Univ. Press,
Cambridge, U.K., 1998, Chap. 7.
12. Gray, P. E. and Searle, C. L., Electronic Principles: Physics, Models, and Circuits, John Wiley & Sons,
New York, 1969, 531.
13. Gray, P. and Meyer, R., Analysis and Design of Analog Integrated Circuits, 3rd ed., John Wiley &
Sons, New York, 1993, Chap. 7.
14. Millman, J. and Grabel, A., Microelectronics, second ed., McGraw-Hill, New York, 1987, 482.
15. Hurtz, G. M., Applications and Technology of the Transferred-Substrate Schottky-Collector Het-
erojunction Bipolar Transistor, M.S. Thesis, University of California, Santa Barbara, 1995.
16. Gray, P. and Meyer, R., Analysis and Design of Analog Integrated Circuits, 3rd ed., John Wiley &
Sons, New York, 1993, Chap. 3.
17
Logic Design Examples
Charles E. Chang 17.1 Design of MESFET and HEMT Logic Circuits ..............17-1
Conexant Systems, Inc. Direct-Coupled FET Logic (DCFL) • Source-Coupled FET
Logic (SCFL) • Advanced MESFET/HEMT Design Examples
Meera Venkataraman
Troika Networks, Inc. 17.2 HBT Logic Design Examples..........................................17-10
III-V HBT for Circuit Designers • Current-Mode Logic •
Stephen I. Long Emitter-Coupled Logic • ECL/CML Logic Examples •
University of California Advanced ECL/CML Logic Examples • HBT Circuit Design
at Santa Barbara Examples
0-8493-1738-X/03/$0.00+$1.50
© 2003 by CRC Press LLC 17-1
17-2 VLSI Technology
drain capacitance will increase in proportion to the number of inputs, slowing down the risetime of the
gate output. Also, the subthreshold current contribution from n parallel devices could become large
enough to degrade VOH, and therefore the noise margin. This must be evaluated at the highest operating
temperature anticipated because the subthreshold current will increase exponentially with temperature
according to:3,4
⎡ ⎛ cV ⎞ ⎤ ⎡ ⎛ bV ⎞ ⎤ ⎡ ⎛ aV ⎞ ⎤
I D = I S ⎢1 − exp⎜ DS ⎟ ⎥ ⎢exp⎜ DS ⎟ ⎥ ⎢exp⎜ GS ⎟ ⎥ (17.1)
⎢⎣ ⎝ VT ⎠ ⎥⎦ ⎢⎣ ⎝ VT ⎠ ⎥⎦ ⎢⎣ ⎝ VT ⎠ ⎥⎦
The parameters a, b, and c are empirical fitting parameters. The first term arises from the diffusion
component of the drain current which can be fit from the subthreshold ID–VDS characteristic at low drain
voltage. The second and third terms represent thermionic emission of electrons over the channel barrier
from source to drain. The parameters can be obtained by fitting the subthreshold ID–VDS and ID–VGS
characteristics, respectively, measured in saturation.5 For the reasons described above, the fan-in of the
DCFL NOR is seldom greater than 4.
In addition to the subthreshold current loading, the forward voltage of the Schottky gate diode of the
next stage drops with temperature at the rate of approximately –2mV/degree. Higher temperature oper-
ation will therefore reduce VOH as well, due to this thermodynamic effect.
A NAND function can also be generated by placing enhancement-mode MESFETs in series rather
than in parallel for the switch function. However, the low voltage swing inherent in DCFL greatly limits
the application of the NAND function because VOL will be increased by the second series transistor unless
the widths of the series devices are increased substantially from the inverter prototype. Also, the switching
threshold VTH shown in Fig. 16.1 will be slightly different for each input even if width ratios are made
different for the two inputs. The combination of these effects reduces the noise margin even further,
making the DCFL NAND implementation generally unsuitable for VLSI applications.
Buffering DCFL Outputs
The output (drain) node of a DCFL gate sources and sinks the current required to charge and discharge
the load capacitance due to wiring and fan-out. Excess propagation delay of the order of 5 ps per fan-
out is typically observed for small DCFL gates. Sensitivity to wiring capacitance is even higher, such that
unbuffered DCFL gates are never used to drive long interconnections unless speed is unimportant.
Therefore, an output buffer is frequently used in such cases or when fan-out loading is unusually high.
The superbuffer shown in Fig. 17.2(a) is often used to improve the drive capability of DCFL. It consists
of a source follower J3 and pull-down J4. The low-to-high transition begins when VIN = VOL. J4 is cut off
Logic Design Examples 17-3
FIGURE 17.2 (a). Superbuffer schematic, and (b) modified superbuffer with clamp transistor. J5 will limit the
output current when Vout > 0.7 V.
and J3 becomes active, driving the output to VOH. VOUT follows the DCFL inverter output. For the output
high-to-low transition, J4 is driven into its linear region, and the output can be pulled to VOL = 0 V in
steady state. J3 is cut off when the DCFL output (drain of J1) switches from high to low. Since this occurs
one propagation delay after the input switched from low-to-high, it is during this transition that the
superbuffer can produce a current spike between VDD and ground. J4 attempts to discharge the load
capacitance before the DCFL gate output has cut off J3 . Thus, superbuffers can become an on-chip noise
source, so ground bus resistance and inductance must be controlled.
There is also a risk that the next stage might be overdriven with too much input current when driven
by a superbuffer. This could happen because the source follower output is capable of delivering high
currents when its VGS is maximum. This occurs when Vout = VOH = 0.7 V, limited by forward conduction
of the gate diodes being driven. For a supply voltage of 2 V, a maximum VGS = 0.7 V is easily obtained
on J3 , leading to the possibility of excess static current flowing into the gates. This would degrade VOL of
the subsequent stage due to voltage drop across the internal source resistance. Figure 17.2(b) shows a
modified superbuffer design that prevents this problem through the addition of a clamp transistor, J5 . J5
limits the gate potential of J3 when the output reaches VOH , thus preventing the overdriving problem.
FIGURE 17.3 Schematic diagram of SCFL inverter with source follower output buffering.
FIGURE 17.5 SCFL D latch schematic. Two cascaded latch cells with opposite clock phasing constitute a master-
slave flip-flop.
The logic swing of the circuit shown in Fig. 17.4 is determined by the size of the current source T3
and the load resistors R1 and R2 (R1 = R2). Assuming T3 is in saturation, the logic swing on nodes X
and Y is
where Idss3 is the saturation current of T3 at Vgs = 0 V. The logic high and low levels on node X (VX,H,
VX,L ) are determined from the voltage drop across R3 and Eq. 17.2.
The noise margin is the difference between the minimum voltage swing required on the inputs to
switch the current from one branch to the other (VSW) and the logic swing ∆VX,Y . VSW is set by the ratio
between the sizes of the switch transistors (T1,T2, T4-T7) and T3. For symmetry reasons, the sizes of all
the switch transistors are kept the same size. Assuming the saturation drain-source current of an FET
can be described by the simplified square-law equation:
where VT is the threshold voltage, W is the FET width, and β is a process-dependent parameter. VSW is
calculated assuming all the current from T3 flows only through T2.
VSW = VT (W 3 W 2) (17.6)
For a fixed current source size (W3), the larger the size of the switch transistors, the smaller the voltage
swing required to switch the current and, hence, a larger noise margin. Although a better noise margin
is desirable, it needs to be noted that the larger switch transistors means increased input capacitance and
decreased speed. Depending on the design specifications, noise margin and speed need to be traded off.
Since all FETs need to be kept in the saturation region for the correct operation of an SCFL gate, level-
shifting is needed between nodes A and B and the input to the next gate, in order to keep T1, T2, and
T4-T7 saturated. T3 is kept in saturation if the potential at node S is higher than VSS + Vds,sat . The potential
at node S is determined by the input voltages to T1 and T2. VS settles at a potential such that the drain-
source current of the conducting transistor is exactly equal to the bias current, Idss3 , since no current
flows through the other transistor. The minimum logic high level at the output node B (VOB,H) is
17-6 VLSI Technology
As with the voltage on node S, the drain voltages of T1 and T2 are determined by the voltage applied to
the A inputs. The saturation condition for T1 and T2 is
Equation 17.9 shows that the lower switch transistors are kept in saturation if the level-shifting difference
between the A and B outputs is larger than the FET saturation voltage. Since diodes are used for level-
shifting, the minimum difference between the two outputs is one diode voltage drop, VD. If Vds,sat > VD,
more diodes are required between the A and B outputs.
The saturation condition for the upper switch transistors, T4 to T7, is determined by the minimum
voltage at nodes A and B and the drain voltage of T1 and T2.
(Vdd ( )) ( )
− Idss 3 ∗ R1 + R3 − VOA ,H − VSW − Vth ≥ Vds,sat (17.11)
Rewriting Eq. 17.11 using Eq. 17.8 gives the minimum power supply range
Equation 17.11 allows the determination of the minimum amount of level-shifting required between
nodes A and B to the outputs
Equations 17.8 to 17.13 can be used for designing the level shifters. The design parameters available in
the level-shifters are the widths of the source followers (W8, W10), the current sources (W9, W11), and
the diode (WD). Assuming the current source width (W9) is fixed, the voltage drop across the diodes is
partially determined by the ratio (WD /W9). This ratio should not be made too small. Operating Schottky
diodes at high current density will result in higher voltage drop, but this voltage will be partially due to
the IDRS drop across the parasitic series resistance. Since this resistance is often process dependent and
difficult to reproduce, poor reproducibility of VD will result in this case.
The ratio between the widths of the source follower and the current source (W8/W9) determines the
gate-source voltage of the source follower (Vgs8). Vgs8 should be kept below 0.5 V to prevent gate-source
conduction.
The dc design of the two-level series-gated SCFL gate in Fig. 17.4 can be accomplished by applying
Eqs. 17.2 to 17.13. Ratios between most device sizes can be determined by choosing the required noise
margin and logic swing. Only W3 in the differential stage and W9 among the level-shifters are unknown
at this stage. All other device sizes can be expressed in terms of these two transistor widths.
The relation between W3 and W9 can be determined only by considering transient behavior. For a
given total power dissipation, the ratio between the power dissipated in the differential stage and the
output buffers determines how fast the outputs are switched. If fast switching at the outputs is desired,
more power needs to be allocated to the output buffers and, consequently, less power to the differential
Logic Design Examples 17-7
stage. While this allocation will ensure faster switching at the output, the switching speed of the differential
stage is reduced because of the reduced current available to charge and discharge the large input capac-
itance of the output buffers.
Finally, it is useful to note that scaling devices to make a speed/power tradeoff is simple in SCFL. If
twice as much power is allocated to a gate, all transistors and diodes are made twice as wide while all
resistors are reduced by half.6
using logic gates because their delays are well characterized in a given process. Output jitter can be
minimized if 50% duty-cycle clock signals are used. Otherwise, a retiming MSFF will be needed at the
output of the 4:1 MUX.
The 4:1 MUX is a good example of an application of GaAs MESFETs with very-high-speed operation
and low levels of integration. Vitesse Semiconductor has several standard products operating at the Gb/s
range fabricated in GaAs using their own proprietary E/D MESFET process. For example, the 16 × 16
crosspoint switch, VSC880, has serial data rates of 2.0 Gb/s. The VS8004 4-bit MUX is a high-speed,
parallel-to-serial data converter. The parallel inputs accept data at rates up to 625 Mb/s and the differential
serial data output presents the data sequentially at 2.5 Gb/s, synchronous with the differential high-speed
clock input.2
While the MESFET technologies have proven capable at 2.5 and 10 Gb/s data rates for optical fiber
communication applications, higher speeds appear to require heterojunction technologies. The 40-Gb/s
TDM application is the next step, but it is challenging for all present semiconductor device IC technologies.
A complete 40-Gb/s system has been implemented in the laboratory with 0.1-µm InAlAs/InGaAs/InP
HEMT ICs as reported in Refs. 7 and 8. Chips were fabricated that implemented multiplexers, photodiode
preamplifiers, wideband dc 47-GHz amplifiers, decision circuits, demultiplexers, frequency dividers, and
limiting amplifiers. The high-speed static dividers used the super-dynamic FF approach.9
A 0.2-µm AlGaAs/GaAs/AlGaAs HEMT quantum well device technology has also demonstrated
40-Gb/s TDM system components. A single chip has been reported that included clock recovery, data
decision, and a 2:4 demultiplexer circuit.10 The SCFL circuit approach was employed.
Very-High-Speed Dynamic Circuits
Conventional logic circuits using static DCFL or SCFL NOR gates such as those described above are
limited in their maximum speed by loaded gate delays and serial propagation delays. For example, a
typical DCFL NOR-implemented edge-triggered DFF has a maximum clock frequency of approximately
1/5τD and the SCFL MSFF is faster, but it is still limited to 1/2τD at best. Frequency divider applications
that require clock frequencies above 40 GHz have occasionally employed alternative circuit approaches
which are not limited in the same sense by gate delays and often use dynamic charge storage on gate
Logic Design Examples 17-9
FIGURE 17.8 Dynamic frequency divider (DFD) divide-by-2 circuit. (Ref. 11, ©1989 IEEE, with permission.)
nodes for temporarily holding a logic state. These approaches have been limited to relatively simple circuit
functions such as divide-by-2 or -4.
The dynamic frequency divider (DFD) technique is one of the well-known methods for increasing
clock frequency closer to the limits of a device technology. For an example, Fig. 17.8 shows a DFD circuit
using a single-phase clock, a cross-coupled inverter pair as a latch to reduce the minimum clock frequency,
and pass transistors to gate a short chain of inverters.11,12 These have generally used DCFL or DCFL
superbuffers for the inverters. The cross-coupled inverter pair can be made small in width, since its serial
delay is not in the datapath. But the series inverter chain must be designed to be very fast, generally
requiring high power per inverter in order to push the power-delay product to its extreme high-speed
end. Since fan-out is low, the intrinsic delays of an inverter in a given technology can be approached.
The maximum and minimum clock frequencies of this circuit can be calculated from the gate delays
of the n series inverters as shown in Eqs. 17.14 and 17.15. An odd number n is required to force an
inversion of the data so that the circuit will divide-by-2. Here, t1 is the propagation delay of the pass
transistor switches, J1 and J2, and tD is the propagation delay of the DCFL inverters. The parameter “a”
is the duty cycle of the clock. For a 50% clock duty cycle, the range of minimum to maximum clock
frequency is about 2 to 1.
1
fφmax = (17.14)
t1 + nt D
a
fφmin = (17.15)
t1 + nt D
Clock frequencies as high as 51 GHz have been reported using this approach with a GaAs/AlGaAs
P-HEMT technology.12 The power dissipation was relatively high, 440 mW. Other DFD circuit approaches
can also be found in the literature.13-15
A completely different approach, as shown in Fig. 17.9, utilizes an injection-locked push-pull oscillator
(J1 and J2) whose free running frequency is a subharmonic of the desired input frequency.16 FETs J3 and
J4 are operating in their ohmic regions and act as variable resistors. The variation in VGS1 and VGS2 cause
the oscillator to subharmonically injection-lock to the input source. Here, a divide-by-4 ratio was
demonstrated with an input frequency of 75 GHz and a power dissipation of 170 mW using a 0.1-µm
InP-based HEMT technology with fT = 140 GHz and fmax = 240 GHz. This divider also operated in the
59–64 GHz range with only –10 dBm RF input power. The frequency range is limited by the tuning range
of the oscillator. In this example, about 2 octaves of frequency variation was demonstrated.
17-10 VLSI Technology
FIGURE 17.9 Injection-locked oscillator divide-by-4. (Ref. 16, ©1996 IEEE. With permission.)
Finally, efforts have also been made to beat the speed limitations of a technology by dynamic design
methods while still maintaining minimum power dissipation. The quasi-dynamic FF8,9 and quasi-differ-
ential FF17 are examples of circuit designs emphasizing this objective. The latter has achieved 16-GHz
clock frequency with approximately 2 mW of power per FF.
technology and Si BJT technology, as discussed below, can be traced to three essential aspects:
(1) heterojunction vs. homojunction, (2) III-V material properties, and (3) substrate properties.
First, the primary advantage of a base–emitter heterojunction is that the wide bandgap emitter allows
the base to be doped higher than the emitter (typically 10 to 50X in GaAs/AlGaAs HBTs) without a
reduction in current gain. This translates to lower base resistance for improved fmax and reduces base
width modulation with Vce for low output conductance. Alternatively, the base can be made thinner for
lower base-transit time (τb) and higher ft without having Rb too high. If the base composition is also
graded from high bandgap to low, an electric field can be established to sweep electrons across the base
for reduced τb and higher ft. With a heterojunction B-E and a homojunction B-C, the junction turn-on
voltage is higher in the B-E than it is in the B-C. This results in a common-emitter I–V curve offset from
the off to saturation transition. This offset is approximately 200 mV in GaAs/AlGaAs HBTs. With a highly
doped base, base punch-through is not typically observed in HBTs and does not limit the ft-breakdown
voltage product as in high-performance Si BJTs and SiGe HBT with thin bases. Furthermore, if a
heterojunction is placed in the base–collector junction, a larger bandgap material in the collector can
increase the breakdown voltage of the device and reduce the I–V offset.
Second, III-V semiconductors typically offer higher electron mobility than Si for overall lower τb and
collector space charge layer transit times (τcscl). Furthermore, many III-V materials exhibit velocity
overshoot in the carrier drift velocity. When HBTs are designed to exploit this effect, significant reductions
in τcscl can result. With short collectors, the higher electron mobility can result in ultra-high ft ; however,
this can also be used to form longer collectors with still acceptable τcscl , but significantly reduced Cbc for
high fmax. The higher mobility in the collector can also lead to HBTs with lower turn on resistance in the
common emitter I–V curves.
Since GaAs/AlGaAs and GaAs/InGaP have wider bandgaps than Si, the turn-on voltage of the B–E
(Vbe,on) junction is typically on the order of 1.4 V vs. 0.9 V for advanced high-speed Si BJT. InP-based
HBTs can have Vbe,on on the order of 0.7 V; however, most mature production technologies capable of
LSI integration levels are based on AlGaAs/GaAs or InGaP/GaAs. The base–collector turn-on voltage is
typically on the order of 1 V in GaAs-based HBTs. This allows Vce to be about 600 mV lower than Vbe
without placing the device in saturation. The wide bandgap material typically results in higher breakdown
voltages, so III-V HBTs typically have a high Johnson figure of merit (ft * breakdown voltage) compared
with Si- and SiGe-based bipolar transistors.
The other key material differences between III-V vs. silicon materials are the lack of a native stable
oxide in III-V, the extensive use of poly-Si in silicon-based processes, and the heavy use of implants and
diffusion for doping silicon devices. III-V HBTs typically use epitaxial growth techniques, and intercon-
nect step height coverage issues limit the practical structure to one device type, so PNP transistors are
not typically included in an HBT process. These key factors contribute to the differences between HBTs
and BJTs in terms of fabrication.
Third, the GaAs substrate used in III-V HBTs is semi-insulating, which minimizes parasitic capacitance
to ground through the substrate, unlike the resistive silicon substrate. Therefore, the substrate contact
as in Si BJTs is unnecessary with III-V HBTs. In fact, the RF performance of small III-V HBT devices
can be measured directly on-wafer without significant de-embedding of the probe pads below 26 GHz.
For interconnects, the line capacitance is typically dominated by parallel wire-to-wire capacitance, and
the loss is not limited by the resistive substrate. This allows for the formation of high-Q inductors, low-
loss transmission lines, and longer interconnects that can be operated in the 10’s of GHz. Although BESOI
and SIMOX Si wafers are insulating, the SiO2 layer is typically thin resulting in reduced but still significant
capacitive coupling across this thin layer.19
Most III-V substrates have a lower thermal conductivity than bulk Si, resulting in observed self-heating
effects. For a GaAs/AlGaAs HBT, this results in observed negative output conductance in the common-
emitter I–V curve measured with constant Ib. The thermal time constant for GaAs/AlGaAs HBTs is on the
order of microseconds. Since thermal effects cannot track above this frequency, the output conductance
17-12 VLSI Technology
FIGURE 17.10 Standard differential CML buffer with a simple reference generator.
of HBTs at RF (> 10 MHz) is low but positive. This effect does result in a small complication for HBT
models based on the standard Gummel Poon BJT model.
Current-Mode Logic
The basic current-mode logic (CML) buffer/inverter cell is shown in Fig. 17.10. The CML buffer is a
differential amplifier that is operated with its outputs clipped or in saturation. The differential inputs
(Vin and Vin′) are applied to the bases of Q1 and Q2. The difference in potential between Vin and Vin′
determines which transistor Ibias is steered through, resulting in a voltage drop across either load resistance
RL1 or RL2. If Vin = VOH and Vin′ = VOL (Vin,High > Vin,Low), Q1 is on and Q2 is off. Consequently, Ibias completely
flows through RL1, causing Vout′ to drop for a logic low. With Q2 off, Vout floats to ground for a logic high.
If the terminal assignment of Vout and Vout′ were reversed, this CML stage would be an inverter instead
of a buffer.
The logic high VOH of a CML gate is 0 V. The logic low output is determined by VOL = –RL1Ibias . With
RL1/RL2 = 200 Ωs, and Ibias = 2 mA, the traditional logic low of a CML gate is –400 mV. As CML gates
are cascaded together, the outputs of one stage directly feed the inputs of another CML gate. As a result,
the base-collector of the “on” transistor is slightly forward-biased (by 400 mV in this example). For high-
speed operation, it is necessary to keep the switching transistors out of saturation. With a GaAs base-
collector turn-on voltage near 1V, 500 to 600 mV forward-bias is typically tolerated without any saturation
effects. In fact, this bias shortens the base-collector depletion region, resulting in the highest ft vs. Vce
(fmax suffers due to increase in Cbc). As a result, maximum logic swing of a CML gate is constrained by
the need to keep the transistors out of saturation. As the transistor is turned on, the logic high is actively
pulled to a logic low; however, as the transistor is turned off, the logic low is pulled up by a RC time
constant. With a large capacitive loading, it is possible that the risetime is slower than the falltime, and
that may result in some complications with high-speed data.
A current mirror (Qcs and Rcs) sets the bias (Ibias) of the differential pair. This is an essential parameter
in determining the performance of CML logic. In HBTs, the ft dependence on Ic is as follows:
Logic Design Examples 17-13
( ( )) ( )
1 2πft = τec = nkT qIc C bej + C bc + C bed + R c C bej + C bc + τ b + τcsc l (17.16)
where τec is the total emitter-to-collector transit time, qIc/nkT is the transconductance (gm), Cbc is the
base-collector capacitance, Cbej is the base–emitter junction capacitance, Cbed is the B–E diffusion capac-
itance, Rc is the collector resistance, τb is the base transit time, and τcscl is the collector space charge layer
transit time. At low currents, the transit time is dominated by the device gm and device capacitance. As
the bias increases, τec is eventually limited by τb and τcscl . As this limit approaches, Kirk effect typically
starts to increase τb/τcscl , which decreases ft . In some HBTs, the peak fmax occurs a bit after the peak ft.
With this in mind, optimal performance is typically achieved when Ibias is near Ic,maxft or Ic,maxfmax . In some
HBT technologies, the maximum bias may be constrained by thermal or reliability concerns. As a rule
of thumb, the maximum current density of HBTs is typically on the order of 5 × 104 A/cm2.
The bias of CML and ECL logic is typically set with a bias reference generator, where the simplest
generator is shown in Fig. 17.10. Much effort has been invested in the design of the reference generator
to maintain constant bias with power supply and temperature variation. In HBT, secondary effects of
heterojunction design typically result in slightly varying ideality factor with bias. This makes the design
of bandgap reference circuits quite difficult in most HBT technologies, which complicates the design of
the reference generator. Nevertheless, the reference generators used today typically result in a 2% variation
in bias current from –40 to 100 C with a 10% variation in power supply. In most applications, the voltage
drop across Rcs is set to around 400 mV. With Vee set at –5.2 V, Vref is typically near –3.4 V. With constant
bias, as Vee moves by ±10%, then the voltage drop across Rcs remains constant, so Vref moves by the change
in power supply (about ±0.5 V). Since the logic levels are referenced to ground, the average value of Vcm
(around –1.4 V) remains constant. This implies that changes in the power supply are absorbed by the
base–collector junction of Qcs , and it is important that this transistor is not deeply saturated.
Since the device goes from the cutoff mode to the forward active mode as it switches, the gate delay
is difficult to predict analytically with small-signal analysis. Thus, large-signal models are typically used
to numerically compute the delay in order to optimize the performance of a CML gate. Nevertheless, the
small-signal model, frequency-domain approach described in Chapter 16.3 (Elmore) leads to the follow-
ing approximation of a CML delay gate with unity fan-ou1:19a
( ) ( ) (
τd ,cml = 1 + g m R L R bC bc + R b C be + C d + 2C bc + 1 2 C be + 1 2 C d ) gm (17.17)
where Cd is the diffusion capacitance of gm(τb + τcscl). Furthermore, by considering the difference in
charge storage at logic high and logic low, divided by the logic swing, the effective CML gate capacitance
can be expressed19b as
(
C cml = C be 2 + 2C bc + C s + τ b + τcsc l ) RL (17.18)
where Cs is collector-substrate and interconnect capacitances. Both equations show that the load resistor
and bias (which affects gm and device capacitors) have a strong effect on performance.
For a rough estimate of the CML maximum speed without loading, one can assume that ft is the gain
bandwidth product. With the voltage gain set at gmRL, the maximum speed is ft/(gmRL). In the above
example, at 1 mA average bias, gm,int = 1/26 S at room temperature. Assuming the internal parasitic emitter
resistance RE is 10 ohms and using the fact that gm,ext = gm,int /(1 + REgm,int), the effective extrinsic gm is
1/36 mhos. With a 200-ohm load resistor, the voltage gain is approximately 5.5. With a 70-GHz ft HBT
process, the maximum switching rate is about 13 GHz. Although this estimate is quite rough, it does
show that high-speed CML logic desires high device bias and low logic swing. In most differential circuits,
only 3 to 4 kT/q is needed to switch the transistors and overcome the noise floor. With such low levels
17-14 VLSI Technology
FIGURE 17.11 Standard differential ECL buffer with outputs taken at two different voltage levels.
and limited gain, the output may not saturate to the logic extremes, resulting in decreasing noise margin.
In practice, the differential logic level should not be allowed to drop below 225 mV. With a 225-mV
swing vs. 400 mV, the maximum gate bandwidth improves to 23 GHz from 13 GHz.
Emitter-Coupled Logic
By adding emitter followers to the basic HBT CML buffer, the HBT ECL buffer is formed in Fig. 17.11.
From a dc perspective, the emitter followers (Qef1 and Qef2 ) shift the CML logic level down by Vbe . With
the outputs at VoutA/VoutA′ and 400 mV swing from the differential pair, the first level ECL logic high is
–1.4 V and the ECL logic low is –1.8 V. For some ECL logic gates, a second level is created through a
Schottky diode voltage shift (Def1/Def2). The typical Schottky diode turn-on voltage for GaAs is 0.7 V, so
the output at VoutB/VoutB′ is –2.1 V for a logic high and –2.5 V for a logic low. In general, the HBT ECL
levels differ quite a bit from the standard Si ECL levels. Although resistors can be used to bias Qef1/Qef2 ,
current mirrors (Qcs1/Qcs2 and Rcs1/Rcs2 ) are typically used. Current mirrors offer stable bias with logic
level at the expense of higher capacitance, while resistors offer lower capacitance but the bias varies more
and may be physically quite large.
From an ac point of view, emitter followers have high input impedance (approximately β times larger
than an unbuffered input) and low output impedance (approx. 1/gm), which makes it an ideal buffer. In
comparison with CML gates, since the differential pair now drives a higher load impedance, the effect
of loading is reduced, yielding increased bandwidth, faster edge rates, and higher fan-out. The cost of
this improvement is the increase in power due to the bias current of the emitter followers. For example,
in a 50 GHz HBT process, a CML buffer (fan-out = 1, Ibias = 2mA, RL1/RL2 = 150 Ω), the propagation
delay (tD) is 14.8 ps with a risetime [20 to 80%] (tr) of 31 ps and a falltime [20 to 80%] (tf ) of 21 ps. In
comparison, an ECL buffer with level 1 outputs (fan-out = 1, Ibias = 2 mA, Ibias1/Ibias2 = 2 mA, RL1/RL2 =
150 Ω) has td = 14 ps, tf = 9 ps, and tr = 17 ps. With a threefold increase in Pdiss, the impedance
transformation of the EF stage results in slightly reduced gate delays and significant improvements in
the rise/falltimes. With the above ECL buffer modified for level 2 (level shifted) outputs, the performance
is only slightly lower with tD = 14.2 ps, tf = 11 ps, and tr = 22 ps.
In general, emitter followers tend to have bandwidths approaching the ft of the device, which is
significantly higher than the differential pair. Consequently, it is possible to obtain high-speed operation
with the EF biased lower than would be necessary to obtain the maximum device ft. With the ECL level 1
Logic Design Examples 17-15
buffer, if the Ibias1/Ibias2 is lowered to 1 mA from 2 mA, the performance is still quite high, with td = 15
ps, tf = 13 ps, and tr = 18 ps. Although tD approaches the CML case, the tf and tr are still significantly better.
As the EF bias is increased, its driving ability is also increased; however, at some point with high bias,
the output impedance of the EF becomes increasingly inductive. When combined with large load capac-
itance (as in the case of high fan-out or long interconnect), it may result in severe ringing in the output
that can result in excessive jitter on data edges. The addition of a series resistor between the EF output
and the next stage can help to dampen the ringing by increasing the real part of the load. This change,
however, increases the RC time constant, which usually results in a significant reduction in performance.
In practice, changing the impedance of the EF bias source (high impedance current source or resistor
bias) does not have a significant effect on the ringing. As a result, the primary method to control the
ringing is through the EF bias, which places a very real constraint on bandwidth, fan-out, and jitter that
needs to be considered in the topology of real designs. In some FET DCFL designs, several source followers
are cascaded together to increase the input impedance and lower the output resistance between two
differential pairs for high-bandwidth drive. Due to voltage headroom limits, it is very difficult to cascade
two HBT emitter followers without causing the current source to enter deep saturation. In general, ECL
gates are typically used for the high-speed sections due to significant improvement in rise/falltimes
(bandwidth) and drive ability, although the power dissipation is higher.
CML or the ECL1 inputs, and the bottom level can be driven by ECL1 and ECL2 levels. The choice of
logic input levels is typically dictated by the design tradeoff between bandwidth, power dissipation, and
fan-out. As seen in Fig. 17.12, only when VinA and VinB are high will Ibias current be steered into the load
resistor that makes Vout = VOH. All other combinations will make Vout = VOL, as required by the AND
function. Due to the differential nature, if the output terminal labels were reversed, this would be a
NAND gate.
For the worst-case voltage headroom, VinA/VinA′ is driven with ECL1 levels, resulting in Vcm1 of –2.8 V.
With an ECL2 high on VinB (–2.1 V), the lower stage (Q3/Q4) has a B-C forward-bias of 0.7 V, which may
result in a slight saturation. This also implies that Vcm2 is around –3.5 V, which results in an acceptable
nominal 100 mV forward-bias on the current source transistor (Qcs). As Vee becomes less negative, the
change in Vee is absorbed across Qcs, which places Qcs closer into saturation. In saturation, the current
source holds Ie in Qcs constant; so if Ib increases (due to saturation), then Ic decreases. For some current
source reference designs that cannot source the increased Ib, the increased loading due to saturated Ib
may lower Vref , which would have a global effect on the circuit bias. If the current source reference can
support the increase in Ib , then the bias of only the local saturated differential pair starts to decrease
leading to the potential of lower speed and lower logic swing. For HBTs, the worst-case Qcs saturation
occurs at low temperature, and the worst-case saturation for Q3 /Q4 occurs at high temperature since Vbe
changes by –1.4 mV/C and Vdiode = –1.1 mV/C (for constant-current bias). It is possible to decrease the
forward-bias of the lower stage by using the base-emitter diode as the level shift to generate the second
ECL levels; however, the power supply voltage needs to increase from –5.2 to possibly –6 V.
With the two-level issues in mind, Fig. 17.13 illustrates the topology for a two-level OR/NOR gate.
This design is similar to an AND gate except that Vout = VOL if both VinA and VinB are low. Otherwise,
Vout = VOH. By using the bottom differential pair to select one of the two top differential pairs, many
other prime logic functions can be implemented. In Fig. 17.14, the top pairs are wired such that Vout =
VOL if VinA = VinB, forming the XOR/XNOR block. If the top differential pairs are thought of as selectable
buffers with a common output as shown in Fig. 17.15, then a basic 2:1 MUX cell is formed. Here, VinB /VinB′
determines which input (VinA1/VinA1′ or VinA2/VinA2′) is selected to the output. This concept can be further
extended to a 4:1 MUX if the top signals are CML and the control signals are ECL1 and ECL2, as shown
in Fig. 17.16. Here, the MSB (ECL1) and LSB (ECL2) determine which of the four inputs are selected.
With the 2:1 MUX in mind, if each top differential pair had separate output resistors with a common
input, a 1:2 DEMUX is formed as shown in Fig. 17.17.
The last primary cell of importance is the latch. This is shown in Fig. 17.18. Here, the first differential
pair is configured as a buffer. The second pair is configured as a buffer with positive feedback. The positive
feedback causes any voltage difference between the input transistors to be amplified to full logic swing
and that state is held as long as the bias is applied. With this in mind, as the first buffer is selected (VinB =
VOH), the output is transparent to the input. As VinB = VOL, the last value stored in the buffer is held,
forming a latch, which, in this case, is triggered on the falling edge of the ECL2 level. When two of these
blocks are connected together in series, it forms the basic master-slave flip-flop.
on either Q1/Q2 , leading to the longest propagation delay. In this case, the longest delay limits the usable
bandwidth of the AND gate. Likewise, in the XOR case, the delay of the top input is shorter than the
lower input, which results in asymmetric behavior and reduced bandwidth. For a 10-GHz flip-flop, this
can result in as much as a 10-ps delay from the rising edge of the clock to the sample point of the data.
This issue must be taken into account in determining the optimal input data phase for lowest bit errors
when dealing with digital data.
One solution to the delay issue is to use a quasi-differential signal. In Fig. 17.19, a single-ended single-
level OR/NOR gate is shown. Here, a reference generator of (VH + VL)/2 is applied to VinA′. If either of
the VinA1 or VinA2 is high, then Vout = VOH. This design has more bandwidth than the two-level topology
shown in Fig. 17.12, but some of the noise margin may be sacrificed.
Figure 17.20 shows an example of a single-level XOR gate with a similar input level reference. In this
case, Ibias1 = Ibias2 = Ibias3 . The additional Ibias3 is used to make the output symmetric. Ignoring Ibias3 , when
VinA is not equal to VinB, Ibias1 and Ibias2 are used to force Vout′ = VOL. When VinA = VinB, Vout = Vout′ since
both are lowered by Ibias , resulting in an indeterminate state. To remedy this, Ibias3 is added to Vout to make
the outputs symmetric. This design results in higher speed due to the single-level design; however, the
noise margin is somewhat reduced due to the quasi-differential approach and the outputs have a com-
mon-mode voltage offset of RLIbias .
In a standard differential pair, the output load capacitance can be broken into three parts. The base-
collector capacitance of the driving pair, the interconnect capacitance, and the input capacitance of the
next stage. The interconnect capacitance is on the order of 5 to 25 fF for adjacent to nearby gates. The
base-collector depletion capacitance is on the order of 25 fF. Assuming that the voltage gain is 5.5, the
effective Cbc or Miller capacitance is about 140 fF. Cbe,j , when the transistor is off, is typically less than
6 fF. The Cbe,d capacitance when the transistor is on is of the order of 50 to 200 fF. These rough numbers
show that the Miller effect has a significant effect on the effective load capacitance. For the switching
transistor, the Miller effect increases both the effective internal Cbc as well as the external load. In these
situations, a cascode stage may result in higher bandwidth and sharper rise/falltimes with a slight increase
in propagation delay. Figure 17.21 shows a CML gate with an added cascode stage. Due to the 400-mV
logic swing, the cascode bases are connected to ground. For higher swings, the cascode bases can be
biased to a more negative voltage to avoid saturation. The cascode requires that the input level be either
Logic Design Examples 17-21
ECL1 or ECL2 to account for the Vbe drop of the cascode. Since the base of the cascode is held at ac
ground, the Miller effect is not seen at the input of the common-base stage as the output voltage swings.
From the common-emitter point of view, the collector swings only about 60 mV per decade change in
Ic ; thus, the Miller effect is greatly reduced. The reduction of the Miller effect through cascoding reduces
17-22 VLSI Technology
FIGURE 17.22 CML buffer with a cascode output stage and bleed current to keep the cascode “on.”
the effect of both the internal transistor Cbc and load capacitance due to Cbc of the other stages, which
results in the reduced rise/falltimes, especially at the logic transition region.
As both of the transistors in a cascode turn off, the increased charge stored in both transistors that
has to discharge through an RC time constant may result in a slower edge rate near the logic high of a
rising edge. In poorly designed cascode stages, the corner point between the fast-rising edge to the slower-
rising edge may occur near the 20/80% point, canceling out some of the desired gains. Furthermore,
with the emitter node of the off common-base stage floating in a high-impedance state, its actual voltage
varies with time (large RC discharge compared to the switching time). This can result in some “memory”
effects where the actual node voltage depends on the previous bit patterns. In this case, as the transistor
turns on, the initial voltage may vary, which can result in increased jitter with digital data. With these
effects in mind, the cascoded CML design can be employed with performance advantages in carefully
considered situations.
One way to remedy the off cascode issues is to use prebias circuits as shown in Fig. 17.22. Here, the
current sources formed with Qpreb1 and Qpreb2 (Iprebias Ibias ) ensures that the cascode is always slightly
on by bleeding a small bias current. This results in improvements in the overall rise- and falltimes, since
the cascode does not completely turn off. This circuit does, however, introduce a common-mode offset
in the output that may reduce the headroom in a two-level ECL gate that it must drive. Furthermore, a
series resistor can be introduced between the bleed point and the current source to decouple the current
source capacitance into the high-speed node. This design requires careful consideration to the design
tradeoffs involving the ratio of Ibias/Iprebias as well as the potential size of the cascode transistor vs. the
switch transistors for optimal performance. When properly designed, the bleed cascode can lead to
significant performance advantages.
In general, high-speed HBT circuits require careful consideration and design of each high-speed node
with respect to the required level of performance, allowable power dissipation, and fan-out. The primary
tools the designer has to work with are device bias, device size, ECL/CML gate topology, and logic level
to optimize the design. Once the tradeoff is understood, CML/ECL HBT-based circuits have formed
Logic Design Examples 17-23
some of the faster circuits to date. The performance and capability of HBT technology in circuit appli-
cations are summarized below.
FIGURE 17.23 2:1 Frequency divider based on two CML latches (master/slave flip-flop).
17-24 VLSI Technology
and 26-GHz variable gain-limiting amplifiers24) have been demonstrated with HBTs in the research lab.
In general, the system-level specifications (SONET) for telecommunication systems are typically very
stringent compared with data communication applications at the same bit rate. The tighter specifications
in telecom applications are due to the long-haul nature and the need to regenerate the data several times
before the destination is reached. Today, there are many ICs that claim to be SONET-compliant at OC-48
(2.5 Gb/s) and some at OC-192 (10 Gb/s) bit rates. Since the SONET specifications apply on a system
level, in truth, there are very few ICs having the performance margin over the SONET specification for
use in real systems. Due to the integration level, high-speed performance, and reliability of HBTs, some
of the first OC-48 (2.5 Gb/s) and OC-192 (10 Gb/s) chip sets (e.g., preamplifiers, limiting amplifiers,
clock and data recovery circuits, multiplexers, demultiplexers, and laser/modulator drivers) deployed are
based on GaAs HBTs. A 16 × 16 OC-192 crosspoint switch has been fabricated with a production 50
GHz ft and fmax process.25 The LSI capability of HBT technology is showcased with this 9000 transistor
switch on a 6730 × 6130 µm2 chip. The high-speed performance is illustrated with a 10 Gb/s eye diagram
shown in Fig. 17.24. With less than 3.1 ps of RMS jitter (with four channels running), this is the lowest
jitter 10-Gb/s switch to date. At this time, only two 16 × 16 OC-192 switches have been demonstrated25,26
and both were achieved with HBTs. With a throughput of 160,000 Mb/s, these HBT parts have the largest
amount of aggregate data running through it of any IC technology.
In summary, III-V HBT technology is a viable high-speed circuit technology with mature levels of
integration and reliability for real-world applications. Repeatedly, research labs have demonstrated the
world’s fastest benchmark circuits with HBTs with ECL/CML-based circuit topology. The production
line has shown that current HBTs can achieve both the integration and performance level required for
high-performance analog, digital circuits, and hybrid circuits that operate in the high gigahertz range.
Today, the commercial success of HBTs can be exemplified by that fact that HBT production lines ship
several million HBT ICs every month and that several new HBT production lines are in the works. In
the future, it is expected that advances in Si based technology will start to compete in the markets currently
held by III-V technology; however, it is also expected that III-V technology will move on to address ever
higher speed and performance issues to satisfy our insatiable demand for bandwidth.
FIGURE 17.24 Typical 10 Gbps eye diagram for OC-192 crosspoint switch.
Logic Design Examples 17-25
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Injection Logic, IEEE Trans. Elect. Dev., 36, 2083, 1989.
19. Johnson, R. A. et al., Comparison of Microwave Inductors Fabricated on Silicon-on-Sapphire and
Bulk Silicon, IEEE Microwave and Guided Wave Letters, 6, 323, 1996.
19a. Ashar, K. G., The Method of Estimating Delay in Switching Circuits and the Fig. of Merit of a
Switching Transistor, IEEE Trans. Elect. Dev., ED-11, 497, 1964.
17-26 VLSI Technology
19b. Asbeck, P. M., Bipolar Transistors, High-Speed Semiconductor Devices, S. M. Sze, Ed., John Wiley &
Sons, New York, 1990, Chap. 6.
19c. Matthews, J. W. and Blakeslee, A. E., Coherent Strain in Epitaxially Grown Films, J. Crystal Growth,
27, 118, 1974.
20. Jensen, J., Hafizi, M., Stanchina, W., Metzger, R., and Rensch, D., 39.5 GHz Static Frequency Divider
Implemented in AlInAs/GaInAs HBT Technology, presented at IEEE GaAs IC Symposium, Miami,
FL, 103, 1992.
21. Lee, Q., Mensa, D., Guthrie, J., Jaganathan, S., Mathew, T. et al., 60 GHz Static Frequency Divider
in Transferred-substrate HBT Technology, presented at IEEE International Microwave Symposium,
Anaheim, CA, 1999.
22. Nary, K. R., Nubling, R., Beccue, S., Colleran, W. T. et al., An 8-bit, 2 Gigasample per Second
Analog to Digital Converter, presented at 17th Annual IEEE GaAs IC Symposium, San Diego, CA,
303, 1995.
23. Runge, K., Pierson, R. L., Zampardi, P. J., Thomas, P. B., Yu, J. et al., 40 Gbit/s AlGaAs/GaAs HBT
4:1 Multiplexer IC, Electronics Letters, 31, 876, 1995.
24. Yu, R., Beccue, S., Zampardi, P., Pierson, R., Petersen, A. et al., A Packaged Broadband Monolithic
Variable Gain Amplifier Implemented in AlGaAs/GaAs HBT Technology, presented at 17th Annual
IEEE GaAs IC Symposium, San Diego, CA, 197, 1995.
25. Metzger, A. G., Chang, C. E., Campana, A. D., Pedrotti, K. D., Price, A. et al., A 10 Gb/s High
Isolation 16×16 Crosspoint Switch, Implemented with AlGaAs/GaAs HBT’s, to be published, 1999.
26. Lowe, K., A GaAs HBT 16×16 10 Gb/s/channel Cross-Point Switch, IEEE J. Solid-State Circuits, 32,
1263, 1997.
Index
I-1
I-2 VLSI Technology
Dielectric isolation (DI), 1-14, 8-2, 8-4–8-6, 8-9, See also etch stop methods, 10-8, 10-10
Silicon on insulator (SOI) technology isotropic, 10-8
Dielectrics for thin-film processing, 12-5 xenon difluoride sublimation, 10-11
Differential epitaxy, 3-20 Ethylenediamine-pyrocatechol (EDP), 10-5
Diffused resistors, 7-10 Excimer laser lithography, 2-9
Digital systems, 1-3–1-9, See also CMOS technology; spe-
cific applications, components F
memory scaling, 1-7–1-9 Fabrication methods, See Micromachining; specific appli-
power dissipation, 1-3–1-5 cations, methods, technologies
signal delay, 1-6 Ferrites, 7-6
Diode noise, 9-7 Field effect transistors (FETs), 15-6, See also MOSFETs
Direct-coupled FET logic (DCFL), 16-2–16-3, 17-1–17-3 bipolar transistor comparison, 15-12–15-13
speed limitations, 17-8 charge control analysis, 15-7–15-9
Display systems, 10-37–10-39 chemical sensitivity, 10-53–10-54
DMOS, 8-1–8-2 direct-coupled logic design, 16-2–16-3, 17-1–17-3
DMOSFETs, 8-14–8-15 high electron mobility transistor (HEMT), 15-15
DNA computing, 1-18 MESFET, See Metal-semiconductor FETs
Dopant-selective etch stop, 10-10 noise, 9-9–9-10, 15-13
Double-diffused MOSFETs, 4-5 performance, 15-15–15-16
Double-poly transistor, 3-11, 3-14, 3-15, 3-17–3-19 SiGe technology, 5-8–5-10
DRAM, 2-15 source-coupled logic design, 16-3–16-5, 17-3–17-7
integrated systems, 1-16, 2-14–2-17, See also Embedded typical device structures, 15-14–15-16
memory Field plate, 8-6, 8-8
power efficiency, 1-8 FIPOS, 4-3
Dual damascene metallization, 2-12 Flash memory, 2-16–2-17
Dual-gate CMOS, 2-6 Flicker noise, 9-5, 9-7–9-10
Dual-in-line packages (DIPs), 11-7 Flip-chip packages, 11-9
Dual-poly capacitors, 1-13
Floating-body effects, 4-9–4-10
Dynamic-threshold MOSFET (DT-MOSFET), 4-10
Frequency divider, 17-8–17-9
Dynamic frequency divider, 17-8–17-9 maximum switching rate, 17-23
Dynamic noise margin (DNM), 16-7 Full isolation by porous oxidized silicon (FIPOS), 4-3
E G
EDP, 10-5 GAA transistor, 4-6
Electroplating into molds, 10-22 Gallium arsenide (GaAs) technology, 14-2
Electrostatic comb drive actuators, 10-40 ADC and DAC HBT applications, 17-23
Elmore delay, 16-12–16-13 comparison with SiC, 6-3
Embedded memory, 1-16, 2-14–2-17 direct-coupled FET logic, 17-1–17-3
capacitor cells, 2-15 GaAs/AlGaAs, comparison silicon BJT, 17-11
fabrication cost, 2-15 GaAs/AlGaAs P-HEMT, 17-9
flash memory, 2-16–2-17 GaAs/InGaP, comparison with silicon BJT, 17-11
gate oxide thickness, 2-15 heterojunctions, 14-3–14-5, 15-9, See also Heterojunc-
MOSFET structure, 2-15 tion bipolar transistors
next-generation DRAM, 2-15–2-16 high-speed MUX design, 17-7–17-8
Emitter-coupled logic (ECL), 17-14–17-23 integrated RF power amplifiers, 1-12
Emitter design, bipolar technology, 3-7–3-8, 3-13 laser mirrors in, 10-30
Emitter doping, 3-19 MESFET performance, 15-15, See also Metal-semicon-
Energy-delay product (EDP), 1-4 ductor FETs
EPIC, 8-2, 8-5 micromachining, 10-23
Epitaxial base bipolar technology, 3-19–3-20 Gallium-indium-arsenide quantum well formation, 15-15
Epitaxial channel MOSFET, 2-19 Gallium nitride (GaN) blue LEDs, 6-17
Epitaxial crystal growth methods, 4-2–4-3 Gas sensors, 6-23, 10-52, 10-54
Epitaxial resistors, 7-10 high-temperature operations, 10-55–10-57
Etching technology, 10-4–10-8, See also Micromachining; Gate all-around (GAA) transistor, 4-6
Reactive ion etching; specific methods Gate delay (td), bipolar circuits, 3-2, 3-8, 3-22
bulk machining of silicon, 10-2–10-14, See also Silicon, Gate electrode, 2-8–2-9
bulk micromachining raised gate/source/drain FET, 2-21
chemical etchants, 10-5–10-8 Gate insulators, embedded flash memory, 2-16–2-17
dopant-selective etch stop, 10-10 Gate length
electrochemical machining and porous silicon, 10- CMOS inverter propagation delay and, 2-10
10–10-12
I-4 VLSI Technology
MOSFET performance and, 2-9 High-voltage technology, 8-6–8-18, See also High-power
Gate oxide, 2-7–2-8 applications and devices; Power integrated circuits;
thickness, for embedded memory, 2-15 specific devices, technologies
tunneling current and, 2-8 edge termination, SiC power devices, 6-21–6-22
ultra-thin, 2-18–2-19 field plate, 8-6
Gate oxide degradation, hydrogen-related hot-carrier effect, interconnection, 8-7–8-8
13-1–13-14 output devices, 8-14–8-17
annealing in deuterium and, 13-1–13-2, 13-5–13-12 RESURF, 8-6–8-7
cost, 13-12 SOI, 8-8–8-20
deuterium localization observations, 13-11 lateral IGBTs, 8-16–8-17
device lifetime improvement, 13-1, 13-7–13-8 Hole mobility, 5-9, 15-7
interconnection issues, 13-6–13-7 Hot carrier degradation, 13-1–13-12
mechanisms, 13-2–13-4 deuterium isotope substitution effect, 13-1–13-2, 13-
mitigation strategies, 13-4 5–13-12
Generation-recombination noise, 9-4–9-5 mechanisms, 13-2–13-4
Germanium-silicon technology, See Silicon-germanium mitigation strategies, 13-4
(Si-Ge) technology SOI devices, 4-4
Gold, 12-6 HTCC materials, 12-3, 12-4
Ground bounce noise, 11-13, 16-6–16-7 Hydrogen-related hot electron degradation effect, 13-1–13-
Gunn effect, 15-7 12, See also Hot carrier degradation
Hydrogen-silicon bond, 13-1–13-2
H
HBTs, See Heterojunction bipolar transistors I
HEMTs, See High electron mobility transistors IDP emitter, 3-19
Hermetic packaging, 11-10–11-11 IGBTs, See also Bipolar junction transistors
Heterojunction bipolar transistors (HBTs), 3-19–3-20, 15- dielectric isolation method, 8-6
9–15-12, 15-16 high-temperature performance, 8-20
ADC and DAC applications, 17-23 high-voltage power ICs, 8-16–8-17
analog systems, 1-10 Implanted base bipolar technology, 3-1
FET comparison, 15-12–15-13 Indium-aluminum-arsenide (InAlAs) systems, 14-5, 17-8
logic design Indium channel doping, 2-6
circuit design examples, 17-23–17-24 Indium-gallium-arsenide (InGaAs) HEMT performance,
current-mode logic, 17-12–17-22 15-15
emitter-coupled logic, 17-14–17-23 Indium phosphide (InP) technology, 14-2
III-V HBT circuit design, 17-10–17-12 HEMT performance, 15-15
noise, 9-8 heterojunction devices, 15-16
performance, 15-16–15-17 quantum well formation, 15-15
Si BJTs vs. III-V HBTs, 17-10–17-11 Inductance
SiGe technology, 5-3–5-8 formula, 7-8
typical device structures, 15-16–15-17 package parasitics, 11-13
Heterojunction FET, SiGe technology, 5-8–5-10 Inductors, 2-14, 7-8–7-9
Heterojunction technology, 14-3–14-5 amplifier circuit integration, 10-44
HEXSIL, 10-22 noise, 9-6
High-density interconnect (HDI) modules, 12-2 on-chip integration, 1-13
High electron mobility transistors (HEMTs), 5-9, 15-15 power systems, 1-14
high-speed TDM, 17-8 quality factor (Q), 1-13
static logic design, 16-2 Ink-jet printers, micromachining, 10-51
High-power applications and devices, See also High-voltage In situ phosphorus doped polysilicon (IDP) emitter, 3-19
technology; Power devices and systems Insulated gate bipolar transistor, See IGBTs
SiC devices, 6-4–6-8, 6-20–6-23 Intelligent power systems, 1-13, 8-2–8-6, See also Smart
switches, SiC, 6-22–6-23 power technology
High-speed device design example, 17-7–17-8 Interconnections and contacts, 11-1, See also Packaging;
High-speed performance, III-V semiconductor systems, Passive components
14-2–14-3, See also Compound semiconductors analog and RF systems, 1-12–1-13
High-temperature co-fired alumina (HTCC), 12-3, 12-4 CMOS, 2-12
High-temperature gas sensors, 10-55–10-57 Cu vs. Al, 1-7
High-temperature performance deuterium anneal effects, 13-6–13-7
SiC devices, 6-1, 6-4, 6-18–6-20 extreme conditions and, 6-13–6-14, 6-16
SOI power ICs, 8-20 noise, 9-16–9-17
High-voltage ICs (HVICs), 1-13, See Power integrated package parasitics, 11-12–11-13
circuits power systems, 1-14, 8-7–8-8
Index I-5
optical MEMS, 10-30–10-39, See also Optical microelec- ultra-thin gate oxide, 2-18–2-19
tromechanical systems MOS resistors, 7-10
processes, 10-2 MOST, 1-10
RF passive components, 10-44 Motor control applications, 8-18, See also Microelectrome-
SCREAM, 10-22 chanical systems
SiC patterned etching, 6-15 Multichip module (MCM) technology, 11-10, 12-1–12-12
silicon bulk machining, 10-2–10-14, See also Silicon, aluminum nitride co-fired substrate (AIN), 12-3, 12-5
bulk micromachining assembly techniques, 12-9–12-11
stiction, 10-16 carrier substrates, 12-5–12-6
surface, 10-15–10-16 choosing substrate technologies, 12-6–12-9
thermal devices, 10-45–10-48 co-fired ceramic (MCM-C), 12-3–12-6
thin film materials properties, 10-16 conductor metallization, 12-6
tuning fork oscillators, 10-45 high-temperature co-fired alumina (HTCC), 12-3, 12-4
wafer bonding, 4-3–4-4, 10-29–10-30 laminate (MCM-L), 12-2–12-3
wireless packages, 11-14 low-temperature co-fired ceramic (LTCC), 12-3, 12-4
Micropipes, 6-7, 6-9, 6-11, 6-19, 6-20 packaging efficiency, 12-2, 12-3
Microrelays, 10-43, 10-49–10-50 thin-field dielectrics, 12-5
Microsensors, See Sensors MUMPS, 10-16
Microvibromotor, 10-40 MUX logic design, 17-7–17-8
Microwave transmission lines, 10-44
Microwave waveguides, 10-44 N
Miller effect, 17-20–17-22
Neural networks, 1-18
Mirror micromachining, 10-30, 10-34–10-37
Neural probes, 10-58
Mixed-signal bipolar systems, 2-18, 3-1, 3-22 Nitrogen doping, SiC, 6-11
Molecular beam epitaxy, 15-16 NMOS transistors
Molecular computing, 1-18 CMOS, 2-1
MOS capacitors, 1-13, 7-11 H/D isotope effect and hot-channel degradation,
MOSFETs, 2-1, 15-14, See also CMOS technology; Field
13-1–13-12
effect transistors
SiGe FET, 5-9–5-10
channel doping, 2-5–2-7 Node capacitance scaling, 1-6–1-7
DMOSFETs, 8-14–8-15 Noise, 9-1–9-19
double-diffused MOSFETs, 4-5 amplifiers, 9-10–9-14
dynamic-threshold (DT-MOSFET), 4-10 BJTs, 9-7–9-9
embedded DRAM, 2-15 chemical sensor arrays, 10-57–10-58
epitaxial channel, 2-19 chip, 9-10–9-17
fabrication process, See CMOS technology, fabrication crosstalk, 9-16, 11-3, 11-13, 16-7
process devices, 9-6–9-10
gate dielectric, 2-7–2-8 diodes, 9-7
gate length and performance, 2-9 dynamic noise margin (DNM), 16-7
hot-carrier degradation and deuterium annealing effect, FETs, 9-9–9-10
13-1–13-12, See also Gate oxide degradation, FETs vs. bipolar transistors, 15-13
hydrogen-related hot-carrier effect flicker, 9-5, 9-7–9-10
low-noise amplifiers, 1-11 future trends, 9-17–9-19
noise sources, 9-9–9-10 generation-recombination, 9-4–9-5
raised gate/source/drain structure, 2-21 ground bounce, 11-13, 16-6–16-7
resistor, 7-10 interconnects, 9-16–9-17
SiC technology, 6-15–6-16 microscopic, 9-2–9-6
SOI transistors, 4-6–4-10 non-equilibrium transport, 9-18–9-19
defect coupling, 4-9 oscillators, 9-14–9-15
dynamic-threshold MOSFET, 4-10 package design considerations, 11-3, 11-13, 16-7
floating-body effects, 4-9–4-10 passive components, 9-6–9-7
full depletion, 4-6–4-9
processing, 9-17–9-18
minimum dimensions, 4-12
quantum effects, 9-6
partial depletion, 4-9–4-10
scaling, 9-17
pseudo-MOSFET (Y-MOSFET), 4-12
shot, 9-3–9-4, 9-6, 9-7, 9-18–9-19
short-channel effects, 4-10–4-11
SiGe HBT properties, 5-7–5-8
subthreshold slope, 4-8
thermal, 9-2–9-3, 9-6–9-9, 9-17–9-18
threshold voltage, 4-7–4-8
timing jitter, 9-15–9-16
transconductance, 4-8–4-9
Noise figure (NF), 1-11
volume inversion, 4-9
bipolar circuits, 3-3
source/drain, 2-9–2-10, 2-15
Noise margins, 16-1, 16-5–16-8
Index I-7
Noise measure, for amplifiers, 9-13 p-channel FET (pFET), SiGe bandgap engineering, 5-9
Nuclear magnetic resonance, 1-18 Permalloy, 7-6–7-7
pH selective FET, 10-53
O Phosphorus doped emitter, 3-19
Phosphosilicate glass (PSG), 10-15
Optical fiber communications, 17-7–17-8
Photodiodes, 6-17
Optical microelectromechanical systems, 10-30–10-39
Photoresists, 10-22
active gratings, 10-33–10-34
Pick-up heads, 10-39
actuators, 10-40–10-41
Pin grid arrays (PGAs), 11-8
components, 10-30
Pinched resistors, 7-10
display systems, 10-37–10-39
Plastic-leaded chip carriers (PLCCs), 11-9
modulators, 10-33
Plastic packaging, 11-5
pick-up heads, 10-39
PMOS transistors, CMOS, 2-1
piezoelectric devices, 10-37
p-n junction noise, 9-7
scanning mirrors, 10-34–10-37
pnp devices
spectrometer on chip, 10-37
bipolar technology, 3-11
Optical pick-up heads, 10-39
SiC optoelectronics, 6-17
OR/NOR gate, ECL/CML logic examples, 17-16–17-17,
Polycide, 2-8
17-20
Polysilicon emitter, 3-7, 3-13
Oscillators
micromachining, 10-45 Polysilicon gate electrodes, 2-8
noise, 9-14–9-15 Polysilicon surface micromachining, 10-15–10-16
Oxynitride gate dielectric, 2-7 Porous silicon, electrochemical machining, 10-10–10-12
Potassium hydroxide (KOH) etching, 10-4
Power-added efficiency, 1-12
P Power amplifiers, 1-12
Packaging, 11-1–11-14 Power devices and systems, 1-3, 1-13–1-14, See also Power
bare chip solutions, 11-14 integrated circuits; High-voltage technology
ceramic substrates, 11-5–11-6 electrical isolation, 1-14
design parameters, 11-2–11-5 interconnects and passive components, 1-14
die attachment techniques, 11-1–11-12 sensors, 8-18
extreme environments and, 6-16 SiC devices
future trends, 11-14 high-power performance, 6-1, 6-4–6-6, 6-20–6-23
hermetic, 11-10–11-11 high-voltage edge termination, 6-21–6-22
hierarchy, 11-2 rectifiers, 6-22
micromachining RF packages, 11-14 switches, 6-22–6-23
modeling, 11-13 smart power, 1-3, 1-13, 8-2–8-6
multichip modules, 12-2, 12-3, See also Multichip types, 1-13
module (MCM) technology Power dissipation
noise reduction, 16-7 bipolar circuits, 3-2
number of terminals, 11-3 digital systems, 1-3–1-5
parasitics, 11-12–11-13 memory systems, 1-8
plastic substrates, 11-5 SOI, 4-4, 4-10
reliability and testability, 11-5 static logic circuit, 16-8
SiC devices, 6-16 Power efficiency, quantum computing, 1-17
silicon-on-silicon hybrid, 11-10 Power gain-bandwidth product, 15-6
thermal and electric properties (table), 11-6 Power integrated circuits (PICs), 1-13, 8-1–8-20, See also
thermal design, 11-4–11-5, 11-14 Power devices and systems
3-D, 11-10 DMOSFETs, 8-1
types, 11-6–11-10 high-voltage technology, 1-13, 8-6–8-7
wireless applications, 11-13–11-14 field plate, 8-6
Parasitics packaging, 11-12–11-13 RESURF, 8-6–8-7
Partially depleted SOI MOSFETs, 4-9–4-10 intelligent power ICs, 8-2–8-6, See also Smart power
Passive components, 7-1–7-11, See also Capacitors; Induc- technology
tors; Interconnections and contacts; Resistors interconnection, 8-7–8-8
air core inductors, 7-8–7-9 output devices, 8-14–8-17
capacitors, 7-11 sense and protection circuit, 8-18
magnetic components, 7-1–7-7 SOI technology, 8-8–8-20
micromachining, RF and microwave devices, 10-44 high-temperature operation, 8-20
noise, 9-6–9-7 system integration, 8-19–8-20
resistors, 7-9–7-11 Power switch protection, 8-18
Patterned etching, SiC, 6-15 Pseudomorphic growth, 14-5
I-8 VLSI Technology
V W
Very high-speed technology, 14-1, 16-8–16-17 Wafer bonding (WB), 4-3–4-4, 8-6, 10-29–10-30
dynamic circuit design, 17-8–17-10 Wire bonding, 11-11
Elmore delay and risetime, 16-10–16-12 Wireless applications
open-circuit time constants, 16-12–16-16 packaging, 11-13–11-14
source-coupled FET logic, 17-3 VLSI applications, 1-10–1-11
time constant delay methods, 16-10–16-17
zero-order delay estimate, 16-8–16-10 X
VLSI systems, 1-1–1-8, See also specific applications, com- Xenon difluoride etching, 10-11, See also Reactive ion
ponents, systems etching
analog systems, 1-10–1-13 XOR/NOR gate, ECL/CML logic examples, 17-16, 17-20
digital systems, 1-3–1-9 X-ray lithography, LIGA, 10-22
DNA computing, 1-18
emerging technologies, 1-14–1-17
molecular computing, 1-18 Z
package-on-chip vs. board-level integration, 1-1–1-12 Zero-order delay estimate, 16-8–16-10
power systems, 1-3, 1-13–1-14, See also Power systems Zone melting recrystallization, 4-3
and devices
quantum computing, 1-17–1-18
Voltage noise spectral density, 9-2
Volume inversion, 4-9