Nothing Special   »   [go: up one dir, main page]
Scribd Logo
Upload

Welcome to Scribd!

  • 8 views

    U-1 Overview of HDL

    Uploaded by

    DEEPA KUNWAR
    The document provides an overview of HDL (Hardware Description Language). It discusses that HDLs like Verilog and VHDL are used to model digital circuits. Verilog is a more succinct hardware modeling language with C-like syntax, while VHDL is strongly typed and more wordy but easier to understand. The document also covers modules and instances in Verilog, different data types in HDL like integers and arrays, and simulation commands like $monitor.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    U-1 Overview of HDL

    Uploaded by

    DEEPA KUNWAR
    8 views14 pages
    The document provides an overview of HDL (Hardware Description Language). It discusses that HDLs like Verilog and VHDL are used to model digital circuits. Verilog is a more succinct hardware modeling language with C-like syntax, while VHDL is strongly typed and more wordy but easier to understand. The document also covers modules and instances in Verilog, different data types in HDL like integers and arrays, and simulation commands like $monitor.

    Original Description:

    Original Title

    u-1

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document provides an overview of HDL (Hardware Description Language). It discusses that HDLs like Verilog and VHDL are used to model digital circuits. Verilog is a more succinct hardware modeling language with C-like syntax, while VHDL is strongly typed and more wordy but easier to understand. The document also covers modules and instances in Verilog, different data types in HDL like integers and arrays, and simulation commands like $monitor.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    8 views14 pages

    U-1 Overview of HDL

    Uploaded by

    DEEPA KUNWAR
    The document provides an overview of HDL (Hardware Description Language). It discusses that HDLs like Verilog and VHDL are used to model digital circuits. Verilog is a more succinct hardware modeling language with C-like syntax, while VHDL is strongly typed and more wordy but easier to understand. The document also covers modules and instances in Verilog, different data types in HDL like integers and arrays, and simulation commands like $monitor.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 14

    u-1

    OVERVIEW OF HDL

    circuit
    Design Specifications describe abstractly the functionality, interface, and overall architecture
    of the circuit.
    A behavioral description is then created to analyse the design in terms of functionality,
    performance, and compliance to standards, and other high-level issues.
    The behavioral description is manually converted to an RTL description in an HDL.
    Logic synthesis tools convert the RTL description to a gate-level net list. Logic synthesis tools
    ensure that the gate-level net list meets timing, area, and power specifications.
    A gate-level net list is a description of the circuit in terms of gates and connections between
    them.
    The gate-level netlist is input to an Automatic Place and Route tool, which creates a layout.
    The layout is verified and then fabricated on a chip.

    Thus, most design activity is concentrated on manually optimizing the RTL


    description of the circuit. After the RTL description is frozen, EDA tools are
    available to assist the designer in further processes.
    they

    hence
    understand
    Logic designers decide the structure of design and break up the functionality
    functionality into blocks and sub blocks
    Then higher level are build using this leaf cell.

    EXAMPLE:
    4 bit ripple counter
    MODULE AND INTANCES
    Module: A module is the basic building block in Verilog. A module can be
    an element or a collection of lower-level design blocks. A module provides the
    necessary functionality to the higher-level block through its port interface
    (inputs and outputs), but hides the internal implementation.
    In Verilog, a module is declared by the keyword module. A corresponding
    keyword endmodule must appear at the end of the module definition.
    Each module must have a module_name, which is the identifier for the
    module, and a module_terminal_list, which describes the input and output
    terminals of the module.
    Internals of each module can be defined at four levels of abstraction,
    depending on the needs of the design.
    The level are as follows:
    • Behavioral level
    This is the highest level of abstraction provided by Verilog HDL. A module can
    be implemented in terms of the design algorithm
    • Dataflow level
    At this level, the module is designed by specifying the data flow.
    • Gate level
    The module is implemented in terms of logic gates and interconnections
    between these gates.
    • Switch level
    This is the lowest level of abstraction provided by Verilog. A module can be
    implemented in terms of switches, storage nodes, and the interconnections
    between them.

    Instance: A module provides a template from which you can create actual
    objects. When a module is invoked, Verilog creates a unique object from the
    template. Each object has its own name, variables, parameters, and I/O
    interface. The process of creating objects from a module template is called
    instantiation, and the objects are called instances
    For Example: ripple carry counter instantiates 4 T-flipflops.
    module ripple_carry_counter(q, clk, reset);
    output [3:0] q;
    input clk, reset;
    T_FF tff0(q[0],clk, reset);
    T_FF tff1(q[1],q[0], reset);
    T_FF tff2(q[2],q[1], reset);
    T_FF tff3(q[3],q[2], reset);
    Endmodule
    LEXICAL CONVENTION
    The lexical conventions used by Verilog HDL similar to those used in C
    programming language. The only difference is that it contains a
    stream of tokens. Tokens can be comments, delimiters, numbers,
    strings, identifiers, and keywords. Verilog HDL is a case-sensitive
    language. All keywords are in lowercase.
    3.1.1 Whitespace: whitespace comprise the Blank spaces (\b), tabs (\
    t) and newlines (\n).
    DATA TYPES IN HDL
    time save_time; // Define a time variable save_time

    ARRAY
    Arrays are allowed in Verilog for reg, integer, time, real, realtime and vector register data
    types. it is accessed by <array name>[<subscript>]

    integer count[0:7]; // An array of 8 count variables

    membyte[511] // Fetches 1 byte word whose address is 511.

    parameter n = 5; // Defines a constant n

    reg [8*18:1] string_value; // Declare a variable that is 18 bytes wide initial

    string_value = "Hello Verilog World"; // String can be stored // in variable


    $monitor continuously monitors the values of the variables or signals specified
    in the parameter list and displays all parameters in the list whenever the value
    of any one variable or signal changes. Unlike $display, $monitor needs to be
    invoked only once. Only one monitoring list can be active at a time. If there is
    more than one $monitor statement, the last $monitor statement will be the
    active statement. The earlier $monitor statements will be overridden.
    What are different available HDL
    There are several HDLs available but the most popular HDLs are Verilog and
    VHDL.
    Verilog: Verilog stands for verification logic. It is used to model and stimulate
    the Digital circuits Application-Specific Integrated Circuits (ASICs) and Field-
    Programmable Gate Arrays (FPGAs).
    Syntax:
    module module_name(inputs,output)
    //statements
    end module
    VHDL: VHDL stands for Very High-speed Integrated Circuit Hardware
    Description Language (VHSIC). It is used to design digital circuits. It is often
    used to design complex Digital circuits such as Microprocessors and Digital
    Signal Processors.
    Syntax:
    library ieee;
    use ieee.std_logic_1164.all;
    entity Circuit_name is
    Port ( a : in STD_LOGIC;
    b : in STD_LOGIC;
    out1 : out STD_LOGIC);
    end Circuit_1;
    architecture Behavioral of Circuit_name is
    begin
    // statements
    end Behavioral;

    VHDL vs Verilog
    VHDL Verilog

    Strongly typed Weakly typed

    Easier to understand Less code to write

    More natural in use More of a hardware modelling language

    Wordy Succinct

    Non-C-like syntax Similarities to the C language

    Variables must be described by data type A lower level of programming constructs

    Widely used for FPGAs and military A better grasp on hardware modeling

    More difficult to learn Simpler to learn

    You might also like