Synthesis

Synthesis is the process in which synthesis tools like design compiler or simplify
take RTL in Verilog or VHDL, target technology (.lib), and design constrains
(sdc) as input and maps the RTL to target technology primitives and produces a
gate- level netlist as output.
Synthesis tool, after mapping the RTL to gates, also do the minimal amount of
timing analysis to see if the mapped design is meeting the timing requirements.
Synthesis = translation + optimization + mapping

1
 • RTL Description
In order to adopt high-level design principles, it is necessary to try and
describe a design at a higher level of abstraction. This means thinking about the
functionality of the design rather than its implementation. This allows the
synthesis tool to optimize the functionality you have specified, leaving you to
describe what the design does, whilst the synthesis tool's job is to implement the
design how it sees fit in order to create the optimal implementation. The style of
coding required for synthesis tools is known as RTL coding.
RTL is an acronym for register transfer level. This implies that your VHDL
code describes how data is transformed as it is passed from register to register.
The transforming of the data is performed by the combinational logic that exists
between the registers.
Verilog HDL is one of the two most common Hardware Description
Languages (HDL) used by integrated circuit (IC) designers. ... More recently
Verilog is used as an input for synthesis programs which will generate a gate-
level description (a netlist) for the circuit. HDL like VHDL, Verilog and System
Verilog have synthesizable and non-synthesizable statements.Some Verilog
constructs are not synthesizable.

If a piece of HDL can be converted to a design with logic gates by a

synthesis tool, then it is synthesizable. E.g. System Verilog/Verilog example:

assign out = in_0 + in_1 ; // adder without handling carry overflow.

If a piece of HDL is used for creating reference events, trackers, displays,

file dumping, etc., and the synthesis tool cannot infer a digital circuit, then it is
non-synthesizable. E.g. System Verilog/ Verilog example: always #0.5 clk <=
~clk; // generation of clock with timescale specified in the file or simulator tool.

It is in the format of .vhd or .v

Synchronous designs run smoothly through synthesis, simulation and
place-and-route. Isolate necessary Asynchronous logic into separate blocks.

• Library
Design Compiler uses these libraries:
a) Technology libraries
b) Symbol libraries

2
 c) Design Ware libraries

a) Technology file library

Technology file defines basic characteristic of cell library pertaining to a
particular technology node (i.e 28nm,14nm,7nm etc).

They are units used in the design, graphical characteristics like colours, stipple
patterns, line styles, physical parameters of metal layers, coupling capacitances,
capacitance models, dielectric values, device characteristics, design rules.

A standard cell library is a collection of predesigned layouts of basic logic gates

like inverters, buffers, ANDs, ORs, NANDs etc.

All the cells in the library have same standard height and have varied width.
These standard cell libraries are known as reference libraries in Astro.

target_library (.db):
The target library is the technology library you want to map to during
synthesis. It is also known as the destination library.
Target library is used for technology mapping. All the combo (AND, NAND,
NOT, etc) and the sequential (SDFF, DFF, etc) are mapped to equivalent gates
from the target library. standard cell database (binary), cell area/pins/timing data
(for synthesis decisions).
Note: .db — Synopsys internal database format.

link_library (.db):
The link library is a technology library that is used to describe the
function of mapped cells prior to optimization. Typically, the link and target
library are set to the same technology library.

The link_library variable specifies every library that has cells referenced by the
netlist. The tool uses the libraries specified in the link_library variable for
resolving references (linking). The link_library can include memory (RAM,
ROM or any macro) libraries, in addition to the standard cell library.

b) symbol_library (.sdb)

3
 Symbol libraries contain definitions of the graphic symbols that represent
library cells in the design schematics. Semiconductor vendors maintain and
distribute the symbol libraries.
Design Compiler uses symbol libraries to generate the design schematic.
You must have Design Analyzer to view the design schematic.
When you generate the design schematic, Design Compiler performs a
one-to-one mapping of cells in the netlist to cells in the symbol library.

c) Design ware Libraries or synthetic_library (.sldb)

A Design ware library is a collection of reusable circuit-design building
blocks (components) that are tightly integrated into the Synopsys synthesis
environment.
If you are using additional Design Ware libraries, you must specify these
libraries, using the synthetic_library variable (for optimization purposes) and the
link_library variable (for cell resolution purposes).
Design Ware components that implement many of the built-in HDL
operators are provided by Synopsys. These operators include +, -, *, <, >, <=,
>=, and the operations defined by if and case statements. Additional Design
Ware libraries can be developed by users at their sites by using Design Ware
Developer,

• Design Constraints (SDC)

Design constraints are ASIC design specifications that are applied during logic
and physical synthesis.
1) Timing constraints
2)Design rule constraints

1) Timing constraints

Timing constraints are user-specified and are related to speed, area, and the
power consumption of the ASIC design.

The most basic timing constraints are as follows:

a) System clock definition and clock delays
b) Multiple cycle paths
c) Input and output delays
d) Minimum and maximum path delays
e) Input transition and output load capacitance
f) False paths

4
System clocks are typically supplied externally but can be generated inside an
ASIC. All delays, especially in a synchronous ASIC design, dependent upon the
system clocks.

Multiple cycle paths are for ASIC designs that have a non-single cycle clock
timing requirement. This directs the physical design tools to avoid optimization
of data paths that have non-single clock behaviour.

False paths are used to specify point-to-point non-critical timing either internal
or external to an ASIC design. Properly identifying these noncritical timing paths
has a great impact on physical design tools’ performance.

The physical design tools use the system clock definition to perform what is
known as Clock Tree Synthesis (CTS) and try to meet the clock networks’ delay
constraints.

2) Design rule constraints

Design rule constraints are imposed upon ASIC designs by requirements

specified in a given standard cell library or within physical design tools

Design rule constraints have precedence over timing constraints because

they have to be met in order to realize a functional ASIC design. There are
four types of major design rule constraints:

a) Maximum number of fan-outs

b) Maximum transitions
c) Maximum capacitance
d) Maximum wire length

Design Environment

• Setting Design Environment

• Setting Operating Environment
• Setting Input Driving Strength
• Setting Output Loading
• Setting Input/output Delay
• Setting Wire Load Model

5
SDC is a format used to specify the design intent, including the timing, power
and area constraints for a design. SDC contains mainly following constraints that
are very essential for design.

The constraints are the following types according the commands types:
✓ Basic commands
✓ Object Access Commands
✓ Timing Commands
✓ Environment Commands
✓ Multi-Voltage Commands

❖ Basic Constraints commands

These commands used to set the attributes from that instance
cmd: set: used to define variables
for example: set_units [-capacitance cap_unit] [-resistance res_units]
[-time time_unit] [-voltage voltage_unit]
[-current current_unit] [-power power_unit]

❖ Object Access Constraints commands

These commands specify how to access objects in a design instance.
these commands are used to get the location of an object in the design.
the object can be a cell, a block, a port, a pin, or anything else in the design.
for example:
all_clocks
# Returns a collection of all clocks.
Examples:
foreach_in_collection clkvar [all_clocks] {
. . .}
set_clock_transition 0.150 [all_clocks]
get_libs [-regexp] [-nocase] patterns
# Returns a collection of libraries that are currently
# loaded in the design.
❖ Timing Constraints commands

These commands are related to timing specifications of the design which

contains,
Clock definition : create_clock

6
Generated clock : create_generated_clock
Clock transition : set_clock_transition
Clock Uncertainty : set_clock_uncertainty
Clock Latency : set_clock_latency
Propagated clock : set_propagated_clock
Disable timing : set_disable_timing
False path : set_false_path
Input/output delay : set_input_delay & set_output_delay
Min/Max delay : set_min_delay / set_max_delay
Multicycle path : set_multicycle_path

❖ Environmental constraints

These commands are used to setup the environment of the design under analysis
commands are:
set_driving_cell
set_input_transition
set_load
set_max_fanout
set_max_area
set_operating_conditions
set_wire_load_model
set_case_analysis.......etc

❖ Multi-Voltage Commands

These commands apply when multi-voltage islands are present in s design.

create_voltage_area
set_level_shifter_strategy
set_level_shifter_threshold
set_max_dynamic_power
set_max_leakage_power

7
Setup and Synthesis Flow

Follow the given steps shown below

STEP 1: Login to the Linux system on Linuxlab server.

8
Start a terminal (the shell prompt).

“xterm” command is used to open a new terminal.

STEP 2: Build work environment for DC. Open the file location.

Using Setup Files

STEP 3: Getting started with Verilog.
Creating a new folder. Better if you have all the files for a sparc project in a
specific folder such as rtl, scripts, setup files, library files, unmapped.
Examine and modify the setup files
You are provided with a (dot). synopsys_dc.setup file.
It defines aliases and sources two other setup files:
1) common_setup.tcl 2) dc_setup.tcl.

o The common_setup.tcl file contains user defined variables (in UPPER

CASE letters) which specify technology file and directory names. These
variables are used in dc_seup.tcl.

o The dc_setup.tcl file executes commands to load the necessary logical

9
and physical technology data, using variables from common_setup.tcl.

10
A setup file contains commands that are automatically executed when you start a
software tool. The Synopsys synthesis tools use a setup file called
.synopsys_dc.setup. Use the setup file to define the libraries and parameters for
synthesis.

When you invoke Design Compiler, it reads the .synopsys_dc.setup file from
three directories, in the following order:
1. The Synopsys root directory
This system-wide file resides in the $SYNOPSYS/admin/setup directory for
UNIX users, or %SYNOPSYS%/admin for Windows NT users, and contains
general Design Compiler setup information. Only the system administrator can
modify this file.
2. Your home directory
This file contains your preferences for your Design Compiler working
environment.
3. The current working directory (the directory from which you invoke
Design Compiler)
If the setup files share commands or variables, values in the last setup file read
override values in previously read files. The working directory’s settings override
any default settings in your home or Synopsys directory.

STEP 4: Writing constraints file - “. tcl” file.

where modifications are required specific to model:
Using a text editor of your choice, edit common_setup.tcl and incorporate any
missing information.
o Set Path to Verilog files (.v) which are in rtl.
o Top module of the design have to be specified to specify the Hierarchy.
o Specifying the clock port used in the model.
o Clock frequency at which the model is operated.

11
To enter the data use button “i”. After editing save the file using command=>
“ESC :wq”.

Starting Design Compiler

STEP 5: Compile your code
Open the folder which contains the all the project files.
From here to invoke dc_shell, enter the dc_shell command at the system prompt:
❖ From the path of the project file enter > dc_shell
Program Header and Default Prompt
Design Compiler Graphical
DC Ultra (TM)
DFTMAX (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)

12
 HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)
Version L-2016.03-SP1 for linux64 - Apr 18, 2016
Copyright (c) 1988 - 2016 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and
conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, or distribution of this software is strictly prohibited.
Initializing...
Initializing gui preferences from file /home/pduser02/.synopsys_dv_prefs.tcl
dc_shell>
after entering the dc_shell run a command, now

Using Script Files

Execute a script file by using one of the following commands:
• include (dcsh)
• source (Tcl)
❖ Compile the files by typing in the terminal:
dc_shell> source scripts/dc_setup.tcl

The command log records the dc_shell commands processed by Design

Compiler, including setup file commands and variable assignments.
By default, Design Compiler writes the command log to a file called
command.log in the directory from which you invoked dc_shell.
You can change the command log name by setting the command_log_file
variable in a setup file. If you change the variable interactively during a Design
Compiler session, it does not have any effect.

13
After running this command, there might be some warning, but no error presented
in the terminal. Otherwise you need to check your code or tcl file and correct
them according to the related messages.
Note: The oldest messages might be lost due to too many lines printed on the
terminal. In this situation you could redirect the output to a file:
dc_shell> source scripts/dc_setup.tcl > sparc.log
Then you can open sparc.log using gedit and search in it. The “>” here is the sign
for Output Redirection in Linux shell.
When a script completes processing, dc_shell returns a value of 1 if the script ran
successfully or a value of 0 if the script failed.
Now we can create the reports of area, power, timing etc by using the command:
a) dc_shell>reporting_timing > sparctiming.rpt
b) dc_shell>reporting_area > sparcarea.rpt
c) dc_shell>reporting_power > sparcpower.rpt
You can exit Design Compiler at any time and return to the operating system.
However, dc_shell does not automatically save designs when you exit. Use the
write command to save your design before exiting dc_shell.
dc_shell> write -hierarchy -output my_design.db

Exiting Design Compiler

To exit dc_shell, do one of the following:
• Enter quit.
• Enter exit.
• Press Ctrl-d.
When you exit dc_shell, text similar to the following appears (the memory and
the CPU numbers reflect your actual usage):
Memory usage for this session 1373 Kbytes. CPU usage for this session 4
seconds.

14
Now we check all the reports which was created like area, power, timing and
every step by step process done by the design compiler which was stored in
sparc.log file, which we can open by using command “gvim”.

Output of DC compiler are

a) Optimized Design (Gate-Level Netlist)
b) Schematic
c) Reports (Timing, Area, Power, …, etc)

a) Optimized Design (Gate-Level Netlist)

➢ A netlist is a description of the connectivity of an electronic circuit. In its

simplest form, a netlist consists of a list of the electronic components in a
circuit and a list of the nodes they are connected to. It can be in the form
of Verilog or VHDL. This netlist is produced during logical synthesis,
which takes place prior to the physical design stage.
➢ The netlist out of the synthesis tool is then fed into layout tools to
produce the layout of the chip. During this process the netlist may be
modified but remains functionally equal to its corresponding HDL code.
➢ The netlist then written by the layout tool after the layout has been done
is often called post-layout-netlist.
➢ The noticeable difference between the pre-layout-netlist and post-layout-
netlist is the inclusion of 'clock tree buffers' in the post-layout-netlist.

b) Schematic
A schematic, or schematic diagram, is a representation of the elements of a
system using abstract, graphic symbols rather than realistic pictures. A schematic
usually omits all details that are not relevant to the information the schematic is
intended to convey, and may add unrealistic elements that aid comprehension.
c) Reports (Timing, Area, Power, …, etc)
Area: With shrinking system size ASIC should be able to accommodate
maximum functionality in minimum area. Designer can specify area constraint
and synthesis tool will optimize for minimum area. Area can be optimized by

15
having lesser number of cells and by replacing multiple cells with single cell that
includes both functionality.
Area report:

Timing: Designer specifies maximum delay between primary input and primary
output. This is taken as maximum delay across any critical path. There are three
types of critical paths:
1 Path between a primary input and primary output.
2 Path from any primary input to a register.
3 Path from a register to a primary output.
4 Path from a register to another register.

Timing report:
Make sure the timing report requirements are MET. You can observe which
module in the design is giving the maximum delay and optimize accordingly.

16
17
Power: Development of hand-held devices has led to reduction of battery size
and hence low power consuming systems. Low power consumption has become
a big requirement for lot of designers.

18
Power report:
Design Compiler gives the detailed information about the static and dynamic
power.

19
Synthesis Verification
The first step is to verify a set of reports, which have information about
timing, area, fanout and shows the violations to the defined constraints.
These reports must be interpreted to check if there are violations (setup
time, hold times, area, max transition, etc.).
In case of violations DC can try to fix them by running optimization
algorithms. If DC cannot fix the violations, one must go back to RTL coding.
With these reports it is possible to check if the design is synthesizable and,
therefore, if it is possible to proceed.

20