Innovus Mixed Signal Implementation

Update Training
May 2015
What if there were no OpenAccess (OA)?
AOT(Analog on Top) DOT (Digital on Top)
Virtuoso Innovus
Digital Custom

Mixed Signal
designers
could do Innovus Virtuoso
either file
based AOT
or DOT
MSOT (Mixed signal on top)
Innovus Virtuoso

D A D A D A D A

D
But not D

MSOT D
A A
D
A A

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What does MSOT enable?
• Extending of digital design automation techniques to Mixed
Signal design implementation
• Implementation of large scale MS designs
– File interface, not efficient
– Lib/Cell/View structure allows seamless exchange of a cell view and
easier version control
– Ability to push and pop
• Working on the entire design, in both platforms
– EDI’s automatic abstract generation improves productivity, as you do not
have to generate abstracts for layout views that are in progress.
– Enables many new capabilities
– Early timing/power analysis of MS designs implemented in Virtuoso,
Ability to do timing and power sign-off on a MS design
– Improved usability, that is, easier implementation and better debugging
capability
– Constraint-driven design methodology
– Reduces risk for design errors leading to tapeout delays

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Mixed Signal Static Timing Analysis (MS STA)
enhancement
Automatic identification of digital logic for analysis
Digital P&R logic two levels down
• Exposing the digital logic to
the top level for MS STA,
requires detailed knowledge of
the design
• Innovus will auto detect the
presence of digital logic in the
physical hierarchy.
– You no longer have to direct the
tool, for exposing the logic paths Custom digital logic five levels
that require STA. down the physical hierarchy
Hand placed std. cells five levels
down the physical hierarchy

Today’s MS Designs

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assembleDesign Syntax

assembleDesign -allTimingBlocks –except_blocks -blockCell

• Enables automatic detection and assembly of blocks with digital

content.

• The -blockCell option can be used to manually force blocks to be

assembled

• -except_blocks option can be used to exclude cells from being

assembled because it overrides to the default list of blocks to be

assembled.
Note: only –blockCell and –except_blocks work with –allTimingBlocks.

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assembleDesign –allTimingBlocks

• Use model
– Works only for incremental mode.

For example,
source scripts/LP_pll.globals
init_design
assembleDesign -allTimingBlocks

– Not in batch mode

For example,
assembleDesign -topDesign {zambezi45 LP_pll
layout_init} -allTimingblocks

**ERROR: (ENCSYT-35004): Cannot run assembleDesign with

-allTimingBlocks option because design is not loaded. -
allTimingBlocks option is supported in incremental
assembleDesign only. Load the design and then run
assembleDesign.

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Mixed Signal Static Timing Analysis
Made easy for Virtuoso users

• Automatic identification of Digital logic in the design

• Automatic exposure of digital timing paths to the timer
• Interface directly in Virtuoso
• Sign-off level analysis
through Tempus

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Enhancements to oaIn -filter
• EDI supported a flow where the top level
owner in Virtuoso could change the Virtuoso
PrBoundary or the pin locations of the Digital
digital block.
• Can bring the new data into EDI without
invalidating the connectivity
• In 15.1, you will be able to selectively
import the following design objects from

OA
a different version of the cellview
• Macro placement
• Power routing Innovus
• Power domains
• Pre-routes

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Enhancements to oaIn -filter
• When to use oaIn versus oaIn -filter.
 Case 1: To read updated placement, routing, and so on, with no changes to
the netlist.
 Example: Sending a placed database to another tool to do routing and then
reading back the results

 Use oaIn without -filter. Error checking is performed to make sure

that you are reading from the correct database.

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Enhancements to oaIn -filter
• When to use oaIn versus oaIn -filter.

 Case 2: To read floorplanning information from a cellview whose

connectivity does not match the current Innovus in-memory connectivity.

 Use oaIn with -filter. The -filter option allows youto selectively load some
data, while not loading others. When -filter is used, error checking for
database consistency (nets, instances, terminals, and so on) is disabled.

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Enhancements to oaIn -filter
• When to use oaIn, oaIn -filter, and ecoOaDesign. Usage
cases:
 Case 3: To read a new netlist and as much of the original cellview's
information as possible. The flow where this applies is a timing eco or post-
mask eco. In those cases, the amount of change to the netlist is typically
small and the goal is to disturb as little of the original information as
possible for timing closure or "frozen-metal" eco purposes.
o Use ecoOaDesign

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Enhancements to oaIn -filter
• Tcl Syntax: (new items in bold)
oaIn <lib> <cell> <view> [-filter {blockages block_insts boundary
fixed_core_insts floorplan pad_insts pin_shapes regions regular_routing
special_routing}] [-nets <net_names>]

Argument Description
blockages Indicates that blockages should be processed. If a blockage is attached to an instance that
does not exist in the in-memory database, then it is ignored.
block_insts Indicates that any CLASS PAD instances should be updated. Physical only block instances
may be added to the database if placement status is "fixed/cover".
boundary Indicates that design boundary information should be updated (includes rows, tracks)
fixed_core_insts Indicates that any CLASS CORE instances that have placement status "fixed/cover" should
be updated. Physical only core instances may be added to the database if placement status
is "fixed/cover".
floorplan Equivalent to "blockages block_insts boundary fixed_core_insts pad_insts pin_shapes
regions special_routing"
pad_insts Indicates that any CLASS PAD instances should be updated. Physical only pad instances
may be added to the database if placement status is "fixed/cover".
pin_shapes Indicates that pin shapes should be read.
regions Indicates regions should be updated
regular_routing Indicates that nets should be processed and regular routing (and associated shield net
wiring) and net constraints updated
special_routing Indicates that nets should be processed and special routing (except shield nets wiring)
should be read

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oaDbChecker – The OA gate keeper
To check the data being exchanged between various teams

• Often, data being

exchanged between analog Analog Digital & SoC
Interoperability
Design team Design team
and digital teams creates
challenges for the team
receiving the data.
– No PRBoundary, Layout not xl
compliant, Objects for which
connectivity cannot be
extracted, among other issues
• oaDbChecker is the gate
keeper for data being
exchanged in the Foundry Enablement
interoperable environment. OpenAccess DB
– Custom data is run through the Common techfiles
DB checker prior to being
passed to the digital team.

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What is oaDBChecker?

• It is a SKILL-based utility that can be run in the Virtuoso

environment
• Ensures that the OpenAccess database when brought
inside EDI System is compatible for place-and-route flow.
• Ensures that the OpenAccess database contains all the
necessary database objects that are required by
applications within Innovus System.

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Where to find the oaDBChecker SKILL scripts?

• You can run OA DB checker by loading

the oaDBChecker.il SKILL file located at:

base_dir/release_number/lnx86/tools.lnx86/fe/gift/AoT/OACh
ecker/oaDBChecker.il
where, base_dir specifies the Innovus installation path
and release_number specifies the Innovus System version number.

• To start OA DB Checker, type the following in CIW:

1. Load
"base_dir/release_number/lnx86/tools.lnx86/fe/gift/AoT/OAChecker/oaDBC
hecker.il“
2. oaDBChecker should be available in the CIW->Tools->menu

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oaDBChecker GUI

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Technology Pipeline (MS implementation)
interoperability improvements - Problem statement
• In Mixed Signal designs, very often the top-level designer is
in a different organization that some of the block designers

• Blocks are over-constrained by the top level making them

difficult to implement by the block designers.
• Block designers make changes during implementation
that makes previous top-level analysis invalid.

• The number of blocks and pins per blocks is increasing in

custom designs.

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DOT flow
Passing pinGroupGuides to Virtuoso

• Innovus runs timing driven

Placement Innovus
• Assigns pin constraints to the
AMS block.
• Innovus will generate an abstract

D
ANA
for the AMS block with an initial Virtuoso
pin assignment by Innovus (or

ANA

ANA
manual) (Pin spacing,
layer, side etc)
(Pin spacing,
layer, side etc)

D
• LPV in Virtuoso is used to import AMS AMS

the pins. prBoundary and the

constraints from the OA abstract
OA
into the layout.
• While implementing the block, a
Virtuoso user is aware of what
pins can/cannot be modified and
what modifications are allowed.

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AOT flow
Extending EDI’s pin placement/optimization capabilities
Legend

• Virtuoso designers can pre- unassigned pins by Virtuoso

Pre-assigned pins by Virtuoso
place pins, and mark them Pin get assigned by EDI

fixed. Virtuoso Innovus

(pin assignment & optimization)
• Can also create interoperable
pinGroupGuides in Virtuoso to
be used by Encounter for pin

D
ANALOG

manipulation.

A
• PinGroupGuides define such
things as: Pin grouping, pin

A
Pin constraints Pin get assigned
based on
location, pin spacing, layer, (side, layer etc) for
unassigned pins constraints passed

D
through OA view
side, order, and exclusivity. DIGITAL DIGITAL

• If routing constraints exist, Pre-assigned pins Pre-assigned pins

Innovus will use routing

constraints to define the OA
pinWidth.

• Innovus will place the created/optimized pin in an abstract.

• Virtuoso will use LPV to compare the pinConstraints between the original
block, and the abstract sent back by EDI. Once compared, LPV is used to
transfer the pins to the original block.
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assembleDesign -allTimingBlocks
For each cellview, Innovus checks the following condition:
1) If there is a standard cell (with CORE celltype) exists in the cellview.
2) If there is a cell in the cellview that is bound with timing library.
3) If any of the cellview below its current level has met any of the above two
condition.

Legend top
C2 is bound to timing
flatten A1 B1 C1
unflatten library
A2 B2 C2  C1 will be flattened
 C2 and C3 will not
A3a A3b B3 C3 be flattened
B4
Standard cell exist in A3a
=> A3a will be flattened,
=> A2 and A1 (cellviews
above A3a) will be Cell bound with timing
All the B* cells are not
flattened library exists in A3b
flattened, because no
 A3b will be flattened,
digital content found at
 A2 and A1 will be
any level.
flattened

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Full MS training material

• Mixed Signal RAK Page

– Click here
– If above does not work copy below link on any browser:
– https://support.cadence.com/apex/ArticleAttachmentPortal?
id=a1Od000000051ys

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