CD 74 HCT 164 M
CD 74 HCT 164 M
CD 74 HCT 164 M
(CD74
HC164
,
CD74
HCT16
4)
/Subject
(High
Speed
CMOS
Logic
8-Bit
SerialIn/Parallel-
CD54HC164, CD74HC164,
CD54HCT164, CD74HCT164
Data sheet acquired from Harris Semiconductor
SCHS155C
Features
Description
Buffered Inputs
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC164F3A
-55 to 125
14 Ld CERDIP
HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
CD54HCT164F3A
-55 to 125
14 Ld CERDIP
CD74HC164E
-55 to 125
14 Ld PDIP
CD74HC164M
-55 to 125
14 Ld SOIC
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1A at VOL, VOH
CD74HC164MT
-55 to 125
14 Ld SOIC
CD74HC164M96
-55 to 125
14 Ld SOIC
CD74HCT164E
-55 to 125
14 Ld PDIP
CD74HCT164M
-55 to 125
14 Ld SOIC
CD74HCT164MT
-55 to 125
14 Ld SOIC
CD74HCT164M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC164, CD54HCT164
(CERDIP)
CD74HC164, CD74HCT164
(PDIP, SOIC)
TOP VIEW
DS1 1
14 VCC
DS2 2
13 Q7
Q0 3
12 Q6
Q1 4
11 Q5
Q2 5
10 Q4
Q3 6
9 MR
GND 7
8 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
1
DS1
Q0
4
2
Q1
DS2
Q2
Q3
10
Q4
11
Q5
12
Q6
13
9
Q7
MR
GND = 7
VCC = 14
CP
TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
DS1
DS2
Q0
Q1 - Q7
RESET (CLEAR)
L-L
Shift
q0 - q6
q0 - q6
q0 - q6
q0 - q6
Thermal Information
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
VIL
25oC
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
1.5
1.5
1.5
4.5
3.15
3.15
3.15
4.2
4.2
4.2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
1.8
1.8
1.8
-0.02
1.9
1.9
1.9
-0.02
4.5
4.4
4.4
4.4
-0.02
5.9
5.9
5.9
-4
4.5
3.98
3.84
3.7
-5.2
5.48
5.34
5.2
HC TYPES
VOH
VIH or
VIL
VOL
VIH or
VIL
0.02
0.1
0.1
0.1
0.02
4.5
0.1
0.1
0.1
0.02
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.2
0.26
0.33
0.4
II
VCC or
GND
0.1
ICC
VCC or
GND
80
160
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
VIH
VIL
VOH
VIH or
VIL
PARAMETER
25oC
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
4.5 to
5.5
0.8
0.8
0.8
-0.02
4.5
4.4
4.4
4.4
-4
4.5
3.98
3.84
3.7
0.02
4.5
0.1
0.1
0.1
4.5
0.26
0.33
0.4
HCT TYPES
VOL
VIH or
VIL
VCC to
GND
5.5
0.1
ICC
VCC or
GND
5.5
80
160
ICC
(Note 2)
VCC
-2.1
4.5 to
5.5
100
360
450
490
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
UNIT LOADS
0.3
MR
0.9
Clock
0.7
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
fMAX
MHz
4.5
30
24
20
MHz
35
28
24
MHz
60
75
90
ns
4.5
12
15
18
ns
10
13
15
ns
HC TYPES
Maximum Clock Frequency
MR Pulse Width
tw
(Continued)
25oC
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tW
80
100
120
ns
4.5
16
20
24
ns
14
17
20
ns
60
75
90
ns
4.5
12
15
18
ns
10
13
15
ns
ns
4.5
ns
ns
80
100
120
ns
4.5
16
20
24
ns
14
17
20
ns
fMAX
4.5
27
22
18
MHz
tw
18
23
27
ns
CP Pulse Width
tw
4.5
18
23
27
ns
Set-up Time
tSU
12
15
18
ns
Hold Time
tH
4.5
ns
tREM
16
20
24
ns
PARAMETER
CP Pulse Width
Set-up Time
tSU
Hold Time
tH
MR to Clock,
Removal Time
tREM
HCT TYPES
Maximum Clock Frequency
MR Pulse Width
MR to Clock,
Removal Time
Switching Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
170
212
255
ns
4.5
34
43
51
ns
CL = 15pF
14
ns
CL = 50pF
29
36
43
ns
CL = 50pF
140
175
210
ns
4.5
28
35
42
ns
CL = 15pF
11
ns
CL = 50pF
24
30
36
ns
CL = 50pF
75
110
ns
4.5
15
22
ns
13
19
ns
HC TYPES
Propagation Delay,
CP to Qn
MR to Qn
tPLH, tPHL
tTLH, tTHL
fMAX
CL = 15pF
60
MHz
CIN
10
10
10
pF
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
TYP
MAX
MAX
MAX
UNITS
CPD
47
pF
CL = 50pF
4.5
36
45
54
ns
CL = 15pF
15
ns
CL = 50pF
4.5
38
46
57
ns
CL = 15pF
16
ns
CL = 50pF
4.5
15
19
22
ns
Power Dissipation
Capacitance
(Notes 3, 4)
HCT TYPES
Propagation Delay,
CP to Qn
tPLH, tPHL
MR to Qn
tPLH, tPHL
tTLH, tTHL
Input Capacitance
CIN
pF
fMAX
CL = 15pF
54
MHz
Power Dissipation
Capacitance
(Notes 3, 4)
CPD
49
10
10
10
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per device.
4. PD = VCC2 fi + (CL VCC2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
CLOCK
INPUT
trCL
tfCL
trCL
VCC
90%
GND
tH(H)
GND
tH(H)
VCC
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
tREM
VCC
SET, RESET
OR PRESET
1.3V
0.3V
tH(L)
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
10%
tfCL
CL
50pF
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-8970401CA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-8970401CA
CD54HCT164F3A
CD54HC164F
ACTIVE
CDIP
14
TBD
A42
-55 to 125
CD54HC164F
CD54HC164F3A
ACTIVE
CDIP
14
TBD
A42
-55 to 125
8416201CA
CD54HC164F3A
CD54HCT164F3A
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-8970401CA
CD54HCT164F3A
CD74HC164E
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
-55 to 125
CD74HC164E
CD74HC164EE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
-55 to 125
CD74HC164E
CD74HC164M
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC164M
CD74HC164M96
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC164M
CD74HC164M96G4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC164M
CD74HC164ME4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC164M
CD74HC164MG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC164M
CD74HC164MT
ACTIVE
SOIC
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC164M
CD74HCT164E
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
-55 to 125
CD74HCT164E
CD74HCT164EE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
-55 to 125
CD74HCT164E
CD74HCT164M
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT164M
CD74HCT164M96
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT164M
CD74HCT164M96E4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT164M
Addendum-Page 1
Samples
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
CD74HCT164M96G4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT164M
CD74HCT164MG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT164M
CD74HCT164MT
ACTIVE
SOIC
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT164M
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC164, CD54HCT164, CD74HC164, CD74HCT164 :
Addendum-Page 3
14-Jul-2012
Device
CD74HC164M96
SOIC
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HC164MT
SOIC
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HCT164M96
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HCT164MT
SOIC
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
14-Jul-2012
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC164M96
SOIC
14
2500
367.0
367.0
38.0
CD74HC164MT
SOIC
14
250
367.0
367.0
38.0
CD74HCT164M96
SOIC
14
2500
367.0
367.0
38.0
CD74HCT164MT
SOIC
14
250
367.0
367.0
38.0
Pack Materials-Page 2
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