C.I 74HC365
C.I 74HC365
C.I 74HC365
High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting
low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. The HC365 and HCT365 are non-inverting buffers, whereas the HC366 is an inverting buffer. These devices have two three-state control inputs (OE1 and OE2) which are NORed together to control all six gates. The HCT365 logic families are speed, function and pin compatible with the standard LS logic family.
Features
Buffered Inputs
[ /Title (CD74 HC365 , CD74 HCT36 5, CD74 HC366 , CD74 HCT36 6) /Subject (High Speed
High Current Bus Driver Outputs Typical Propagation Delay tPLH, tPHL = 8ns at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
Ordering Information
PART NUMBER CD54HC365F3A CD54HC366F3A CD54HCT365F3A CD74HC365E CD74HC365M CD74HC365MT CD74HC365M96 CD74HC366E CD74HC366M CD74HC366M96 CD74HCT365E CD74HCT365M CD74HCT365MT CD74HCT365M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The HC365, HCT365, and HC366 silicon gate CMOS threestate buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to
NOTE: When ordering, use the entire part number. The sufx 96 denotes tape and real. The sufx T denotes a small-quantity reel of 250.
Pinout
CD54HC365, CD54HCT365, CD54HC366 (CERDIP) CD74HC365, CD74HCT365, CD74HC366 (PDIP, SOIC) TOP VIEW
OE1 1 1A 2 (1Y) 1Y 3 2A 4 (2Y) 2Y 5 3A 6 (3Y) 3Y 7 GND 8 16 VCC 15 OE2 14 6A 13 6Y (6Y) 12 5A 11 5Y (5Y) 10 4A 9 4Y (4Y)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
HC366
OE1
16
VCC
OE1
16
VCC
1A
2 3
15 14
OE2 6A
1A
2 3
15 14
OE2 6A
1Y
1Y
2A
13
6Y
2A
13
6Y
2Y
5 6
12
5A
2Y
5 6
12
5A
3A 7
11 10
5Y
3A 7
11 10
5Y
3Y
4A 9
3Y
4A 9
GND
4Y
GND
4Y
NOTE: H = High Voltage Level L = Low Voltage Level X = Dont Care Z = High Impedance (OFF) State
(NOTE)
GND 8
1 OE1 4 15 OE2 6 3A 10 4A 12 5A 14 6A 7 3Y 9 4Y 11 5Y 2A 5 2Y
13 6Y
NOTE: Inverter not included in HC/HCT365. FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
3.84
3.7
0.02
4.5
0.1
0.1
0.1
4.5
0.26
0.33
0.4
0 0 -
100
0.1 8 360
1 80 450
1 160 490
A A A
IOZ
VIL or VIH
VO = VCC or GND
5.5
0.5
5.0
10
NOTE: Unit Load is ICC limit specied in DC Electrical Specications table, e.g., 360A max at 25oC.
Input tr, tf = 6ns 25oC VCC (V) 2 4.5 6 TYP MAX -40oC TO 85oC MAX -55oC TO 125oC MAX UNITS
SYMBOL
TEST CONDITIONS
tPLH, tPHL
CL = 50pF
105 21 18 -
130 26 22 -
160 32 27 -
ns ns ns ns
CL = 15pF
GND
tTHL
INVERTING OUTPUT
FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tr OUTPUT DISABLE 6ns tf 2.7 1.3 tPLZ OUTPUT LOW TO OFF tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 6ns 3V 0.3 tPZL GND
10% tPZH
1.3V
OUTPUT RL = 1k CL 50pF
VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT