CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541: High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541: High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541: High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State
(CD74
HC540
,
CD74
HCT54
0,
CD74
HC541
,
CD74
HCT54
CD54/74HC540, CD74HCT540,
CD54/74HC541, CD54/74HCT541
Data sheet acquired from Harris Semiconductor
SCHS189B
Features
Description
Ordering Information
TEMP. RANGE
(oC)
PART NUMBER
PACKAGE
CD54HC540F3A
-55 to 125
20 Ld CERDIP
CD54HC541F3A
-55 to 125
20 Ld CERDIP
CD54HCT541F3A
-55 to 125
20 Ld CERDIP
CD74HC540E
-55 to 125
20 Ld PDIP
CD74HC540M
-55 to 125
20 Ld SOIC
CD74HC540M96
-55 to 125
20 Ld SOIC
HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
CD74HC541E
-55 to 125
20 Ld PDIP
CD74HCT540E
-55 to 125
20 Ld PDIP
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1A at VOL, VOH
CD74HCT540M
-55 to 125
20 Ld SOIC
CD74HCT540M96
-55 to 125
20 Ld SOIC
CD74HCT541E
-55 to 125
20 Ld PDIP
CD74HC541M
-55 to 125
20 Ld SOIC
CD74HC541M96
-55 to 125
20 Ld SOIC
CD74HCT541M
-55 to 125
20 Ld SOIC
CD74HCT541M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
Pinouts
CD54HC540
(CERDIP)
CD74HC540, CD74HCT540
(PDIP, SOIC)
TOP VIEW
CD54HC541, CD54HCT541
(CERDIP)
CD74HC541, CD74HCT541
(PDIP, SOIC)
TOP VIEW
OE
20 VCC
OE1
A0
19 OE2
A0
19 OE2
A1
18 Y0
A1
18 Y0
A2
17 Y1
A2
17 Y1
A3
16 Y2
A3
16 Y2
A4
15 Y3
A4
15 Y3
A5
14 Y4
A5
14 Y4
A6
13 Y5
A6
13 Y5
A7
12 Y6
A7
12 Y6
GND 10
11 Y7
GND 10
11 Y7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
20 VCC
OEB
540
541
D0
Y0
Y0
D1
Y1
Y1
D2
Y2
Y2
D3
Y3
Y3
D4
Y4
Y4
D5
Y5
Y5
D6
Y6
Y6
D7
Y7
Y7
TRUTH TABLE
INPUTS
OUTPUTS
OE1
OE2
An
540
541
Thermal Information
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
VIH
VIL
VOH
PARAMETER
VCC
(V)
25oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
VIH or VIL
VOL
VIH or VIL
II
VCC or
GND
1.5
1.5
1.5
4.5
3.15
3.15
3.15
4.2
4.2
4.2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
1.8
1.8
1.8
-0.02
1.9
1.9
1.9
-0.02
4.5
4.4
4.4
4.4
-0.02
5.9
5.9
5.9
-6
4.5
3.98
3.84
3.7
-7.8
5.48
5.34
5.2
0.02
0.1
0.1
0.1
0.02
4.5
0.1
0.1
0.1
0.02
0.1
0.1
0.1
4.5
0.26
0.33
0.4
7.8
0.26
0.33
0.4
0.1
(Continued)
TEST
CONDITIONS
25oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
Quiescent Device
Current
ICC
VCC or
GND
80
160
IOZ
VIL or VIH
VO =
VCC or
GND
0.5
5.0
10
VIH
4.5 to
5.5
VIL
4.5 to
5.5
0.8
0.8
0.8
VOH
VIH or VIL
-0.02
4.5
4.4
4.4
4.4
-6
4.5
3.98
3.84
3.7
0.02
4.5
0.1
0.1
0.1
4.5
0.26
0.33
0.4
0.1
PARAMETER
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HCT TYPES
VOL
VIH or VIL
II
VCC and
GND
5.5
Quiescent Device
Current
ICC
VCC or
GND
5.5
80
160
IOZ
VIL or VIH
VO =
VCC or
GND
5.5
0.5
5.0
10
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
ICC
(Note 2)
VCC
-2.1
4.5 to
5.5
100
360
450
490
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT540
HCT541
A0 - A7
0.4
OE2
0.75
0.75
OE1
1.15
1.15
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
-40oC TO
85oC
25oC
-55oC TO
125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
110
140
165
ns
4.5
22
28
33
ns
CL = 15pF
ns
CL = 50pF
19
24
28
ns
CL = 50pF
115
145
175
ns
4.5
23
29
35
ns
CL = 15pF
ns
CL = 50pF
20
25
30
ns
CL = 50pF
160
200
240
ns
4.5
32
40
48
ns
CL = 15pF
13
ns
CL = 50pF
27
34
41
ns
CL = 50pF
160
200
240
ns
4.5
32
40
48
ns
CL = 15pF
14
ns
CL = 50pF
23
29
35
ns
CL = 50pF
60
75
90
ns
4.5
12
15
18
ns
10
13
15
ns
HC TYPES
Propagation Delay
Data to Outputs (540)
tPLZ, tPHZ
tPLZ, tPHZ
tPLZ, tPHZ
tTHL, tTLH
Input Capacitance
CI
CL = 50pF
10
10
10
10
pF
Three-State Output
Capacitance
CO
20
20
20
20
pF
CPD
CL = 15pF
50
pF
CPD
CL = 15pF
48
pF
CL = 50pF
4.5
24
30
36
ns
CL = 15pF
ns
CL = 50pF
4.5
28
35
42
ns
CL = 15pF
11
ns
CL = 50pF
4.5
35
44
53
ns
CL = 15pF
14
ns
tTLH, tTHL
CL = 50pF
4.5
12
15
18
ns
CI
CL = 50pF
10
10
10
10
pF
HCT TYPES
Propagation Delay
tPHL, tPLH
tPHL, tPLH
tPLZ, tPHZ
25oC
-55oC TO
125oC
SYMBOL
TEST
CONDITIONS
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
Three-State Output
Capacitance
CO
20
20
20
20
pF
CPD
CL = 15pF
55
pF
PARAMETER
NOTES:
3. CPD is used to determine the dynamic power consumption, per channel.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
tPHL
tr
VCC
90%
50%
10%
OUTPUT LOW
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
ENABLED
0.3
GND
1.3V
10%
OUTPUT HIGH
TO OFF
50%
3V
tPZL
tPHZ
tPZH
90%
6ns
2.7
1.3
tPLZ
10%
tPHZ
tf
GND
50%
OUTPUT HIGH
TO OFF
6ns
OUTPUT
DISABLE
tPZL
tPLZ
tPLH
6ns
OUTPUT LOW
TO OFF
1.3V
10%
INVERTING
OUTPUT
tTLH
90%
tPLH
tPHL
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
OUTPUT
DISABLE
tf = 6ns
tr = 6ns
VCC
90%
tPZH
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
(Continued)
IC WITH
THREESTATE
OUTPUT
OUTPUT
RL = 1k
CL
50pF
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT