1787AHC125 Quad Bus 3-State Output
1787AHC125 Quad Bus 3-State Output
1787AHC125 Quad Bus 3-State Output
JESD 17
12
11
10
1A
1Y
2OE
2A
2Y
14
1A
1OE
NC
VCC
4OE
VCC
1
2
13 4OE
12 4A
11 4Y
10 3OE
9 3A
6
7
1Y
NC
2OE
NC
2A
2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
2Y
GND
NC
3Y
3A
13
VCC
4OE
4A
4Y
3OE
3A
3Y
3Y
14
1OE
GND
1OE
1A
1Y
2OE
2A
2Y
GND
SN54AHCT125 . . . FK PACKAGE
(TOP VIEW)
SN54AHCT125 . . . J OR W PACKAGE
SN74AHCT125 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
NC No internal connection
description/ordering information
The AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
SN74AHCT125RGYR
HB125
PDIP N
Tube
SN74AHCT125N
SN74AHCT125N
Tube
SN74AHCT125D
SN74AHCT125DR
SOP NS
SN74AHCT125NSR
AHCT125
SSOP DB
SN74AHCT125DBR
HB125
Tube
SN74AHCT125PW
SN74AHCT125PWR
TVSOP DGV
SN74AHCT125DGVR
HB125
CDIP J
Tube
SNJ54AHCT125J
SNJ54AHCT125J
CFP W
Tube
SNJ54AHCT125W
SNJ54AHCT125W
LCCC FK
Tube
SNJ54AHCT125FK
SNJ54AHCT125FK
TSSOP PW
55C
55 C to 125
125C
C
TOP-SIDE
MARKING
QFN RGY
SOIC D
40C to 85C
ORDERABLE
PART NUMBER
PACKAGE
TA
AHCT125
HB125
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O DECEMBER 1995 REVISED JULY 2003
FUNCTION TABLE
(each buffer)
INPUTS
OE
OUTPUT
Y
2OE
2A
1Y
4
5
2Y
10
3OE
3A
3Y
13
4OE
4A
11
12
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
4Y
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O DECEMBER 1995 REVISED JULY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
SN74AHCT125
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
Supply voltage
VIH
VIL
VI
Input voltage
5.5
VO
Output voltage
VCC
IOH
IOL
t/v
TA
2
0.8
V
V
0.8
5.5
VCC
55
UNIT
V
mA
mA
20
20
ns/V
85
125
40
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O DECEMBER 1995 REVISED JULY 2003
TEST CONDITIONS
VCC
IOH = 50 mA
VOH
45V
4.5
IOH = 8 mA
IOL = 50 mA
VOL
TA = 25C
MIN
TYP
4.4
4.5
MIN
3.94
45V
4.5
IOL = 8 mA
SN54AHCT125
MAX
MAX
SN74AHCT125
MIN
4.4
4.4
3.8
3.8
MAX
UNIT
V
0.1
0.1
0.1
0.36
0.44
0.44
II
VI = 5.5 V or GND
0 V to 5.5 V
0.1
1*
mA
IOZ
VO = VCC or GND
5.5 V
0.25
2.5
2.5
mA
ICC
VI = VCC or GND,
IO = 0
5.5 V
20
20
mA
ICC
5.5 V
1.35
1.5
1.5
mA
Ci
VI = VCC or GND
5V
10
pF
Co
VO = VCC or GND
5V
15
10
pF
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
CL = 15 pF
OE
CL = 15 pF
OE
CL = 15 pF
CL = 50 pF
OE
CL = 50 pF
OE
CL = 50 pF
tsk(o)
TA = 25C
MIN
SN54AHCT125
SN74AHCT125
TYP
MAX
MIN
MAX
MIN
MAX
3.8**
5.5**
1**
6.5**
6.5
3.8**
5.5**
1**
6.5**
6.5
3.6**
5.1**
1**
6**
3.6**
5.1**
1**
6**
4.6**
6.8**
1**
8**
4.6**
6.8**
1**
8**
5.3
7.5
8.5
8.5
5.3
7.5
8.5
8.5
5.1
7.1
5.1
7.1
6.1
8.8
10
10
6.1
8.8
10
10
CL = 50 pF
1***
UNIT
ns
ns
ns
ns
ns
ns
ns
VOL(V)
VOH(V)
VIH(D)
VIL(D)
MIN
UNIT
0.8
0.8
4.4
V
0.8
MAX
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O DECEMBER 1995 REVISED JULY 2003
TEST CONDITIONS
No load,
TYP
f = 1 MHz
UNIT
14
pF
RL = 1 k
From Output
Under Test
Test
Point
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
In-Phase
Output
50% VCC
tPHL
Out-of-Phase
Output
50% VCC
VOL
3V
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
1.5 V
0V
tPZL
50% VCC
tPLZ
VCC
50% VCC
tPZH
tPLH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH 0.3 V
VOH
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
www.ti.com
6-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-9686901Q2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
59629686901Q2A
SNJ54AHCT
125FK
5962-9686901QCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9686901QC
A
SNJ54AHCT125J
5962-9686901QDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
5962-9686901QD
A
SNJ54AHCT125W
SN74AHCT125D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT125
SN74AHCT125DBLE
OBSOLETE
SSOP
DB
14
TBD
Call TI
Call TI
-40 to 85
SN74AHCT125DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
SN74AHCT125DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT125
SN74AHCT125DGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
SN74AHCT125DR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
AHCT125
SN74AHCT125DRE4
ACTIVE
SOIC
14
TBD
Call TI
Call TI
-40 to 125
SN74AHCT125DRG4
OBSOLETE
SOIC
14
TBD
Call TI
Call TI
-40 to 85
SN74AHCT125N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
-40 to 125
SN74AHCT125N
SN74AHCT125NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
-40 to 125
SN74AHCT125N
SN74AHCT125NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT125
SN74AHCT125NSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT125
SN74AHCT125PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
Addendum-Page 1
Samples
www.ti.com
Orderable Device
6-Aug-2014
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
SN74AHCT125PWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
SN74AHCT125PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
SN74AHCT125PWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
SN74AHCT125PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
SN74AHCT125PWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
SN74AHCT125PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB125
SN74AHCT125RGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HB125
SNJ54AHCT125FK
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
59629686901Q2A
SNJ54AHCT
125FK
SNJ54AHCT125J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9686901QC
A
SNJ54AHCT125J
SNJ54AHCT125W
ACTIVE
CFP
14
TBD
A42
-55 to 125
5962-9686901QD
A
SNJ54AHCT125W
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
Samples
www.ti.com
6-Aug-2014
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHCT125, SN74AHCT125 :
Catalog: SN74AHCT125
Automotive: SN74AHCT125-Q1, SN74AHCT125-Q1
Enhanced Product: SN74AHCT125-EP, SN74AHCT125-EP
Military: SN54AHCT125
NOTE: Qualified Version Definitions:
Addendum-Page 3
www.ti.com
6-Aug-2014
Addendum-Page 4
11-Oct-2013
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AHCT125DBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74AHCT125DGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74AHCT125DR
SOIC
14
2500
330.0
16.8
6.5
9.5
2.3
8.0
16.0
Q1
SN74AHCT125DR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHCT125DR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHCT125NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AHCT125PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHCT125RGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
11-Oct-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHCT125DBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74AHCT125DGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74AHCT125DR
SOIC
14
2500
364.0
364.0
27.0
SN74AHCT125DR
SOIC
14
2500
333.2
345.9
28.6
SN74AHCT125DR
SOIC
14
2500
367.0
367.0
38.0
SN74AHCT125NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74AHCT125PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74AHCT125RGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
08
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
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