Lab 03c: Study of CMOS Inverter

Objective
To study the properties of CMOS inverters as well as their characteristics and parameters by the
application of HSpice circuit simulation tool and hence provide an estimation of its values through
calculations.

Laboratory tasks
2.1. Characteristics of CMOS Inverter (INV) Circuit
• Build the circuit of CMOS inverter based on data of table 1 (Fig. 4.1):

IN Z
0 1
1 0

Bulks of NMOS transistors are connected to VSS

Bulks of PMOS transistors are connected to VDD

Fig. 4.1. Inverter symbol, electrical circuit, truth table and

input & output signal waveforms

• Get the circuit netlist (inv.netl file) and put it in the following link:
/student_lab/digital_ic/variant_val/...

• Input files necessary for simulation.

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For input files take:
• Input slope50 ps
• Output capacitive load value Cload: 5 fF

2.1.1. The input file for measuring the switching point voltage level for CMOS inverter in DC
mode by using HSpice circuit simulation tool is listed below:

*Inverter
*Threshold Voltage
* HSPICE Netlist
.options POST=1 parhier=local

* Models section
* Include models
.include '/student_lab/digital_ic/all_models/model_val'

* Design variables section

* Define parameters
.param vdd = VDD_val
.temp Temp_val

* Structural netlist section

.include '/student_lab/digital_ic/variant_val/inv.netl'

vvss vss gnd dc=0

vvdd vdd gnd dc='vdd'
vin in gnd dc=0
cload z gnd LOAD_val

* Analysis section
* DC Analyses
.dc vin 0 vdd 0.01
.probe v(*) i(*)

*Measures
.meas dc vthr_in_out find v(in) when v(in)=v(z) td=0.1

*Options
.option post probe
.option autostop

.end

2.1.2. The input file for measuring the delays for CMOS inverter and transition time in transition
mode by using HSpice circuit simulation tool is listed below:

*Inverter
*Propagation Delay, Transition Time
* HSPICE Netlist
.options POST=1 parhier=local

* Models section
* Include models
.include '/student_lab/digital_ic/all_models/model_val'

* Design variables section

* Define parameters
.param vdd = VDD_val
.param tr=TR_val
.param freq=FREQ_val

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.param per='1/freq'
.param tst='0.5*per'
.temp Temp_val

* Structural netlist section

.include '/student_lab/digital_ic/variant_val/inv.netl'

vvss vss gnd dc=0

vvdd vdd gnd dc='vdd'
vin in vss pulse vdd 0 ‘tst’ tr tr ‘0.5*per-tr’ per
cload z gnd LOAD_val

* Analysis section
* Transient Analyses
.tran ‘0.01*tr’ ‘2*per’
.probe v(*) i(*)

*Measures
***Propagation Delay
.meas tran tplh_in_ z trig v(in) val='0.5*vdd' fall=1 targ v(z) val='0.5*vdd' rise=1
.meas tran tphl_in_ z trig v(in) val='0.5*vdd' rise=1 targ v(z) val='0.5*vdd' fall=1
***Transition Time
.meas tran ttrlh_in_ z trig v(z) val='0.1* vdd ' rise=1 targ v(z) val='0.9* vdd ' rise=1
.meas tran ttrhl_in_ z trig v(z) val='0.9* vdd ' fall=1 targ v(z) val='0.1* vdd ' fall=1

*Options
.option post probe
.option autostop

.end

2.2. Draw the simulation circuit of ring oscillator to get inverter’s voltage transfer and transition
characteristics (Fig. 4.2).

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 Bulks of NMOS transistors are connected to VSS
Bulks of PMOS transistors are connected to VDD

Fig.4.2. Ring oscillator symbol, electrical circuit, and input and internal signal waveforms

• Get the netlist of the circuit (inv_ring.netl file). Build the circuit on the existing inverter
circuit, using the idea of subcircuit and put it in the following link:
/student_lab/digital_ic/variant_val/...

2.2.1. An example of ring oscillator consisting of three inverters

*.SUBCKT inv I ZN
MM1 VSS I ZN VSS NMOS L=0.09U W=0.2U
MM2 VDD I ZN VDD PMOS L=0.09U W=0.5U
*.ENDS inv

xu1 Z Z1 inv
xu2 Z1 Z2 inv
xu3 Z2 Z inv

• Input files necessary for simulation.

For input files take:

• Input slope 50 ps
• Output capacitive load value Cload=5 fF

2.2.2. The input file for measuring the delays for ring oscillator frequency in transition mode by
using HSpice circuit simulation tool is listed below:

*Inverter Chain
*Propagation Delay
* HSPICE Netlist
.options POST=1 parhier=local

* Models section
* Include models
.include '/student_lab/digital_ic/all_models/model_val'

* Design variables section

* Define parameters
.param vdd = VDD_val

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.param tr=TR_val
.param freq=FREQ_val
.param per='1/freq'
.param tst='0.5*per'
.param wwp=0.75u
.param wwn=0.35u
.param A=1
.temp Temp_val

* Structural netlist section

.include '/student_lab/digital_ic/variant_val/inv_chain.netl'

vvss vss gnd dc=0

vvdd vdd gnd dc='vdd'
vin in vss pulse vdd 0 ‘tst’ tr tr ‘0.5*per-tr’ per
cload z gnd 80f

* Analysis section
* Transient Analyses
.tran ‘0.01*tr’ ‘2*per’ sweep a 1 7 0.1
.probe v(*)

*Options
.option post probe
.option autostop
.end

2.3. Draw the Simulation Circuit of Inverter Chain to get Voltage Transfer Characteristics
(Fig. 4.3).

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 Bulks of NMOS transistors are connected to VSS
Bulks of PMOS transistors are connected to VDD

Fig. 4.3. The views of inverter chain’s symbol, electrical circuit, and
Input, output and internal signal waveforms

Table 1. Transistor sizes of inverter chain

Transistor W, (um) L, (um)
MP0 0.75 0.09
MN0 0.35 0.09
MP1 ‘0.75* A’ 0.09
MN1 ‘0.35 * A’ 0.09
MP2 ‘0.75 * A* A’ 0.09
MN2 ‘0.35 * A* A’ 0.09
MP3 ‘0.75 * A* A* A’ 0.09
MN3 ‘0.35 * A* A* A’ 0.09

• Get the netlist of the circuit (inv_chain.netl file) using the given sizes in table 4.1 and put it
in the following link:
/student_lab/digital_ic/variant_val/...

• Input files necessary for simulation.

For input files take:
• Input slope: 50 ps
• Output capacitive load value, Cload: 5Ff

2.3.1. The input file for measuring the minimum delays for inverter chain in transition mode by
using HSpice circuit simulation tool is listed below:

*Inverter Chain
*Propagation Delay
* HSPICE Netlist
.options POST=1 parhier=local

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 * Models section
* Include models
.include '/student_lab/digital_ic/all_models/model_val'

* Design variables section

* Define parameters
.param vdd = VDD_val
.param tr=TR_val
.param freq=FREQ_val
.param per='1/freq'
.param tst='0.5*per'
.param wwp=0.75u
.param wwn=0.35u
.param A=1
.temp Temp_val

* Structural netlist section

.include '/student_lab/digital_ic/variant_val/inv_chain.netl'

vvss vss gnd dc=0

vvdd vdd gnd dc='vdd'
vin in vss pulse vdd 0 ‘tst’ tr tr ‘0.5*per-tr’ per
cload z gnd 80f

* Analysis section
* Transient Analyses
.tran ‘0.01*tr’ ‘2*per’ sweep a 1 7 0.1
.probe v(*) i(*)

*Options
.option post probe
.option autostop

*Measures
***Propagation Delay
.meas tran tplh_in_ z trig v(in) val='0.5*vdd' rise=1 targ v(z) val='0.5*vdd' rise=1
.meas tran tphl_in_ z trig v(in) val='0.5*vdd' fall=1 targ v(z) val='0.5*vdd' fall=1
.meas tran tp_in_z param=’(tplh_in_z+tphl_in_z)/2’

.end

Steps to Perform the Exercise

Simulation of CMOS Inverter
• Assuming LOAD_val = 0, get voltage transfer characteristic by giving 0 to VDD_val
voltages to the input (Table 5, point 1).
• Assuming LOAD_val = 0, define the value of switching point voltage level (Fig. 4.1)
• Assuming LOAD_val = 0, get input and output signal waveforms, measure t pHL, tpLH
delays (Table 9, points 3, 4).
• Perform above step assuming LOAD_val = Cload

Simulation of Ring Oscillator

• Get the output signal waveform of the oscillator.
Measure:
a) Rise and fall times
b) Frequency

Simulation of Inverter Chain

• Get the value of A parameter in case of minimum delay

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Processing the Results Obtained in the Laboratory Exercise
Compare inverter’s switching point voltages, measured through simulation, with calculated
values.
• The following formula can be used:

β
+
 VDD − V 
n
V
9β THN  THP 
p
V =
SP β
n
1+
9β
p
Calculate the delays and compare them with the values when
a) LOAD_val = 0
b) LOAD_val = Cload/4

• The following formula can be used:

( )
t PLH = 0.7  R p  C outp + C outn + Cload ,

t PHL = 0.7  R n  (C outp + C outn + Cload )

where output capacitances (Coutp and Coutn ) and output resistances (Rp and Rn) are defined by the
following formula:
ε ε
C =C = ox  W  L and C =C = ox  W  L
outp oxp t p p outn oxn t n n
ox ox

VDD VDD
R = and R =
p kp W n kp W
p

p
 ( VDD − V )2
n  n  ( VDD − V )2
2 L THP 2 L THN
p n

where
ε ε
ox ox
kp =μ  and kp =μ 
p p t n n t
ox ox

Compare ring oscillator frequency measured through simulation with calculated values.
• The following formula can be used to calculate the frequency of ring oscillator:
1
f=
2 n  tP

where n is the number of inverters in ring oscillator,

tp is the average value of inverter’s delay calculated in 4.1.2. step above (t P=(tPLH+tPHL)/2)
when the capacitive load of the inverter equals Cload/4

In case of minimum delay, compare the value of A parameter measured through simulation with
calculated values.
• The following formula can be used:

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 −15 1
80  10 F 4
A =( ) ,
C
in
where
ε
ox
C = 3  0.75um  0.35um 
in t
ox

• Take the data necessary for calculations from Table 6.

• Fill in the results measured from simulation in Table 7.

Report
The report should contain:
1. Studied circuits;
2. Texts of input files;
3. Calculated characteristics and parameters of circuits;
4. Characteristics obtained from simulation;
5. Results obtained from the lab exercise;
6. Brief summary.

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