LAB-1

ARNAB DAS
2101043

OBJECTIVES:
Experiment 1) To plot the input characteristics of NMOS.
Experiment 2) To plot the output characteristics of NMOS.
Experiment 3) To plot the input characteristics of PMOS.

PROCEDURE:
1. Launch cadence:
 Launch the cadence application from the terminal with the following commands
csh -> source /home/install/cshrc -> virtuoso &

2. Design an NMOS/PMOS transistor:

 Load the NMOS schematic from the gpdk180 toolkit and add all the required DC
components.

3. Add DC analysis
 Go to ADE-L and add the DC analysis after selecting the appropriate component.
 Then with appropriate voltage values, run the system after save and check.
4. Do the parametric analysis
 Take the DC voltages as variables and run the parametric analysis to check the output
and input graphs for a given range of gate to source voltages.
5. Plot the graphs

 Plot the input and output characteristics graph for NMOS transistor and input
characteristics for PMOS transistor.
CIRCUIT DIAGRAM FOR THE STUDY OF NMOS CHARACTERISTICS

CIRCUIT DIAGRAM FOR THE STUDY OF PMOS CHARACTERISTICS

 RESULTS

1) INPUT CHARACTERISTIC GRAPH OF NMOS TRANSISTOR

2) OUTPUT CHARACTERISTIC GRAPH OF NMOS TRANSISTOR

3) INPUT CHARACTERISTIC GRAPH OF PMOS TRANSISTOR

DISCUSSION:
The threshold voltage holds significant importance as it represents the gate voltage where the NMOS
transistor initiates conduction. The analysis of input characteristics aids in determining this threshold
voltage (Vth). The saturation voltage (Vdsat) serves as a crucial indicator, denoting the drain voltage
at which the NMOS transistor enters saturation. By examining output characteristics, one can ascertain
this saturation voltage (Vdsat). Valuable insights have been gleaned from the investigation into the
input characteristics of a P-type Metal-Oxide-Semiconductor (PMOS) transistor via DC analysis. This
examination involves scrutinizing the correlation between gate voltage and drain current.
 LAB-2

OBJECTIVES:
Experiment 4) Plot the transfer characteristics of CS amplifier and maximize the low frequency
gain and determine the minimum value of dynamic range.

PROCEDURE:
1. Schematic Design:
- Launch Cadence Virtuoso Design Environment and create a new schematic cellview.
- Place the components required for the CS amplifier, including the FET transistor, biasing
resistors, coupling capacitors, and load resistor.
- Wire the components according to the CS amplifier topology.

2. DC Biasing Circuit:
- Design the DC biasing circuit to establish the proper DC operating point for the FET
transistor.
- Calculate biasing resistor values (RD, RS) and biasing voltage sources to set the
quiescent drain current (IDQ) and drain-source voltage (VDSQ) at the desired values.

3. Small-Signal Analysis:
- Perform small-signal analysis to determine the small-signal parameters of the CS
amplifier, such as voltage gain (Av), input impedance (Zin), and output impedance (Zout).
- Linearize the transistor model around the DC operating point and analyze the small-
signal equivalent circuit.
 CIRCUIT DIAGRAM OF CS AMPLIFIER

REULTS:

1) TRANSFER CHARACTERISTIC OF A CS AMPLIFIER

2) DETERMINING THE MINMUM VALUE OF DYNAMIC RANGE

3) MAXIMIZING THE LOW FREQUENCY GAIN BY TRANSIENT ANALYSIS

DISCUSSION:

Upon completion of simulating the CS amplifier circuit, one can generate transfer characteristics, illustrating the
correlation between the input voltage (Vin) and the output voltage (Vout). These characteristics typically
display nonlinear behaviour, particularly near the transition region where the FET operates in saturation. The
plot may uncover crucial parameters such as gain, linearity, and the operational region of the amplifier. The
low-frequency gain holds paramount importance for applications necessitating signal amplification with low-
frequency components. To optimize the low-frequency gain of the CS amplifier, it is imperative to fine-tune the
biasing conditions and adjust the load resistor value to ensure maximum voltage swing at the output for low-
frequency input signals. Modifying the biasing voltage, biasing resistor values, and load resistor value aids in
achieving higher low-frequency gain while maintaining stability and linearity. Nonetheless, it is crucial to ensure
that the amplifier operates within its linear operational range and does not introduce excessive distortion or
noise at low frequencies.
 LAB-3

OBJECTIVES:
Experiment 5) To plot the dc characteristics of a CMOS inverter and determine the time taken
for going from low to high and high to low.

PROCEDURE:
1. Schematic Design:
Launch Cadence Virtuoso Design Environment and create a new schematic cellview.
Place the NMOS and PMOS transistors to form the basic structure of the inverter.
Connect the transistors to form the complementary structure of the inverter, with the
drain of the NMOS transistor connected to the output node (Y) and the drain of the PMOS
transistor connected to the power supply (VDD).
Connect the gates of the NMOS and PMOS transistors together to form the input node (A).
Connect the sources of the transistors to the ground (GND).

2. DC Biasing Circuit:
Design the DC biasing circuit to establish the proper operating point for the NMOS and
PMOS transistors.

3. Transient analysis of CMOS inverter at the given values:

Delay time = 0 kp = 300 uA/v^2
Rise time = 1ps kn = 75 uA/v^2
Pulse width = 50 ns
Frequency = 1/10 Mhz
Stop time = 500 ns
 CIRCUIT DIAGRAM OF A CMOS INVERTER

RESULTS:

1) DC characteristics of a CMOS inverter

2) TRANSIENT ANALYSIS OF A CMOS INVERTER

DISCUSSION:
The DC transfer characteristics typically exhibit a sharp transition from high output voltage (VDD) to low
output voltage (GND) and vice versa, around the threshold voltage (Vth) of the transistors. The plot shows
two regions: the saturation region where the NMOS transistor is ON and the PMOS transistor is OFF, and
the cutoff region where the PMOS transistor is ON and the NMOS transistor is OFF. The transition region
between the saturation and cutoff regions represents the input voltage range where the inverter switches
its output state.
Propagation delay depends on various factors such as transistor sizing, load capacitance, parasitic
capacitances, and switching speed of the transistors. A shorter propagation delay indicates faster switching
speed and better performance of the CMOS inverter in digital applications.
 LAB-4

OBJECTIVE:
Experiment 6) Design NAND and NOR gate and find out the (W/L) ratio for both the cases. Also
verify truth table through the output pulse.

PROCEDURE:

1. Design of NAND Gate:

- Begin by selecting an appropriate configuration of P-MOS and N-MOS transistors for the
NAND gate.
- Implement the truth table for a NAND gate: the output is low (0) only when all inputs are
high (1).
- Design the NAND gate circuit using P-MOS and N-MOS transistors in a configuration that
satisfies the truth table.
- Calculate the size (W/L ratio) of each transistor in the NAND gate circuit.

2. Design of NOR Gate:

- Similarly, design a NOR gate using P-MOS and N-MOS transistors.
- Implement the truth table for a NOR gate: the output is high (1) only when all inputs are
low (0).
- Design the NOR gate circuit to meet the truth table requirements, ensuring proper logic
functionality.
- Calculate the size (W/L ratio) of each transistor in the NOR gate circuit.

3. Simulation and Verification:

- Set up simulations for both the NAND and NOR gate circuits in simulation software.
- Apply input signals corresponding to all possible combinations of inputs for the gates.
- Observe the output waveforms to verify that the gates produce the correct logic levels
according to their respective truth tables.
CIRCUIT DIAGRAM FOR NOR GATE

CIRCUIT DIAGRAM FOR NAND GATE

RESULTS:

1) OUTPUT WAVEFORM OF NAND GATE

2) OUTPUT WAVEFORM OF NOR GATE

 LAB-5

OBJECTIVES:
Experiment 7) Design NAND and NOR gates separately and then integrate them into a flip flop
circuit. Subsequently, perform transient analysis and generate a waveform with a 20% duty
cycle.

PROCEDURE:

1. Flip Flop Circuit Design:

- Design the NAND and NOR gates and then proceed to design the flip flop circuit.
- Select a flip flop type suitable for the desired application (e.g., D flip flop, JK flip flop).
- Use the previously designed NAND and NOR gates to construct the required logic for the flip
flop.
- Connect the inputs and outputs of the flip flop circuit appropriately.
- Ensure that the flip flop can toggle between states and store data effectively.

2. Transient Analysis:
- Set up the transient analysis parameters in the simulation software.
- Define the time duration for simulation and specify the time step.
- Apply appropriate input signals to trigger the flip flop and observe the output.
- Run the transient analysis simulation to analyse the behaviour of the flip flop circuit over
time.

3. Waveform Generation:
- Extract the output waveform from the simulation results.
- Analyse the waveform to ensure a 20% duty cycle.
- Verify that the flip flop transitions between states correctly and maintains the desired duty
cycle.
CIRCUIT DIAGRAM AND SYMBOL OF A NOT GATE

CIRCUIT DIAGRAM AND SYMBOL OF A NAND GATE

CIRCUIT DIAGRAM OF A D-FLIP FLOP

RESULTS:

1) WAVEFORM WITH 20% DUTY CYCLE

DISCUSSION:
This comprehensive procedure outlines the steps involved in designing NAND and NOR gates
separately and then integrating them into a flip flop circuit. It also includes transient analysis
and waveform generation to verify the functionality and performance of the flip flop circuit.
Adjustments can be made to fit the specific requirements and constraints of the experiment.
 LAB-6

OBJECTIVE:
Experiment 8) The objective of this experiment is to design a current mirror circuit that
maintains a specified relationship between the currents flowing through different P-MOS
transistors.

PROCEDURE:
1. Determine Transistor Sizes (W/L ratios):
- Begin by selecting appropriate W/L ratios for the P-MOS transistors to achieve the desired
current ratios.
- Calculate the W/L ratios based on the current mirror configuration and the desired current
values.
- Adjust the W/L ratios iteratively until the desired current ratios are achieved.

2. Circuit Design:
- Design the current mirror circuit using P-MOS transistors and N-MOS transistors.
- Connect the transistors in a configuration that ensures the desired current ratios are
maintained.
- Determine the appropriate biasing voltages (vin) for the N-MOS transistors to achieve the
desired current levels through the P-MOS transistors.
- Use appropriate resistor values, if necessary, to set the biasing voltages accurately.

3. Simulation and Analysis:

- Define the parameters such as transistor sizes (W/L ratios) and input voltages (vin).
- Run transient analysis simulations to observe the currents flowing through each P-MOS
transistor.
- Analyse the simulation results to ensure that the current ratios meet the specified
requirements.
CIRCUIT DIAGRAM AND RESULTS:

CIRCUIT DIAGRAM OF THE CURRENT MIRROR CIRCUIT

DISCUSSION:
The current flowing through the first P-MOS transistor should be I, the current flowing through
the second P-MOS transistor should be 2I, and the current flowing through the third P-MOS
transistor should be I. The parameters that can be adjusted in the circuit design are the width-
to-length ratios (W/L) of the transistors and the input voltages (vin) provided to the N-MOS
transistors.
Here we have got the values of voltages as 0.9v and the currents in the second and third PMOS
124.6 micro Ampere and 62.4 micro Ampere respectively which exactly meets the required
condition.