The Cmos Inverter: Slides Adapted From: N. Weste, D. Harris, CMOS VLSI Design,, 3/e, 2004

The CMOS
Inverter
Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design,
Addison-Wesley, 3/e, 2004
Outline
Robustness of CMOS Inverter The Static Behavior
Performance of CMOS Inverter Dynamic Behavior
Switching threshold
Noise Margins
Propagation delay
Power Dissipation
Static dissipation
Dynamic dissipation
2
Q&A
1.
2.
3.
4.
5.
6.
If the width of a transistor increases, the current will

increase
decrease
not change
If the length of a transistor increases, the current will
increase
decrease
not change
If the supply voltage of a chip increases, the maximum transistor current will
increase
decrease
not change
If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
If the length of a transistor decreases, its gate capacitance will
increase
decrease
not change
If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase
decrease
not change
3
Q&A
1.
2.
3.
4.
5.
6.
If the width of a transistor increases, the current will

increase
decrease
not change
If the length of a transistor increases, the current will
increase
decrease
not change
If the supply voltage of a chip increases, the maximum transistor current will
increase
decrease
not change
If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
If the length of a transistor increases, its gate capacitance will
increase
decrease
not change
If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase
decrease
not change
4
CMOS Inverter Static Behavior:

DC Analysis
CMOS Inverter: DC Analysis
DC Response: Vout vs. Vin for a gate
Inverter
When Vin = 0
Vout = VDD
When Vin = VDD
Vout = 0
In between, Vout depends on transistor current
By KCL, must settle such that

Idsn = |Idsp|
We can solve equations
Graphical solution gives very good insight
Transistors operation regions
Current depends on transistors operation region

For what Vin and Vout are nMOS and pMOS in
Cutoff ?
Linear ?
Saturation ?
nMOS and pMOS operation
Vgsn = Vin
Vgsp = Vin - VDD
Vdsn = Vout
Vdsp = Vout - VDD
Graphical derivation of the inverter DC

response: I-V Characteristics
Make pMOS wider than nMOS such that n = p
For simplicity lets assume Vtn=Vtp

response: current vs. Vout, Vin
Load Line Analysis:
For a given Vin:
Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal
10

response: Load Line Analysis
Vin = 0
Vin0
Idsn, |Idsp|
Vin0
Vout
VDD
11

Idsn, |Idsp|
Vin = 0.2 VDD
Vin1
Vin1
Vout
VDD
12

Vin = 0.4 VDD
Idsn, |Idsp|
Vin2
Vin2
Vout
VDD
13

Vin = 0.6 VDD
Idsn, |Idsp|
Vin3
Vin3
Vout
VDD
14

Vin = 0.8 VDD
Vin4
Idsn, |Idsp|
Vin4
Vout
VDD
15

Vin = VDD
Vin0
Idsn, |Idsp|
Vin5
Vin1
Vin2
Vin3
Vin4
Vout
VDD
16
DC Transfer Curve
Transcribe points onto Vin vs. Vout plot
17
DC transfer curve: operating regions
18
Beta Ratio
If p / n 1, switching point will move from VDD/2
Called skewed gate
19
Noise Margins
How much noise can a gate input see before it does not
recognize the input ?
20
Noise Margins
To maximize noise margins, select logic levels at unity gain

point of DC transfer characteristic
21
DC parameters
Input switching threshold: VTH

Minimum high output voltage: VOH
Maximum low output voltage: VOL
Minimum HIGH input voltage: VIH
Maximum LOW input voltage: VIL
22
CMOS Inverter Dynamic Behavior:

AC Analysis
DC analysis tells Vout if Vin is constant
AC analysis tells Vout(t) if Vin(t) changes
Requires solving differential equations
Input is usually considered to be a step
or ramp from 0 to VDD or vice versa
23
CMOS Inverter Dynamic Behavior:

AC Analysis
The switching characteristic (Vout(t) given Vin(t)) of a logic gate

tells the speed at which the gate can operate
The switching speed of a logic gate can be measured in terms of
the time required to charge and discharge a capacitive load
Critical paths
Timing Analyzers automatically finds the slowest paths in a logic
design
Critical paths can be affected at various levels:
Architecture/ Microarchitecture Level
Logic Level
Circuit Level
Layout level
24
Inverter Step Response
Find step response of inverter driving load cap
Vin (t ) u(t t0 )VDD
Vin(t)
Vout (t t0 ) VDD
Vout(t)
Cload
dVout (t )
I dsn (t )
dt
Cload
I dsn (t )
VDD V
Vin(t)
t t0
Idsn(t)
Vout VDD Vt
V (t )
VDD Vt out
Vout (t ) Vout VDD Vt
2
Vout(t)
t0
t
25
Delay Parameters
tr: rise time
tf: fall time
From input crossing VDD/2 to rising output crossing V DD/2
tpdf: falling propagation delay
From output crossing 0.8 VDD to 0.2 VDD
tpdr: rising propagation delay
From output crossing 0.2 VDD to 0.8 VDD
From input crossing VDD/2 to falling output crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2

26
Delay Parameters cont.
tr, tf
Tells how steep can be the waveform that the

logic gate is able to provide at its output
tpdr, tpdf
Input-to-output delay of the logic gate (time

needed for the output to respond to a change
in the input)
27
Factors affecting delay
CLOAD (= Cintrinsic + Cextrinsic)

intrinsic capacitance
(parasitic capacitance of the driving logic gate)
extrinsic capacitance
(interconnect capacitance + capacitance of the stage driven)
Slope of the input waveform

As the voltage on the gate terminal of a transistor change so
does its capacitance
28
Simulated Inverter Delay
Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write
It is important to develop back of the envelope techniques to rapidly
estimate delay, understand its origin, and figure out how it can be
reduced
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
t(s)
800p
1n
29
Delay Estimation
We would like to be able to easily estimate delay

Not as accurate as simulation
But easier to ask What if ?
The step response usually looks like a 1 st order RC response
with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
Depends on average current as gate switches
30
RC Delay Models
Use equivalent circuits for MOS transistors

Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
d
d
k
s
s
kC
R/k
g
kC
kC
s
d
k
s
kC
2R/k
kC
kC
d
31
Power Dissipation
Static CMOS gates are very power-efficient because

they dissipate nearly zero power while idle
Instantaneous power:
P i DD (t) VDD
T
Energy consumed:
E i DD VDD dt
0
Average power:
Pavg
1
i DD VDD dt
T0
32
Power Dissipation
Power dissipation in CMOS circuits comes from two

components:
Static Dissipation
Subtreshold conduction
Tunneling current
Leakage through reverse biased diodes
Dynamic Dissipation
Charging and discharging (switching) of the load capacitance
Short-Circuit current while both pMOS and nMOS networks are
partially ON
33
Static Dissipation
Pstatic VDD I leakage
OFF transistors still conduct a small amount of current :

Sub threshold current
Current through reverse biased diodes
gate tunneling current
In 130 nm processes and beyond leakage is becoming

a major design issue and vendors now provide leakage
data (often in the form of nA/m of gate length)
34
Dynamic Dissipation
T
Pdynamic
1
VDD
Psw Psc i DD (t) VDD dt
i DD (t)dt
T0
T 0
Assuming a logic gate goes through one complete charge/discharge cycle

every clock cycle:
2
Psw C VDD
f clock
Because most gates do not switch every clock cycle, we introduce a corrective
activity factor :
2
Psw C VDD
f clock
A clock has =1 because it rises and fall every cycle, but most data have a
maximum activity factor =0.5 because they transition only once every cycle
35
Dynamic Dissipation
Because, input rise/fall time is greater than zero, both

nMOS and pMOS will be ON for a short period of time
(while the input is between Vtn and VDD-|Vtp|)
This results in a short-circuit current pulse from VDD
to GND
Typically this increases power dissipation by about
10%
36
Low Power Design
Power Dissipation is a major problem !!!
37
Dynamic Power Reduction
Decrease activity factor
Decrease switching capacitance
Small transistors
Careful floor planning to reduce interconnect
Decrease power supply
Selective clock gating

Drawback: if the system transitions rapidly from an idle
mode to a fully active mode a large di/dt spike will
occur
Adjust voltage depending on the operating mode
Decrease operating frequency

38
Static Power Reduction
Subthreshold current can be reduced by increasing Vt
Selective application of multiple threshold

(low-Vt transistors on critical paths, high Vt transistors
on other paths)
Control Vt through the body voltage
39
Static Power Reduction cont.
Turn off the power supply entirely.

MTCMOS circuits use low Vt
transistors for computation and
high Vt transistor as a switch to
disconnect the power supply
during idle mode
The leakage through two series

OFF transistor is much lower (1020x) than that of a single
transistor (stack effect)
40

The Cmos Inverter: Slides Adapted From: N. Weste, D. Harris, CMOS VLSI Design,, 3/e, 2004

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The Cmos Inverter: Slides Adapted From: N. Weste, D. Harris, CMOS VLSI Design,, 3/e, 2004

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The CMOS

Robustness of CMOS Inverter The Static Behavior

Performance of CMOS Inverter Dynamic Behavior

If the width of a transistor increases, the current will

If the width of a transistor increases, the current will

CMOS Inverter Static Behavior:

CMOS Inverter: DC Analysis

DC Response: Vout vs. Vin for a gate

When Vin = VDD

In between, Vout depends on transistor current

By KCL, must settle such that

Transistors operation regions

Current depends on transistors operation region

nMOS and pMOS operation

Vgsp = Vin - VDD

Vdsp = Vout - VDD

Graphical derivation of the inverter DC

Make pMOS wider than nMOS such that n = p

For simplicity lets assume Vtn=Vtp

Graphical derivation of the inverter DC

Graphical derivation of the inverter DC

Graphical derivation of the inverter DC

Vin = 0.2 VDD

Graphical derivation of the inverter DC

Vin = 0.4 VDD

Graphical derivation of the inverter DC

Vin = 0.6 VDD

Graphical derivation of the inverter DC

Vin = 0.8 VDD

Graphical derivation of the inverter DC

Transcribe points onto Vin vs. Vout plot

DC transfer curve: operating regions

If p / n 1, switching point will move from VDD/2

Called skewed gate

To maximize noise margins, select logic levels at unity gain

Input switching threshold: VTH

CMOS Inverter Dynamic Behavior:

CMOS Inverter Dynamic Behavior:

The switching characteristic (Vout(t) given Vin(t)) of a logic gate

Inverter Step Response

Find step response of inverter driving load cap

Vin (t ) u(t t0 )VDD

tr: rise time

tf: fall time

From input crossing VDD/2 to rising output crossing V DD/2

tpdf: falling propagation delay

From output crossing 0.8 VDD to 0.2 VDD

tpdr: rising propagation delay

From output crossing 0.2 VDD to 0.8 VDD

From input crossing VDD/2 to falling output crossing VDD/2

tpd: average propagation delay

tpd = (tpdr + tpdf)/2

Delay Parameters cont.

Tells how steep can be the waveform that the

Input-to-output delay of the logic gate (time

Factors affecting delay

CLOAD (= Cintrinsic + Cextrinsic)

Slope of the input waveform