Exercise 3 - Vlsi

EED401-VLSI Technology and Design SPRING 2023
Exercise-3: CMOS INVERETER: (VTC and Noise Margin)
Objective:
I. To create a symbol for CMOS inverter circuit and instantiate symbol in a new test schematic
II. To study the VTC characteristics
a) Simulate the CMOS inverter using dc analysis and plot its functionality voltage transfer curve (VTC)
b) Design the CMOS inverter for symmetric voltage transfer curve (VTC) (Wp ↑es and Wn remains the
same) c) Verify the results/observations with theoretical analysis
III. To study the Noise Margin of the CMOS inverter
a) Calculate the Noise margin (NM) of the CMOS inverter
b) Comment on noise margin behavior by varying width of PMOS (WP) and supply voltage (VDD)
c) Verify results/observations with theoretical analysis for symmetric CMOS inverter.
Variables in schematic are

mentioned in Tables given below.
Fig.1: left to right:(a) Schematic of CMOS inverter cell with supply, ground, input, and output pins (b) CMOS
inverter Symbol after reshaping in the symbol editor. (c) Schematic of inverter Test with ‘vpulse’ as input source.
CMOS parameters:
Transistors P-MOS N-MOS
Design Variables in Schematic (cellview) Wp Lp Wn Ln
Initial values in ADE-L 1u 180n 1u 180n
-where W and L are the channel width and length of MOSFETs
I. Create a CMOS inverter symbol and instantiate it in a new schematic
a) CMOS symbol creation:
• Construct the CMOS unit cell circuit given in Fig. 1(a). (Execute Create → Pin) (choose pin direction
appropriately, supply (vdd) and ground (gnd) to be ‘InputOutput’)
• Create symbol and edit (delete and redraw if necessary) the symbol shape to triangle as shown in Fig. 1(b)
Note: Please go through Symbol Creation Section-I only of the Support Document provided to you.
• b) CMOS inverter test circuit:

i. Create new CellView with CellView name CMOS_inv_test and import symbol using Create → add Instance,
and complete the circuit in Fig. 1(c) by making proper connections with necessary voltage sources and output
pin.
ii. Assign the input and supply voltage sources with variables VDD and T in schematic view as given below:
input voltage (source type: vpulse) Voltage 1 Voltage 2 Period Rise Time Fall Time Pulse Width
Variables given in Schematic View 0 VDD T 0.1*T 0.1*T 0.5*T
Initial Values in ADE-L - 1.8 220n - - -
Supply voltage (source type: vdc)

DC Voltage (variable) VDD
Initial Values in ADE-L 1.8
II. Study the VTC Curve - DC Analysis

a) VTC (voltage transfer curve): In ADE – L, select dc analysis (similar to exercise -1) with dc-parameter of
Vin source to vary from 0-1.8 V, outputs to be plotted are the wires: Vout and Vin.
Note: DC analysis using Component parameter instead of Design variable for your reference Simulating
DC Analyses
This section demonstrates how to view and select the different types of analyses to complete the circuit when
running the simulation. You have to execute Analyses → Choose To set up for DC Analyses:
→ In the Analyses section, select dc

→ In the DC Analyses section, turn on Save DC Operating Point
→ Turn on the Component Parameter
→ Double click the Select Component, which takes you to the
schematic window
→ Select input signal voltage source(vpulse) in the test schematic
window
→ Select “DC Voltage” in the Select Component Parameter form
and click OK
→ In the analysis form type start and stop voltages as 0 to 1.8
respectively
→ Check the enable button and then click Apply
b) Design of CMOS inverter for symmetric VTC Curve: Using parametric analysis, select Wp as the parametric
variable, plot VTC curve for (10 values from 1u to 5u) and observe the symmetric VTC (for certain Wp
value,
Vout and Vin intersects at ~0.9V (VDD/2)); make comment on Wp/Wn ratio for the symmetric VTC
c) Verify the simulation results with the theoretical equations of both long channel and short channel models
(after theory lectures completion)
III. To study the Noise Margin behaviour through VTC characteristics

a) Calculate the Noise margin of CMOS invertor (dc analysis)
→ Create the derivative of Vout expression in the ADE-L output by following the steps given in support
document (section-II only).
→ After plotting derivative of Vout, use horizontal marker in the waveform window and set it at -1 value.
→ The horizontal line intersects the derivative curve at two distinct points, earlier point is VIL and later is VIH
Vil = 592.5mv
Vih=856.87mv
b) Verify the noise margin from theory (for long channel) [Ref: Kang book, pp. 179-181]
c) Comment on noise margin behaviour (Parametric dc analysis) by varying
i. Wp/Wn from 1μ/1μ to 5μ/1μ: 10 steps (keeping VDD=1.8V)
ii. VDD from 1.2V to 1.8 V: 6 steps (keeping Wp/Wn = 3μ/1μ)
d) Simulate the symmetric CMOS inverter VTC characteristics and retrieve the noise margin (NM) and verify
the results with theory [Kang book, pp. 185]

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EED401-VLSI Technology and Design SPRING 2023

Exercise-3: CMOS INVERETER: (VTC and Noise Margin)

Variables in schematic are

• b) CMOS inverter test circuit:

Supply voltage (source type: vdc)

II. Study the VTC Curve - DC Analysis

→ In the Analyses section, select dc

III. To study the Noise Margin behaviour through VTC characteristics

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