Opa1692 Posibil Used in A Module of Prism Sound ADA 128
Opa1692 Posibil Used in A Module of Prism Sound ADA 128
Opa1692 Posibil Used in A Module of Prism Sound ADA 128
OPA1692
SBOS566C – JUNE 2017 – REVISED OCTOBER 2018
Preamplifier for 3-Wire Electret Microphones THD + N vs Frequency (3 VRMS, 2-kΩ Load)
5V 5V 0.1 -60
Primo EM-173 0.1 F Competitor A
C1
Microphone R3 OPA1692
0.1 F
100 Competitor B
+
Microphone Output Competitor C
Cable R1 R2 C2 ± 0.01 -80
5.9 k 100 k 100 pF OPA1692
0.1 F
-5 V
0.001 -100
C3 R4 100 k
1 F
R5 1.1 k
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1692
SBOS566C – JUNE 2017 – REVISED OCTOBER 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.1 Application Information............................................ 20
2 Applications ........................................................... 1 8.2 Typical Application .................................................. 24
3 Description ............................................................. 1 8.3 Other Application Examples.................................... 27
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 29
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
6 Specifications......................................................... 4
10.2 Layout Example .................................................... 30
6.1 Absolute Maximum Ratings ...................................... 4
10.3 Power Dissipation ................................................. 30
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 31
6.4 Thermal Information: OPA1692 ................................ 4 11.1 Device Support...................................................... 31
6.5 Electrical Characteristics........................................... 5 11.2 Documentation Support ........................................ 32
6.6 Typical Characteristics .............................................. 7 11.3 Related Links ........................................................ 32
11.4 Receiving Notification of Documentation Updates 32
7 Detailed Description ............................................ 16
11.5 Community Resource............................................ 32
7.1 Overview ................................................................. 16
11.6 Trademarks ........................................................... 32
7.2 Functional Block Diagram ....................................... 16
11.7 Electrostatic Discharge Caution ............................ 32
7.3 Feature Description................................................. 16
11.8 Glossary ................................................................ 32
7.4 Device Functional Modes........................................ 19
8 Application and Implementation ........................ 20 12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Changed status of data sheet from Advance Information to Production Data ...................................................................... 1
OUT A 1 8 V+
±IN A 2 7 OUT B
+IN A 3 6 ±IN B
V± 4 5 +IN B
Not to scale
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 40
Voltage V
Input (V–) – 0.5 (V+) + 0.5
Input (all pins except power-supply pins) –10 10 mA
Current
Output short-circuit (2) Continuous Continuous
Operating, TA –55 125
Temperature Junction, TJ 200 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
30 30
25 25
20 20
Amplifiers (%)
Amplifiers (%)
15 15
10 10
5 5
0 0
-800
-720
-640
-560
-480
-400
-320
-240
-160
-80
0
80
160
240
320
400
480
560
640
720
800
-800
-720
-640
-560
-480
-400
-320
-240
-160
-80
0
80
160
240
320
400
480
560
640
720
800
Input Offset Voltage (PV) Input Offset Voltage Delta (PV)
N = 1160 Mean = –139.2 µV Std. Dev. = 105.4 µV N = 580 Mean = 17 µV Std. Dev. = 145.2 µV
Figure 1. Input Offset Voltage Distribution Figure 2. Input Offset Voltage Matching (Ch. A – Ch. B)
20 40
35
15 30
Amplifiers (%)
Amplifiers (%)
25
10 20
15
5 10
0 0
250
255
260
265
270
275
280
285
290
295
300
305
310
315
320
325
330
335
340
345
350
0.5
1.5
2.5
0
3
-2.5
-1.5
-0.5
-3
-2
-1
Figure 3. Offset Voltage Drift Distribution Figure 4. Input Bias Current Distribution
30 25
25
20
20
Amplifiers (%)
Amplifiers (%)
15
15
10
10
5
5
0 0
620
624
628
632
636
640
644
648
652
656
660
664
668
672
676
680
684
688
692
696
700
-10
0
1
2
3
4
5
6
7
8
9
10
-9
-8
-7
-6
-5
-4
-3
-2
-1
Figure 5. Input Offset Current Distribution Figure 6. Power Supply Current Distribution
90 120
Gain (dB)
10
Phase (q)
Gain (dB)
60 80
0
30 40
0 0 -10
-30 -40
-20
100m 1 10 100 1k 10k 100k 1M 10M
100 1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz)
Figure 7. Open-Loop Gain and Phase vs Frequency Figure 8. Closed-Loop Gain vs Frequency
160 100 10
PSRR Input Voltage Noise
100
80 10 1
60
40
20
0 1 0.1
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz) C001
Figure 9. CMRR and PSRR vs Frequency (Referred to Input) Figure 10. Input Voltage Noise Spectral Density
1000
Input Referred Voltage Noise (50 nV/div)
10
0.1
10 100 1k 10k 100k 1M Time (1 s/div)
Source Resistance (O) C001
14 100
12
10
8
10
6
4
2
0 1
10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) C001 Frequency (Hz) C001
Figure 13. Maximum Output Voltage vs Frequency Figure 14. Open-Loop Output Impedance vs Frequency
60 90
RISO = 0 :
50 80 RISO = 25 :
RISO = 50 :
40
70
Phase Margin (q)
Overshoot ( )
30
60
20
50
10
40
0
-10 30
-20 20
10 100 1000 20 100 1000 2000
Capacitive Load (pF) Capactiance (pF)
G=1 G=1 10-mV input step
Figure 15. Phase Margin vs Capacitive Load Figure 16. Overshoot vs Capacitive Load
60 -100
RISO = 0 : G=1
Total Harmonic Distortion Noise (dB)
55 RISO = 25 : G= 1
RISO = 50 :
50
-110
45
Overshoot ( )
40
-120
35
30
-130
25
20
15 -140
20 100 1000 2000 100 1k 10k
Capactiance (pF) Frequency (Hz)
G = –1 10-mV input step VOUT = 3 VRMS 80-kHz bandwidth
Figure 17. Overshoot vs Capacitive Load Figure 18. THD + N Ratio vs Frequency
-60
-120
-80
-130
-100
-140 -120
100 1k 10k 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
VOUT = 3 VRMS RL = 600 Ω 80-kHz bandwidth VOUT = 3 VRMS 500-kHz bandwidth
Figure 19. THD + N Ratio vs Frequency Figure 20. THD + N Ratio vs Frequency
-100 -100
HD2 HD2
HD3 HD3
HD4 HD4
Harmonic Distortion (dB)
-140 -140
-160 -160
-180 -180
100 1k 10k 100 1k 10k
Frequency (Hz) Frequency (Hz)
VOUT = 3 VRMS G=1 80-kHz bandwidth VOUT = 3 VRMS G = –1 80-kHz bandwidth
Figure 21. Distortion Harmonics vs Frequency Figure 22. Distortion Harmonics vs Frequency
-20 -20
G=1 G=1
Total Harmonic Distortion + Noise (dB)
G= 1 G= 1
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
1m 10m 100m 1 10 1m 10m 100m 1 10
Amplitude (VRMS) Amplitude (VRMS)
f = 1 kHz 80-kHz bandwidth f = 1 kHz RL = 600 Ω 80-kHz bandwidth
Figure 23. THD + N Ratio vs Output Amplitude Figure 24. THD + N Ratio vs Output Amplitude
Figure 25. Intermodulation Distortion vs Output Amplitude Figure 26. Channel Separation vs Frequency
0 0
-20 -20
-40 -40
-60 -60
Amplitude (dBc)
Amplitude (dBc)
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
-180 -180
0 5000 10000 15000 20000 0 50000 100000
Frequency (Hz) Frequency (Hz)
f = 1 kHz VO = 3 VRMS RL = 600 Ω f = 20 kHz VO = 3 VRMS RL = 600 Ω
Figure 27. 1-kHz Output Spectrum Figure 28. 20-kHz Output Spectrum
VIN VIN
VOUT VOUT
Voltage (5 mV/div)
Voltage (5 mV/div)
Figure 29. Small-Signal Step Response Figure 30. Small-Signal Step Response
Voltage (5 V/div)
Time (1 Ps/div) Time (1 Ps/div)
100-pF 100-pF
10-V input step G=1 10-V input step G = –1
capacitive load capacitive load
Figure 31. Large-Signal Step Response Figure 32. Large-Signal Step Response
1000
Rising
Falling 800
Input-referred Offset Voltage (PV)
600
Ouput Voltage (1 mV/div)
400
200
0
-200
-400
-600
-800
-1000
Time (1 Ps/div) -75 -50 -25 0 25 50 75 100 125 150
Temperature (qC)
5 typical units
Figure 33. Settling Time
Figure 34. Input Offset Voltage vs Temperature
-300 150
VS = r18 V
VS = r1.75 V 0.1
Input-referred Offset Voltage (PV)
140
-200
130
-100
120 1
0
110
100
100 10
200 90
300 80 100
-20 -15 -10 -5 0 5 10 15 20 -75 -50 -25 0 25 50 75 100 125 150
Input Common-mode Voltage (V) Temperature (qC)
5 typical units
Figure 35. Input Offset Voltage vs Common-Mode Voltage Figure 36. CMRR vs Temperature
170
120 1 150
140 0.1
110
130
100 10 120 1
-75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150
Temperature (qC) Temperature (qC)
300
10
250
0
200
-10
150
-20
100
50 -30
0 -40
-40 -20 0 20 40 60 80 100 120 140 -20 -15 -10 -5 0 5 10 15 20
Temperature(C) Input Common-mode Voltage (V)
Figure 39. Input Bias and Offset Current vs Temperature Figure 40. IB vs Common-Mode Voltage
10 1
0.9
Normalized Input Bias Current (nA)
0.8
Quiescent Current (mA)
5
0.7
0.6
0 0.5
0.4
0.3
-5
0.2
0.1 VS = r18 V
VS = r1.75 V
-10 0
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 -75 -50 -25 0 25 50 75 100 125 150
Input Common-mode Voltage (V) Temperature (qC)
VS = ±1.75 V
0.2
60 1k
0.1
40 10k
0 0.01 0.1 1
0 5 10 15 20 25 30 35 40 Output Voltage Swing from Rail (V)
Supply Voltage (V)
-5 85qC 60
125qC
50
-10 40
30
-15 20
10
-20 0
0 10 20 30 40 50 60 70 75 -75 -50 -25 0 25 50 75 100 125 150
Output Current (mA) Temperature (qC)
Sinking
Figure 47. Output Voltage vs Output Current Figure 48. Short-Circuit Current vs Temperature
Voltage (5 V/div)
VOUT
VIN
Figure 49. Negative Overload Recovery Figure 50. Positive Overload Recovery
VOUT
VIN
Voltage (5V/div)
7 Detailed Description
7.1 Overview
The OPA169x amplifiers are unity-gain stable, dual and quad op amps with low noise. The Functional Block
Diagram shows a simplified schematic of the OPA169x (one channel shown). The device consists of a very low
noise input stage with a folded cascode and a rail-to-rail output stage. A proprietary distortion reduction
technology allows the OPA169x family of amplifiers to achieve significantly lower distortion than other op amps
that consume the equal or greater power supply current.
V+
Pre-Driver and
Distortion
IN- IN+ Cancellation OUT
Competitor B
Competitor C
0.01 -80
OPA1692
0.001 -100
0.0001 -120
0.00001 -140
10 100 1k 10k
Frequency (Hz) C001
VOUT
VIN
Voltage (5V/div)
Figure 54. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
TVS
RF
+
±
+VS
R1 IN± 250 Ÿ
RS IN+ 250 Ÿ
+
Power-Supply
ID ESD Cell RL
+
VIN ±
+
±
±VS
TVS
Copyright © 2016, Texas Instruments Incorporated
Figure 55. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA169x but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see Figure 55), the ESD protection components are
intended to remain inactive and are not involved in the application-circuit operation. However, circumstances may
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
Figure 55 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10
0.1
10 100 1k 10k 100k 1M
Source Resistance (O) C001
R1 R2
'1 = l1 + p „ ¨:A5 ;2 + :A0 ;2 + kA41 æ42 o + :E0 „ 45 ;2 + lE0 „ d hp
41 „ 42 2
:1; > 84/5 ?
42 2
41 41 + 42
GND ±
:2; A5 = ¥4 „ G$ „ 6(-) „ 45 d h
EO 8
+ Thermal noise of RS
¾*V
RS
:3; A41 æ42 = ¨4 „ G$ „ 6(-) „ d h d h
41 „ 42 8
Thermal noise of R1 || R2
41 + 42 ¾*V
+
:4; G$ = 1.38065 „ 10F23 d h
VS ,
± Boltzmann Constant
-
Source
:5; 6(-) = 237.15 + 6(°%) >-? Temperature in kelvins
GND
(B) Noise in Inverting Gain Configuration Noise at the output is given as EO, where
R1 R2
:45 + 41 ; „ 42
'1 = l1 + p „ ¨:A0 ;2 + kA41 +45 æ42 o + FE0 „ H
2
:6; IG > 84/5 ?
42 2
45 + 41 45 + 41 + 42
RS ±
:45 + 41 ; „ 42
EO
:7; A41 +45 æ42 = ¨4 „ G$ „ 6(-) „ H I d h
+ 8
+
45 + 41 + 42 ¾*V Thermal noise of (R1 + RS) || R2
VS
d h
±
:8; G$ = 1.38065 „ 10F23
GND ,
Source Boltzmann Constant
-
GND :9; 6(-) = 237.15 + 6(°%) >-? Temperature in kelvins
(1) eN is the voltage noise of the amplifier. For the OPAx169x series of operational amplifiers, eN = 4.2 nV/√Hz at 1 kHz.
(2) iN is the current noise of the amplifier. For the OPA169x series of operational amplifiers, iN = 370 fA/√Hz at 1 kHz.
(3) For additional resources on noise calculations, see TI's Precision Labs Series.
100
EMIRR IN+ (dB)
80
60
40
20
10M 100M 1G 10G
Frequency (Hz)
Table 1 lists the EMIRR IN+ values for the OPA169x at particular frequencies commonly encountered in real-
world applications. Applications listed in Table 1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
+VS
±
50 Low-Pass Filter
+
RF source
-VS
DC Bias: 0 V Sample /
Modulation: None (CW) Averaging Digital Multimeter
Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF
supply decoupling
C3 R4 100 k
1 F
R5 1.1 k
R6 100
C4 6.8 nF
R1, C1, and R2 provide the correct termination impedance for the microphone and AC-couple the microphone
signal to the amplifier input. R2 is selected with a large value (100 kΩ) so that a smaller AC-coupling capacitor
can be used (C1). The high-pass corner frequency produced by C1 and R2 must be set to 20 Hz using
Equation 1:
1 1
20 Hz o C1 79.6 nF o 100 nF
2 ˜ S ˜ R2 ˜ C1 2 ˜ S ˜ 100 k: ˜ C1 (1)
R1 and R2 are in parallel for frequencies above 20 Hz. Therefore, select the value of R1 so that when in parallel
with R2, the combination results in a 5.6-kΩ resistance as specified in the microphone data sheet. Equation 2
calculates R1.
R1 ˜ R2 R1 ˜ 100 k:
5.6 k: o R1 5.9 k:
R1 R2 R1 100 k: (2)
R3 and C2 form a low-pass filter to prevent the amplification of electromagnetic interference (EMI) signals.
Equation 3 shows the corner frequency of this EMI filter.
1 1
f 3dB 15.9 MHz
2 ˜ S ˜ R3 ˜ C2 2 ˜ S ˜ 100 : ˜ 100 pF (3)
The input bias current of the OPA1692 through the 100-kΩ input resistor (R2) and can potentially cause a large
offset voltage to appear at the output of the amplifier. One solution to this problem is to match the DC resistance
of the circuit at each input of the amplifier. R4 and C3 accomplish this goal by providing a DC-feedback path for
the amplifier (R4) which has the same resistance as the input resistor (R2). Capacitor C3 serves two functions.
First, at low-frequencies this capacitor is effectively an open circuit and therefore the gain of the amplifier is 1,
which reduces DC offsets at the output. At high frequencies where the impedance of the capacitor is low, the
feedback network of R5, R6, and C4 determine the gain of the amplifier.
The nominal gain of the preamplifier circuit is calculated by considering the output of the microphone at the
maximum input SPL. For this design, a maximum input SPL of 120 dB or [20 pascals (Pa)] is specified. The
microphone sensitivity is shown as –37 dBV, measured at 1-Pa air pressure. The output signal of the microphone
at 20-Pa air pressure can be calculated by converting the –37 dBV sensitivity specification to mV per pascal of
air pressure as shown in Equation 4:
§ 37 dBV ·
¨ ¸
VOUT(MIC) 20 Pa u 10© 20 ¹ 282.5 mVRMS 399.5 mVp (4)
The linear output voltage range of the OPA1692 extends to within 200 mV of each power supply. Therefore, on a
±5-V power supply, the linear output voltage range is ±4.8 V. The linear output voltage range of the amplifier and
the maximum output signal level of the microphone determine the gain of the amplifier, as shown in Equation 5:
VOUT(OPA1692) 4.8 VP R5
G 12.015 (21.6 dB) 1
VOUT(MIC) 399.5 mVP R6 (5)
Selecting values of 1.1 kΩ and 100 Ω for R5 and R6, respectively, produce a nominal gain of 12 for the circuit,
allowing the full linear output swing of the amplifier to be used for the maximum input SPL. The feedback
capacitor (C4) limits the gain of the circuit at high frequencies beyond the range of human hearing. Equation 6
shows the high-pass corner frequency that capacitor C4 produces:
1 1
20 kHz o C4 7.23 nF o 6.8 nF
2 ˜ S ˜ R5 ˜ C4 2 ˜ S ˜ 1.1 k: ˜ C4 (6)
Lastly, by the low-frequency bandwidth requirement for the design and the gain determines the value of C3. The
high-pass corner frequency produced by this capacitor is affected by resistors R5 and R6 as shown in
Equation 7:
§ R5 · 1 1
C3 ¨1 ¸ 12 o C3 955 nF o 1 PF
© R6 ¹ 2 ˜ S ˜ R 4 ˜f 3dB 2 ˜ S ˜ 100 k: ˜ 20 Hz (7)
100
Gain (dB)
10
1
10 100 1k 10k 100k
Frequency (Hz) C001
Figure 61. Frequency Response of the Low-Noise Preamplifier for 3-Wire Electret Microphones
2.2 5V
Electret k 0.1 F
Microphone 0.1 F ½ OPA1692
100
+
Output
Microphone
47 100 ±
Cable
k pF
0.1 F
-5 V
47 k
2.2 F
150 3.57 k
2.2 nF
0.1 F
100 k
OPA171
+
VBIAS
±
100 k 1 F
10-k Potentiometer
(Logarithmic)
20
48 V Phantom Power 1k 1k 1k 1k
9V
9V
0.1 F
47 k
10 V
6.8 k 6.8 k D1 D2
47 F
± ±
47 F
Microphone Output
Input + + 68
68 30
100 VBIAS 47 k
pF 2.2 k OPA1692
2
100
1 pF
3 22 k
100 2.2 k
pF
68 30
Figure 63. Preamplifier for Professional Microphones Powered from a 9-V Battery
10 Layout
RF RF
(Schematic Representation)
OUTPUT A V+ GND
RF Output B
GND -IN A OUTPUT B
RG RF
VIN A +IN A -IN B GND
RG
V± +IN B VIN B
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.6 Trademarks
SoundPlus, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA1692ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OP1692
OPA1692IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1692
OPA1692IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1692
OPA1692IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OP1692
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
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of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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