Opa 4197
Opa 4197
Opa 4197
OPA625
Bridge Sensor
Reference Driver
OPA197 Gain Gain
+
4:2
HV MUX
Thermocouple
VIN REF
+ OPA197
P
OPA197 Gain + Antialiasing
Filter ADS8864
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA197, OPA2197, OPA4197
SBOS737C – JANUARY 2016 – REVISED MARCH 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 20
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 26
3 Description ............................................................. 1 8 Application and Implementation ........................ 27
4 Revision History..................................................... 2 8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5 9 Power Supply Recommendations...................... 30
6.1 Absolute Maximum Ratings ..................................... 5 10 Layout................................................................... 31
6.2 ESD Ratings.............................................................. 5 10.1 Layout Guidelines ................................................. 31
6.3 Recommended Operating Conditions....................... 5 10.2 Layout Example .................................................... 31
6.4 Thermal Information: OPA197 .................................. 6 11 Device and Documentation Support ................. 32
6.5 Thermal Information: OPA2197 ................................ 6 11.1 Device Support...................................................... 32
6.6 Thermal Information: OPA4197 ................................ 6 11.2 Documentation Support ........................................ 32
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 11.3 Related Links ........................................................ 32
V to 36 V) ................................................................... 7 11.4 Receiving Notification of Documentation Updates 33
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 11.5 Community Resources.......................................... 33
4.5 V to 8 V)............................................................... 9 11.6 Trademarks ........................................................... 33
6.9 Typical Characteristics ............................................ 11 11.7 Electrostatic Discharge Caution ............................ 33
7 Detailed Description ............................................ 19 11.8 Glossary ................................................................ 33
7.1 Overview ................................................................. 19 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 19 Information ........................................................... 33
4 Revision History
Changes from Revision B (October 2016) to Revision C Page
• Changed "Low Offset Voltage: ±250 µV (Maximum)" to "Low Offset Voltage: ±100 µV (Maximum)" ................................... 1
• Changed Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) Input offset voltage VS = ±18 V under
OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to +125°C" rows from same ...... 7
• Changed Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) Input offset voltage VCM = (V+) – 1.5 V
under OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to +125°C" rows
from same............................................................................................................................................................................... 7
• Changed Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) Input offset voltage VS = ±2.25 V, VCM
= (V+) – 3 V under OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to
+125°C" rows from same........................................................................................................................................................ 9
• Changed Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) Input offset voltage VS = ±3 V, VCM =
(V+) – 1.5 V under OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to
+125°C" rows from same........................................................................................................................................................ 9
• Changed "0" on Frequency (Hz) axis to "0.1" ..................................................................................................................... 11
• Changed "....to achieve a very low offset voltage of 250 µV (max)..." to "...to achieve a very low offset voltage of 100
µV (maximum)..." ................................................................................................................................................................. 19
• Added new row for PW package to Input bias current parameter ......................................................................................... 7
• Added new row for PW package to Input offset current parameter ...................................................................................... 7
• Added new footnote (1) to Open-loop gain parameter........................................................................................................... 7
• Changed Slew rate parameter from 20 V/µs : to 14 V/µs .................................................................................................... 10
NC 1 8 NC OUT A 1 8 V+
V- 4 5 NC V- 4 5 +IN B
V- 2 -IN A 2 13 -IN D
V+ 4 11 V-
+IN B 5 10 +IN C
-IN B 6 9 -IN C
OUT B 7 8 OUT C
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Dual supply ±20
Supply voltage, VS = (V+) – (V–) V
Single supply 40
Common-mode (V–) – 0.5 (V+) + 0.5
Voltage V
Signal input pins Differential (V+) – (V–) + 0.2
Current ±10 mA
Output short circuit (2) Continuous
Operating, TA –55 150
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For OPA2197, OPA4197: When driving high current loads on multiple channels, make sure the junction temperature does not exceed
125°C.
(2) For a detailed description of thermal protection, see the Thermal Protection section.
VS = ±2.25 V, 90 110
(V–) – 0.1 V < VCM < (V+) – 3 V TA = –40°C to +125°C 88 104
dB
Common-mode VS = ±2.25 V, 94 120
CMRR
rejection ratio (V+) – 1.5 V < VCM < (V+) TA = –40°C to +125°C 77 100
VS = ±2.25 V,
See Typical Characteristics
(V+) – 3 V < VCM < (V+) – 1.5 V
INPUT IMPEDANCE
ZID Differential 100 || 1.6 MΩ || pF
ZIC Common-mode 1 || 6.4 1013Ω || pF
OPEN-LOOP GAIN
VS = ±2.25 V, 104 126
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ TA = –40°C to +125°C 100 114
AOL Open-loop voltage gain dB
VS = ±2.25 V, 104 134
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ TA = –40°C to +125°C 100 120
(1) For a detailed description of thermal protection, see the Thermal Protection section.
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
500 35
30
400
Number of Amplifiers
25
Amplifiers (%)
300
20
15
200
10
100
5
0 0
-100 -80 -60 -40 -20 0 20 40 60 80 100 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60
Input Offset Voltage (PV) Input Offset Voltage (PV)
Figure 1. Offset Voltage Production Distribution at 25°C Figure 2. Offset Voltage Production Distribution at 125°C
35 15
30
12
25
Amplifiers (%)
Amplifiers (%)
9
20
15
6
10
3
5
0 0
-200 -150 -100 -50 0 50 100 150 200 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2
Input Offset Voltage (PV) Input Offset Voltage Drift (PV/qC)
Figure 3. Offset Voltage Production Distribution at –40°C Figure 4. Offset Voltage Drift Distribution
from –40°C to +125°C
150 75
100 50
Input Offset Voltage ( V)
50 25
0 0
±50 -25
±100 -50
±150
-75
±75 ±50 ±25 0 25 50 75 100 125 150 -20 -15 -10 -5 0 5 10 15 20
Temperature (ƒC) C001 Common-Mode Voltage (V)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100 200
75 150
Input Offset Voltage (PV)
25 50
0 0
-25 -50
-50 -100
-75 -150
-100 -200
13 14 15 16 17 18 19 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5
Common-Mode Voltage (V) Common-Mode Voltage (V)
Figure 7. Offset Voltage vs Common-Mode Voltage Figure 8. Offset Voltage vs Common-Mode Voltage
100 140 280
Open Loop Gain
75 120 Phase 240
Input Offset Voltage (PV)
50 100 200
Open Loop Gain (db)
25 80 160
Phase (q)
0 60 120
-25 40 80
-50
20 40
-75
0 0
-100
0 2 4 6 8 10 12 14 16 18 20 -20 -40
Power-Supply Voltage (V) 1 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
6 typical units
CLOAD = 15 pF
Figure 9. Offset Voltage vs Power Supply
Figure 10. Open-Loop Gain and Phase vs Frequency
60 1000
G = 100 V/V
G = +1 V/V 800
G = 10 V/V 600
Input Bias Current (pA)
40 G = -1 V/V
Closed Loop Gain (db)
400
200
20 0
±200
±400
0 ±600
±800
±1000
-20
±20.0 ±15.0 ±10.0 ±5.0 0.0 5.0 10.0 15.0 20.0
1k 10k 100k 1M 10M 50M
Frequency (Hz) VCM (V) C001
Figure 11. Closed-Loop Gain and Phase vs Frequency Figure 12. Input Bias Current vs Common-Mode Voltage
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
3000 (V-) + 5
IB-
IB+ +125°C
IOS (V-) + 4
2000 +85°C
Input Bias Current (pA)
(V-) + 1 25°C
0
(V-)
-1000 (V-) - 1
-75 -50 -25 0 25 50 75 100 125 0 10 20 30 40 50 60 70 80
Temperature (qC) Output Current (mA) C001
Figure 13. Input Bias Current vs Temperature Figure 14. Output Voltage Swing from Negative Power
Supply vs Output Current (Maximum Supply)
(V+) + 1 160.0
(V+) - 1
100.0
25°C
(V+) - 2 80.0
-40°C
+125°C 60.0
(V+) - 3
+PSRR
40.0
(V+) - 4 CMRR
+85°C 20.0
-PSRR
(V+) - 5 0.0
0 10 20 30 40 50 60 70 80 1 10 100 1k 10k 100k 1M
Output Current (mA) C001 Frequency (Hz) C012
Figure 15. Output Voltage Swing from Positive Power Figure 16. CMRR and PSRR vs Frequency
Supply vs Output Current (Maximum Supply)
10 1
Common-Mode Rejection Ratio (µV/V)
8 0.8
6 0.6
4 0.4
VS = ±2.25 V
2 0.2
0 0
±2 -0.2
VS = ±18 V
±4 -0.4
±6 -0.6
±8 -0.8
±10 -1
±75 ±50 ±25 0 25 50 75 100 125 150 ±75 ±50 ±25 0 25 50 75 100 125 150
Temperature (ƒC) C001 Temperature (ƒC) C001
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1000
VCM = 0 V (P-Channel)
500 VCM = V+ - 100 mV (N-Channel)
50
30
20
10
5
3
2
1
100m 1 10 100 1k 10k 100k
Time (1 s/div) Frequency (Hz)
Peak-to-peak noise = VRMS × 6.6 = 1.30 VPP
0.01
0.001
0.001
0.0001
0.0001
1E-5 1E-5
10 100 1k 10k 100k 0.01 0.1 1 10 20
Frequency (Hz) Output Amplitude (VRMS)
Figure 21. THD+N Ratio vs Frequency Figure 22. THD+N vs Output Amplitude
1.2 1.2
VS = r2.25 V
VS = r18 V
Quiescent Current (mA)
1.1 1.1
1 1
0.9 0.9
0.8 0.8
0 4 8 12 16 20 24 28 32 36 -50 -25 0 25 50 75 100 125
Supply Voltage (V) Temperature (qC)
Figure 23. Quiescent Current vs Supply Voltage Figure 24. Quiescent Current vs Temperature
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
3 10k
VS = r2.25 V
VS = r18 V
2
100
-1
-2
10
-3 0.1 1 10 100 1k 10k 100k 1M 10M
-50 -25 0 25 50 75 100 125 Frequency (Hz) C016
Temperature (qC)
30 35
Overshoot (%)
Overshoot (%)
25 30
20 25
15 20
10 15
5 10
0 5
20 30 40 50 70 100 200 300 500 700 1000 2000 20 30 40 50 70 100 200 300 500 700 1000 2000
Capacitive Load (pF) Capacitive Load (pF)
G = –1 V/V G = 1 V/V
Figure 27. Small-Signal Overshoot vs Capacitive Load Figure 28. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) (100-mV Output Step)
Output Output
Input Input
Voltage (5 V/div)
Voltage (5 V/div)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Output
Input
Figure 31. Negative Overload Recovery Figure 32. Small-Signal Step Response
Output (50 mV/Div)
G = –1 V/V G = 1 V/V
Figure 33. Small-Signal Step Response Figure 34. Large-Signal Step Response
4 4
Output Voltage Delta from Final Value (mV)
3 3
2 2
1 1
0 0
-1 -1
-2 -2
-3 -3
-4 -4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (Ps) Time (Ps)
G = 1, 0.01% settling = ±1 mV, step applied at t = 0 G = 1, 0.01% settling = ±500 µV, step applied at t = 0
Figure 35. Settling Time (10-V Positive Step) Figure 36. Settling Time (5-V Positive Step)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
Sinking current 30 Maximum output voltage without
VS = ±15 V
Sourcing current slew-rate induced distortion.
80 25
Short-Circuit Current (mA)
15
40 VS = ±5 V
10
VS = ±2.25 V
20 5
0 0
-75 -50 -25 0 25 50 75 100 125 150 10k 100k 1M 10M
Temperature (qC) Frequency (Hz) C033
Figure 37. Short-Circuit Current vs Temperature Figure 38. Maximum Output Voltage vs Frequency
Overdrive = 100 mV
Output Voltage (5 V/div)
C025 C026
Figure 39. Propagation Delay Rising Edge Figure 40. Propagation Delay Falling Edge
7 Detailed Description
7.1 Overview
The OPAx197 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 250 µV
(max) and low voltage offset drift of 0.75 µV/°C (maximum) over the full specified temperature range. This level
of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial
sensors, filters, and high-voltage data acquisition.
OPAx197
NCH Input
Stage
+IN
36-V High OUT
Slew Output
Differential Capacitive Load
Boost Stage
Front End Compensation
-IN
PCH Input
Stage
t
+IN +IN
OUT OUT
36 V OPAx197 ~0.7 V
-IN -IN
V V
OPAx197 Provides Full 36-V Conventional Input Protection
Differential Input Range Limits Differential Input Range
Figure 41. OPA197 Input Protection Does Not Limit Differential Input Capability
Ron_mux 1
Vn = +10 V RFILT +10 V Sn 1 2
D
+10 V ~±9.3 V
CFILT CS
CD
2 Vin±
Vn+1 = ±10 V RFILT ±10 V Sn+1 Ron_mux
~0.7 V
CFILT CS Idiode_transient Vout
Vin+
±10 V
100
Op amp with standard input diodes
Output Delta from Final Value (mV)
OPA197
50
-100
0 6 12 18 24 30 36 42 48 54 60
Time (Ps)
100.0
80.0
60.0
40.0
20.0
0.0
10M 100M 1G 10G
Frequency (Hz) C017
Output
Input
Voltage (5 V/div)
150°C
OPAx197
140ºC
Temperature
IOUT = 30 mA +
RL 3V
+ VIN 100 Ÿ ±
± 3V
45 50
RISO = 0 : RISO = 0 :
40 RISO = 25 : 45 RISO = 25 :
RISO = 50 : RISO = 50 :
35 40
30 35
Overshoot (%)
Overshoot (%)
25 30
20 25
15 20
10 15
5 10
0 5
20 30 40 50 70 100 200 300 500 700 1000 2000 20 30 40 50 70 100 200 300 500 700 1000 2000
Capacitive Load (pF) Capacitive Load (pF)
Figure 47. Small-Signal Overshoot vs Capacitive Load Figure 48. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step, G = –1 V/V) (100-mV Output Step, G = 1 V/V)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
(10-Ω to 20-Ω) resistor, RISO, in series with the output, as shown in Figure 49. This resistor significantly reduces
ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in
parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at
low output levels. A high capacitive load drive makes the OPA197 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 49 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin, and results using the OPA197 are summarized in Table 3. For additional information on techniques to
optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation,
and test results.
+Vs
Vout
Riso
+
+ Cload
Vin -Vs
±
Table 3. OPA197 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and
Measured Results
PARAMETER VALUE
Capacitive Load 100 pF 1000 pF 0.01 µF 0.1 µF 1 µF
Phase Margin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60°
RISO (Ω) 47.0 360.0 24.0 100.0 20.0 51.0 6.2 15.8 2.0 4.7
Measured
23.2 8.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21.0 8.6
Overshoot (%)
Calculated PM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2°
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using
an Isolation Resistor .
IS1
±IN
PCH1
FUSE BANK
TRIM TRIM V±
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx197 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode voltage range, as
shown in Figure 51.
P-Channel Transition N-Channel P-Channel Transition N-Channel
Region Region Region Region Region Region
200 200
100 100
Input Offset Voltage ( V)
0 0
±100 ±100
OPAx197
Input Offset Voltage vs Vcm
±200 ±200
Input Offset Voltage vs Vcm
without a precision trimmed Input
±300 ±300
±15.0 ±14.0 « 11.0 12.0 13.0 14.0 15.0 ±15.0 ±14.0 « 11.0 12.0 13.0 14.0 15.0
Common-Mode Voltage (V) Common-Mode Voltage (V)
RF
+
±
+VS
VDD
OPAx197
R1 100 Ÿ
IN±
±
RS IN+ 100 Ÿ
+
Power-Supply RL
ID + ESD Cell
±
VIN
VSS
+
±
±VS
TVS
Figure 52. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
1 2 3 4
Very Low Output Impedance High-Impedance Inputs Attenuate High-Voltage Input Signal Attenuate ADC Kickback Noise
Input-Filter Bandwidth No Differential Input Clamps Fast-Settling Time Requirements VREF Output: Value and Accuracy
Fast Settling-Time Requirements Stability of the Input Driver Low Temp and Long-Term Drift
Voltage
CH0+ RC Filter Buffer RC Filter
Reference
±20-V, +
10-kHz OPA197
Sine Wave Reference Driver
+
Gain Gain
CH0- OPA197
Network Network
OPA197 +
4:2
Mux
REFP
+ OPA140 VINP
Gain
CH3+ OPA197 + Antialiasing
+ Network SAR
±20-V, Filter
10-kHz OPA197 ADC
Sine Wave
+ VINM
CH3- CONV
Network
Gain
OPA197
n
16 Bits
High-Voltage Level Translation 400 kSPS
High-Voltage Multiplexed Input
VCM
Voltage
REF3240
Divider
OPA350
VCM Generation Circuit Shmidtt
Counter Delay
Trigger
n
Figure 53. OPA197 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage
Inputs With Lowest Distortion
1.5
1.0
0.5
–0.5
–1.0
–1.5
–2.0
–20 –15 –10 –5 0 5 10 15 20
ADC Differential Input (V)
Figure 54. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion.
VEE
VEE
R2
- 1.6 0Ÿ
OPA197 -
VIN
+ V+
+
OPA197 VOUT
+ V+
VCC RL
VCC 10 NŸ
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
RFx CF
10 NŸ 39 nF
RISO
± 37.4 Ÿ
OPA197 VOUT
+ V+
CL
10 µF
VREF VCC
2.5 V
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
VIN +
RG VOUT
RF
(Schematic Representation)
Place components
close to device and
Run the input traces to each other to
as far away from reduce parasitic
the supply lines errors VS+
as possible RF
NC NC
RG
GND ±IN V+ GND
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA197ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA197
OPA197IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12MV
OPA197IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12MV
OPA197IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12ST
OPA197IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12ST
OPA197IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA197
OPA2197ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2197
OPA2197IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 4HV
OPA2197IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 4HV
OPA2197IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2197
OPA4197ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA4197
OPA4197IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA4197
OPA4197IPW ACTIVE TSSOP PW 14 90 RoHS & Green SN Level-3-260C-168 HR -40 to 125 OPA4197
OPA4197IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 OPA4197
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214839/F 06/2021
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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