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LMH6702
SNOSA03H – NOVEMBER 2002 – REVISED MAY 2016

LMH6702 1.7-GHz Ultra-Low Distortion Wideband Op Amp

1 Features 3 Description
VS = ±5 V, TA = 25°C, AV = 2V/V, RL = 100 Ω,
1
The LMH6702 is a very wideband, DC-coupled
VOUT = 2 VPP, Typical Unless Noted: monolithic operational amplifier designed specifically
for wide dynamic range systems requiring exceptional
• 2nd and 3rd Harmonics (5 MHz, SOT-23) −100/−96 signal fidelity. Benefitting from current feedback
dBc architecture, the LMH6702 offers unity gain stability at
• −3-dB Bandwidth (VOUT = 0.5 VPP) 1.7 GHz exceptional speed without need for external
• Low Noise 1.83 nV/√Hz compensation.
• Fast Settling to 0.1% 13.4 ns With its 720-MHz bandwidth (AV = 2 V/V, VO = 2 VPP),
• Fast Slew Rate 3100 V/μs 10-bit distortion levels through 60-MHz (RL = 100 Ω),
1.83-nV/√Hz input referred noise and 12.5-mA supply
• Supply Current 12.5 mA current, the LMH6702 is the ideal driver or buffer for
• Output Current 80 mA high-speed flash A-D and D-A converters.
• Low Intermodulation Distortion (75 MHz) −67 dBc Wide dynamic range systems such as radar and
• Improved Replacement for CLC409 and CLC449 communication receivers that require a wideband
amplifier offering exceptional signal purity will find the
2 Applications low input referred noise and low harmonic and
intermodulation distortion of the LMH6702 an
• Flash A-D Driver attractive high speed solution.
• D-A Transimpedance Buffer
The LMH6702 is constructed using VIP10™
• Wide Dynamic Range IF Amp complimentary bipolar process and proven current
• Radar and Communication Receivers feedback architecture. The LMH6702 is available in
• Line Driver SOIC and SOT-23 packages.
• High Resolution Video Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 4.90 mm × 3.91 mm
LMH6702
SOT-23 (5) 2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Inverting Frequency Response
Harmonic Distortion vs Load and Frequency
1 -30
AV = -1 -40
GAIN
0 AV = -2 -80 -45
-50 HD2, RL = 1 k:
-1 -130
-55
PHASE
-2 -180 -60
Phase (°)
Gain (dB)

-65 HD2, RL = 100 :

HD (dBc)

-3 -230
-70
-4 AV = -4 -280 -75 HD3, RL = 100 :
-80
-5 -330 -85
AV = -10
-90
-6 -380
-95 HD3, RL = 1 k:
-7 -430 -100
1M 10M 100M 1G -105
Frequency (Hz) 1M 10M 100M
Frequency (Hz)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.3 Device Functional Modes........................................ 12
2 Applications ........................................................... 1 8 Application and Implementation ........................ 13
3 Description ............................................................. 1 8.1 Application Information............................................ 13
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 13
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 15
6 Specifications......................................................... 4 10 Layout................................................................... 15
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 15
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 16
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 17
6.4 Thermal Information .................................................. 4 11.1 Documentation Support ....................................... 17
6.5 Electrical Characteristics........................................... 5 11.2 Community Resources.......................................... 17
6.6 Typical Characteristics .............................................. 7 11.3 Trademarks ........................................................... 17
7 Detailed Description ............................................ 11 11.4 Electrostatic Discharge Caution ............................ 17
7.1 Overview ................................................................. 11 11.5 Glossary ................................................................ 17
7.2 Feature Description................................................. 11 12 Mechanical, Packaging, and Orderable
Information ........................................................... 17

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (October 2014) to Revision H Page

• Updated Thermal Information................................................................................................................................................. 4

• Changed non-inverting input bias (with no test conditions) current maximum value from ±15 µA to –15 µA........................ 6
• Changed non-inverting input bias (-40 ≤ TJ ≤ 85) current maximum value from ±21 µA to –21 µA ...................................... 6
• Added Community Resources section ................................................................................................................................. 17

Changes from Revision F (March 2013) to Revision G Page

• Added, updated, or renamed the following sections: Device Information; Specifications; Application and
Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
• Changed ±5 V to ±4 V in Recommended Operating Conditions............................................................................................ 4

Changes from Revision E (March 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

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5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23 D Package
Top View 8-Pin SOIC
Top View

1 5 + 1 8
OUT V N/C N/C

2 7 +
-IN - V
- 2
V

3 6
+ - +IN + OUT

3 4
+IN -IN
- 4 5
V N/C

NC: No internal connection

Pin Functions
PIN
NUMBER I/O DESCRIPTION
NAME
D DBV
-IN 2 4 I Inverting input voltage
+IN 3 3 I Non-inverting input voltage
N/C 1, 5, 8 – – No connection
OUT 6 1 O Output
V- 4 2 I Negative supply
V+ 7 5 I Positive supply

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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS ±6.75 V
(3)
IOUT See
Common mode input voltage V− to V+ V
Maximum junction temperature 150 °C
Storage temperature −65 150 °C
Infrared or convection (20 s) 235 °C
Soldering information
Wave soldering (10 s) 260 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum output current (IOUT) is determined by device power dissipation limitations.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Machine Model (MM), per JEDEC specification JESD22-C101, all pins (2) ±200

(1) Human body model: 1.5 kΩ in series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a
standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as
±2000 V may actually have higher performance.
(2) Machine model: 0 Ω in series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard
ESD control process. Manufacturing with less than 200-V MM is possible with the necessary precautions. Pins listed as ±200 V may
actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Operating temperature −40 85 °C
Nominal supply voltage ±4 ±6 V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.

6.4 Thermal Information

LMH6702
(1)
THERMAL METRIC DBV (SOT-23) D (SOIC) UNIT
5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 182 133 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 139 79 °C/W
RθJB Junction-to-board thermal resistance 40 73 °C/W
ψJT Junction-to-top characterization parameter 28 28 °C/W
ψJB Junction-to-board characterization parameter 40 73 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).

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6.5 Electrical Characteristics

at AV = 2, VS = ±5 V, RL = 100 Ω, RF = 237 Ω (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBWSM VOUT = 0.5 VPP 1700
SSBWLG VOUT = 2 VPP 720
-3-dB Bandwidth MHz
LSBWLG VOUT = 4 VPP 480
SSBWHG VOUT = 2 VPP, AV = +10 140
GF0.1dB 0.1-dB gain flatness VOUT = 2 VPP 120 MHz
LPD Linear phase deviation DC to 100 MHz 0.09 deg
RL =150 Ω, 3.58 MHz 0.024%
DG Differential gain
RL =150 Ω, 4.43 MHz 0.021%
RL = 150 Ω, 3.58 MHz 0.004
DP Differential phase deg
RL = 150 Ω, 4.43 MHz 0.007
TIME DOMAIN RESPONSE
2-V Step, TRS 0.87
tR Rise time ns
2-V Step, TRL 0.77
6-V Step, TRS 1.70
tF Fall time ns
6-V Step, TRL 1.70
OS Overshoot 2-V Step 0%
(4)
SR Slew rate 6 VPP, 40% to 60% 3100 V/µs
Ts Settling time to 0.1% 2-V Step 13.4 ns
DISTORTION AND NOISE RESPONSE
2 VPP, 5 MHz (5) (SOT-23) −100
HD2L dBc
2 VPP, 5 MHz (5) (SOIC) −87
2VPP, 20 MHz (5) (SOT-23) −79
HD2 2nd Harmonic distortion dBc
2VPP, 20 MHz (5) (SOIC) −72
2VPP, 60 MHz (5) (SOT-23) −63
HD2H dBc
2VPP, 60 MHz (5) (SOIC) −64
2VPP, 5 MHz (5) (SOT-23) −96
HD3L (5)
dBc
2VPP, 5 MHz (SOIC) −98
2VPP, 20 MHz (5) (SOT-23) −88
HD3 3rd Harmonic distortion dBc
2VPP, 20 MHz (5) (SOIC) −82
2VPP, 60 MHz (5) (SOT-23) −70
HD3H dBc
2VPP, 60 MHz (5) (SOIC) −65
OIM3 IMD 75 MHz, PO = 10dBm/ tone −67 dBc
VN Input referred voltage noise >1 MHz 1.83 nV/√Hz
Input referred inverting >1 MHz
IN 18.5 pA/√Hz
noise current
Input referred non-inverting >1 MHz
INN 3.0 pA/√Hz
noise current
SNF Total input noise floor >1 MHz −158 dBm1Hz
INV Total integrated input noise 1 MHz to 150 MHz 35 µV

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise specified.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Harmonic distortion is strongly influenced by package type (SOT-23 or SOIC). See Application Note section under Harmonic Distortion
for more information.

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Electrical Characteristics (continued)

at AV = 2, VS = ±5 V, RL = 100 Ω, RF = 237 Ω (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
STATIC, DC PERFORMANCE
±1.0 ±4.5
VIO Input offset voltage mV
-40 ≤ TJ ≤ 85 ±6.0
Input offset voltage average
DVIO See (6) −13 µV/°C
drift
−6 –15
IBN Input bias current Non-Inverting (7) µA
-40 ≤ TJ ≤ 85 –21
Input bias current average
DIBN Non-Inverting (6) +40 nA/°C
drift
−8 ±30
IBI Input bias current Inverting (7) µA
-40 ≤ TJ ≤ 85 ±34
Input bias current average
DIBI Inverting (6) −10 nA/°C
drift
47 52
PSRR Power supply rejection ratio DC dB
-40 ≤ TJ ≤ 85 45
Common mode rejection 45 48
CMRR DC dB
ration -40 ≤ TJ ≤ 85 44
11.0 12.5 16.1
ICC Supply current RL = ∞ mA
-40 ≤ TJ ≤ 85 10.0 17.5
MISCELLANEOUS PERFORMANCE
RIN Input resistance Non-Inverting 1.4 MΩ
CIN Input capacitance Non-Inverting 1.6 pF
ROUT Output resistance Closed Loop 30 mΩ
±3.3 ±3.5
VOL Output voltage range RL = 100 Ω V
-40 ≤ TJ ≤ 85 ±3.2
CMIR Input voltage range Common Mode ±1.9 ±2.2 V
IO Output current 50 80 mA

(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(7) Negative input current implies current flowing out of the device.

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6.6 Typical Characteristics

TA = 25°C, VS = ±5 V, RL = 100 Ω, Rf = 237 Ω (unless otherwise noted)

1 150 1 -30
GAIN AV = +1 AV = -1
GAIN
0 100 0 AV = -2 -80
AV = +2
-1 50 -1 -130
PHASE AV = +4
PHASE
-2 0 -2 -180

Phase (°)
Gain (dB)

Phase (°)
Gain (dB)
-3 -50 -3 -230
AV = +4
-4 -100 -4 AV = -4 -280
AV = +2
-5 -150 -5 -330
AV = +1 AV = -10
-6 -200 -6 -380
AV = +10
-7 -250 -7 -430
1M 10M 100M 1G 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
V0 = 2 Vpp RL = 100 Ω RF = 237 Ω VOUT = 2 VPP RF = 237 Ω RL = 100 Ω

Figure 1. Non-Inverting Frequency Response Figure 2. Inverting Frequency Response

1 1 150
GAIN GAIN 100 :
0 0 100
-1
-1 50
-2 PHASE
-2 50 : 0

Phase (°)
-3
Gain (dB)

Gain (dB)

PHASE
Phase (°)

-4 0 -3 -50
-5 -54
-4 1 k: -100
1 k:
-6 -108
-5 -150
-7 -162 100 :
-216 -6 -200
-8 50 :
-9 -270 -7 -250
10M 100M 1G 10G 0 200M 400M 600M 800M 1G
Frequency (Hz) Frequency (Hz)
VOUT = 0.5 VPP AV = 2 RF = 232 Ω AV = 2 VO = 2 VPP RF = 237 Ω

Figure 3. Small Signal Bandwidth Figure 4. Frequency Response for Various RLs, AV = 2
1 150 1.5
GAIN
0 100
1
-1 50
PHASE
1 k: 0.5 AV = +2
-2 0
Phase (°)

VOUT (V)
Gain (dB)

50 :
-3 -50 0

-4 -100
-0.5 AV = -2
50 :
-5 -150
-1
-6 -200

-7 100 :
-250 -1.5
0 100M 200M 300M 400M 500M 0 2 4 6 8 10 12 14
Frequency (Hz) Time (ns)
AV = 4 VO = 2 VPP RF = 237 Ω VO = 2 VPP RL = 100 Ω

Figure 5. Frequency Response for Various RLs, AV = 4 Figure 6. Step Response, 2 VPP

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Typical Characteristics (continued)

TA = 25°C, VS = ±5 V, RL = 100 Ω, Rf = 237 Ω (unless otherwise noted)
4 1

1 0.1

Settling Error (%)

VOUT (V)

-1
0.01
-2

-3

-4 0.001
0 10 20 30 40 50 60 1 10 100 1k
Time (ns) Time (ns)

AV = 2 VOUT = 6 VPP RL = 100 Ω RL = 100 Ω

Figure 7. Step Response, 6 VPP Figure 8. Percent Settling vs Time

-40 -40
-45
-50 HD2, RL = 1 k: -50
75 MHz
-55
-60
-60
-65 HD2, RL = 100 :
HD (dBc)

PS (dBc)
-70
-70
-75 HD3, RL = 100 :
-80
-80
-85 -90 50 MHz
-90
-95 HD3, RL = 1 k: -100
-100 25 MHz
-105 -110
1M 10M 100M -5 -3 -1 1 3 5
Frequency (Hz)
Test Tone Power at 50 : Load (dBm)
2 VPP AV = 2 RF = 237 Ω AV = 2 RL = 100 Ω RF = 237 Ω

Figure 9. Harmonic Distortion vs Load and Frequency Figure 10. 2 Tone 3rd Order Spurious Level
(SOIC Package) (SOIC Package)
100 25 -50
90 0.05% SETTLING 60MHz
-60
80 20
70 20MHz
-70
Settling Time (ns)

60 15
HD (dBc)
RS (:)

50 -80
40 0.1% SETTLING 10
RS
-90
30 10MHz
20 5
-100
10 5MHz

0 0 -110
1 10 100 1k 10k -10 -5 0 5 10 15 20
CL (pF) POUT (dBm)

AV = -1 RL = 1 kΩ AV = 2 RF = 237 Ω RL = 100 Ω

Figure 11. RS and Settling Time vs CL Figure 12. HD2 vs Output Power (Across 100 Ω)
(SOIC Package)

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Typical Characteristics (continued)

TA = 25°C, VS = ±5 V, RL = 100 Ω, Rf = 237 Ω (unless otherwise noted)
-50 0.5
60 MHz UNIT 1
-60 0

-0.5
-70
-1
20 MHz

VOS (mV)
HD (dBc)

-80
-1.5

-90 -2 UNIT 2

-100 10 MHz -2.5

5 MHz UNIT 3
-3
-110
-3.5
-120 -4
-10 -5 0 5 10 15 20 -40 -15 10 35 60 85 110 135
POUT (dBm) TEMPERATURE (°C)
AV = 2 RF = 237 Ω RL = 100 Ω

Figure 13. HD3 vs Output Power (Across 100 Ω) Figure 14. Input Offset for 3 Representative Units
(SOIC Package)
10 -4
UNIT 3
8
-5
6
-6 UNIT 3
4
2 IBN (µA) -7
IBI (µA)

UNIT 2
0 -8
UNIT 2
-2
UNIT 1 -9
-4
-10
-6 UNIT 1
-8 -11

-10 -12
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 15. Inverting Input Bias Figure 16. Non-Inverting Input Bias for 3 Representative
for 3 Representative Units Units
1000 70 15
+ PSRR
60 5
Hz)
Hz)

50 -5
100
CMRR/PSRR (dB)

INVERTING CURRENT
NOISE CURRENT (pA/
NOISE VOLTAGE (nV/

- PSRR
20 Log (RO)

40 -15
CMRR
30 -25
NON-INVERTING
10
CURRENT
20 -35
RO
VOLTAGE 10 -45
1
100 1k 10k 100k 1M 10M 0 -55
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Frequency (Hz)
VS = ±5 V RL = 100 Ω

Figure 17. Noise Figure 18. CMRR, PSRR, ROUT

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Typical Characteristics (continued)

TA = 25°C, VS = ±5 V, RL = 100 Ω, Rf = 237 Ω (unless otherwise noted)
120 220 0.03 0.006
110 200
100 180 0.02 0.004
DP
90 160
MAG 0.01 0.002
80 140

Phase (°)
Gain (dB)

DG (%)

DP (°)
70 120 0 0
60 100
PHASE -0.002
50 80 -0.01
DG
40 60
-0.02 -0.004
30 40
20 20 -0.006
-0.03
10k 100k 1M 10M 100M 1G -1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5
Frequency (Hz) VOUT (V)
VS = ±5 V RL = 100 Ω RF = 237 Ω RL = 150 Ω

Figure 19. Transimpedance Figure 20. DG/DP (NTSC)

0.03 0.009

0.02 0.006
DP
0.01 0.003
DG (%)

DP (°)
0 0

-0.01 -0.003

DG
-0.02 -0.006

-0.03 -0.009
-1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5
VOUT (V)
RF = 237 Ω RL = 150 Ω

Figure 21. DG/DP (PAL)

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7 Detailed Description

7.1 Overview
The LMH6702 has been optimized for exceptionally low harmonic distortion while driving very demanding
resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the
distortions introduced by the converter will dominate over the low LMH6702 distortions shown in Typical
Characteristics.

7.2 Feature Description

7.2.1 Harmonic Distortion
The capacitor CSS, shown across the supplies in Figure 24 and Figure 25, is critical to achieving the lowest 2nd
harmonic distortion. For absolute minimum distortion levels, it is also advisable to keep the supply decoupling
currents (ground connections to CPOS, and CNEG in Figure 24 and Figure 25) separate from the ground
connections to sensitive input circuitry (such as RG, RT, and RIN ground connections). Splitting the ground plane
in this fashion and separately routing the high frequency current spikes on the decoupling caps back to the
power supply (similar to Star Connection layout technique) ensures minimum coupling back to the input circuitry
and results in best harmonic distortion response (especially 2nd order distortion).
If this layout technique has not been observed on a particular application board, designer may actually find that
supply decoupling caps could adversely affect HD2 performance by increasing the coupling phenomenon already
mentioned. Figure 22 shows actual HD2 data on a board where the ground plane is shared between the supply
decoupling capacitors and the rest of the circuit. Once these capacitors are removed, the HD2 distortion levels
reduce significantly, especially between 10 MHz to 20 MHz, as shown in Figure 22:
-30

-40

CPOS & CNEG

-50
INCLUDED
HD2 (dBc)

-60
CPOS & CNEG
REMOVED
-70

-80

-90
1 10 100
Frequency (MHz)

Figure 22. Decoupling Current Adverse Effect on a Board with Shared Ground Plane

At these extremely low distortion levels, the high frequency behavior of decoupling capacitors themselves could
be significant. In general, lower value decoupling caps tend to have higher resonance frequencies making them
more effective for higher frequency regions. A particular application board which has been laid out correctly with
ground returns split to minimize coupling, would benefit the most by having low value and higher value capacitors
paralleled to take advantage of the effective bandwidth of each and extend low distortion frequency range.
Another important variable in getting the highest fidelity signal from the LMH6702 is the package itself. As
already noted, coupling between high frequency current transients on supply lines and the device input can lead
to excess harmonic distortion. An important source of this coupling is in fact through the device bonding wires. A
smaller package, in general, will have shorter bonding wires and therefore lower coupling. This is true in the case
of the SOT-23 compared to the SOIC package where a marked improvement in HD can be measured in the
SOT-23 package. Figure 23 shows the HD comparing SOT-23 to SOIC package:

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Feature Description (continued)

-60
HD2, SOIC
-65
-70
-75
HD2, SOT23

HD2 (dBc)
-80
-85
-90 HD3, SOIC
-95
HD3, SOT23
-100
-105

-110
1 10 100
Frequency (MHz)

Figure 23. SOIC and SOT-23 Packages Distortion Terms Compared

The LMH6702 data sheet shows both SOT-23 and SOIC data in Electrical Characteristics to aid in selecting the
right package. Typical Characteristics shows SOIC package plots only.

7.3 Device Functional Modes

7.3.1 2-Tone 3rd Order Intermodulation
Figure 10 shows a relatively constant difference between the test power level and the spurious level with the
difference depending on frequency. The LMH6702 does not show an intercept type performance, (where the
relative spurious levels change at a 2X rate versus the test tone powers), due to an internal full power bandwidth
enhancement circuit that boosts the performance as the output swing increases while dissipating negligible
quiescent power under low output power conditions. This feature enhances the distortion performance and full
power bandwidth to match that of much higher quiescent supply current parts.

7.3.2 DC Accuracy and Noise

The example in Equation 1 shows the output offset computation equation for the non-inverting configuration
using the typical bias current and offset specifications for AV = 2:
Output Offset:
VO = (±IBN · RIN ± VIO) (1 + RF/RG) ± IBI · RF
where
• RIN is the equivalent input impedance on the non-inverting input. (1)
Example computation for AV = +2, RF = 237Ω, RIN = 25Ω:
VO = (±6 μA × 25 Ω ± 1mV) (1 + 237/237) ± 8 μA × 237 = ±4.20 mV (2)
A good design, however, should include a worst case calculation using min/max numbers in the data sheet
tables, in order to ensure worst case operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in
Application Note OA--07, Current Feedback Op Amp Applications Circuit Guide (SNOA365). The two input bias
currents are physically unrelated in both magnitude and polarity for the current feedback topology. It is not
possible, therefore, to cancel their effects by matching the source impedance for the two inputs (as is commonly
done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage
and the two input noise currents, the output noise is developed through the same gain equations for each term
but combined as the square root of the sum of squared contributing elements. See Application Note OA-12,
Noise Analysis for Comlinear Amplifiers (SNOA375) for a full discussion of noise calculations for current
feedback amplifiers.

12 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Product Folder Links: LMH6702

 LMH6702
www.ti.com SNOSA03H – NOVEMBER 2002 – REVISED MAY 2016

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology.
The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the
feedback resistor value. The LMH6702 is optimized for use with a 237-Ω feedback resistor. Using lower values
can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth.

8.2 Typical Application

8.2.1 Feedback Resistor
The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology.
The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the
feedback resistor value. The LMH6702 is optimized for use with a 237-Ω feedback resistor. Using lower values
can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth.

+5V 6.8µF

.01µF AV = 1 +RF/RG = VOUT/VIN

VIN
3 7 CPOS
+ VOUT
CSS 6
RIN LMH6702
0.1µF
-
2 4 CNEG

RF
.01µF

RG
6.8µF
-5V

Figure 24. Recommended Non-Inverting Gain Circuit

+5V 6.8µF

RF VOUT
.01µF AV = =
RG VIN

3 7 CPOS
+ VOUT
CSS 6
25: LMH6702
0.1µF
-
2 4 CNEG

VIN RG RF
.01µF

RT SELECT RT TO
6.8µF YIELD DESIRED
-5V RIN = RT||RG

Figure 25. Recommended Inverting Gain Circuit

Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 13

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LMH6702
SNOSA03H – NOVEMBER 2002 – REVISED MAY 2016 www.ti.com

Typical Application (continued)

8.2.2 Design Requirements
The exceptional performance and uniquely targeted superior technical specifications of the LMH6702 make it a
natural choice for high speed data acquisition applications as a front end amplifier driving the input of a high
performance ADC. Of these specifications, the following can be discussed in more detail:
1. A bandwidth of 1.7 GHz and relative insensitivity of bandwidth to closed loop gain (characteristic of Current
Feedback architecture when compared to the traditional voltage feedback architecture) as shown in Figure 1.
2. Ultra-low distortion approaching -87 dBc at the lower frequencies and exceptional noise performance (see
Figure 9 and Figure 17).
3. Fast settling in less than 20 ns (see Figure 27).
As the input of an ADC could be capacitive in nature and could also alternate in capacitance value during a
typical acquisition cycle, the driver amplifier (LMH6702 in this case) should be designed so that it avoids
instability, peaking, or other undesirable artifacts.
For Capacitive Load Drive, see Figure 26, which shows a typical application using the LMH6702 to drive an
ADC.

ADC

+ RS
LMH6702
- CIN

Figure 26. Input Amplifier to ADC

8.2.3 Detailed Design Procedure

The series resistor, RS, between the amplifier output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels
of ringing in the pulse response. Figure 27 in Application Curve (RS and Settling Time vs CL) is an excellent
starting point for selecting RS. The value derived in that plot minimizes the step settling time into a fixed discrete
capacitive load with the output driving a very light resistive load (1 kΩ). Sensitivity to capacitive loading is greatly
reduced once the output is loaded more heavily. Therefore, for cases where the output is heavily loaded, RS
value may be reduced. The exact value may best be determined experimentally for these cases.
In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly
loaded and some capacitance is present at the output. Due to the much higher frequency response of the
LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance
(parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this
susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be
minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high
frequency resistive loading.
Referring back to Figure 26, it must be noted that several additional constraints should be considered in driving
the capacitive input of an ADC. There is an option to increase RS, band-limiting at the ADC input for either noise
or Nyquist band-limiting purposes. However, increasing RS too much can induce an unacceptably large input
glitch due to switching transients coupling through from the convert signal. Also, CIN is oftentimes a voltage
dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as RS is
increased. Only slight adjustments up or down from the recommended RS value should therefore be attempted in
optimizing system performance.

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 LMH6702
www.ti.com SNOSA03H – NOVEMBER 2002 – REVISED MAY 2016

Typical Application (continued)

8.2.4 Application Curve
100 25
90 0.05% SETTLING

80 20
70

Settling Time (ns)

60 15

RS (:)
50
40 0.1% SETTLING 10
RS
30
20 5
10
0 0
1 10 100 1k 10k
CL (pF)

AV = -1 RL = 1 kΩ

Figure 27. RS and Settling Time vs CL

9 Power Supply Recommendations

The LMH6702 can operate off a single supply or with dual supplies as long as the input CM voltage range
(CMIR) has the required headroom to either supply rail. Supplies should be decoupled with low inductance, often
ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is
recommended, and as in most high speed devices, it is advisable to remove ground plane close to device
sensitive pins such as the inputs.

10 Layout

10.1 Layout Guidelines

Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations. See Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers,
Application Note OA-15 (SNOA367). Texas Instruments suggests the following evaluation boards as a guide for
high frequency layout and as an aid in device testing and characterization. See Table 1 for details.
The LMH6702 evaluation board(s) is a good example of high frequency layout techniques as a reference.
General high-speed, signal-path layout suggestions include:
• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs.
However, open up both ground and power planes around the capacitive sensitive input and output device
pins as shown in Figure 28. After the signal is sent into a resistor, parasitic capacitance becomes more of a
bandlimiting issue and less of a stability issue.
• Use good, high-frequency decoupling capacitors (0.1 μF) on the ground plane at the device power pins as
shown in Figure 28. Higher value capacitors (2.2 μF) are required, but may be placed further from the device
power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling
capacitors that offer a much higher self-resonance frequency over standard capacitors.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces.
• The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into
the summing junction with minimal trace length to the device pin side of the resistor, as shown in Figure 29.
The other side of these elements can have more trace length if needed to the source or to ground.

Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: LMH6702
LMH6702
SNOSA03H – NOVEMBER 2002 – REVISED MAY 2016 www.ti.com

10.2 Layout Example

Figure 28. LMH6702 Evaluation Board Layer 1

Figure 29. LMH6702 Evaluation Board Layer 2

Table 1. Evaluation Board Comparison

DEVICE PACKAGE EVALUATION BOARD PART NUMBER
LMH6702MF SOT-23 LMH730216
LMH6702MA SOIC LMH730227

16 Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Product Folder Links: LMH6702

 LMH6702
www.ti.com SNOSA03H – NOVEMBER 2002 – REVISED MAY 2016

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation, see the following:
• Absolute Maximum Ratings for Soldering (SNOA549)
• Current Feedback Op Amp Applications Circuit Guide, Application Note OA--07 (SNOA365)
• Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367)
• Noise Analysis for Comlinear Amplifiers, Application Note OA-12 (SNOA375)
• Semiconductor and IC Package Thermal Metrics (SPRA953)

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
VIP10, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2002–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: LMH6702
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMH6702MA NRND SOIC D 8 95 Non-RoHS Call TI Level-1-235C-UNLIM -40 to 85 LMH67

& Green 02MA
LMH6702MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH67
02MA
LMH6702MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH67
02MA
LMH6702MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A83A

LMH6702MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A83A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6702MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6702MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6702MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6702MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6702MF/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LMH6702MFX/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LMH6702MA D SOIC 8 95 495 8 4064 3.05
LMH6702MA D SOIC 8 95 495 8 4064 3.05
LMH6702MA/NOPB D SOIC 8 95 495 8 4064 3.05

Pack Materials-Page 3
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/G 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/G 03/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/G 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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