Opa164X Soundplus™ High-Performance, Jfet-Input Audio Operational Amplifiers

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OPA1641, OPA1642, OPA1644

SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
OPA164x SoundPlus™ High-Performance, JFET-Input Audio Operational Amplifiers

1 Features 3 Description
•
1 Superior Sound Quality The OPA1641 (single), OPA1642 (dual), and
OPA1644 (quad) series are JFET-input, ultralow
• True JFET Input Operational Amplifier distortion, low-noise operational amplifiers fully
With Low Input Bias Current specified for audio applications.
• Low Noise: 5.1 nV/√Hz at 1 kHz
The OPA1641, OPA1642, and OPA1644 rail-to-rail
• Ultralow Distortion: 0.00005% at 1 kHz output swing allows increased headroom, making
• High Slew Rate: 20 V/μs these devices ideal for use in any audio circuit.
• Unity Gain Stable Features include 5.1-nV/√Hz noise, low THD+N
(0.00005%), a low input bias current of 2 pA, and low
• No Phase Reversal quiescent current of 1.8 mA per channel.
• Low Quiescent Current:
1.8 mA per Channel These devices operate over a very wide supply
voltage range of ±2.25 V to ±18 V. The OPA1641,
• Rail-to-rail Output OPA1642, and OPA1644 series of operational
• Wide Supply Range: ±2.25 V to ±18 V amplifiers are unity-gain stable and provide excellent
• Single, Dual, and Quad Versions Available dynamic behavior over a wide range of load
conditions.
2 Applications The dual and quad versions feature completely
• Professional Audio Equipment independent circuitry for lowest crosstalk and
freedom from interactions between channels, even
• Analog and Digital Mixing Consoles when overdriven or overloaded.
• Broadcast Studio Equipment
The OPA1641, OPA1642, and OPA1644 are
• High-End A/V Receivers specified from –40°C to +85°C. SoundPlus™
• High-End Blu-ray™ Players
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 4.90 mm × 3.90 mm
OPA1641
VSSOP (8) 3.00 mm × 3.00 mm
SOIC (8) 4.90 mm × 3.90 mm
OPA1642
VSSOP (8) 3.00 mm × 3.00 mm
SOIC (14) 8.65 mm × 3.90 mm
OPA1644
TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
Simplified Internal Schematic Extremely Stable Input Capacitance

V+
7.5
Common-Mode Capacitance (pF)
7
Traditional JFET-Input Amplifier
6.5
6 OPA164x Family
Pre-Output Driver OUT 5.5
IN- IN+ 5
4.5
V-
4
±10 ±8 ±6 ±4 ±2 0 2 4 6 8 10
Common-Mode Voltage (V) C004
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1641, OPA1642, OPA1644
SBOS484D – DECEMBER 2009 – REVISED APRIL 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 18
2 Applications ........................................................... 1 8.1 Application Information............................................ 18
3 Description ............................................................. 1 8.2 Typical Application ................................................. 25
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 27
5 Pin Configuration and Functions ......................... 4 10 Layout................................................................... 28
6 Specifications......................................................... 6 10.1 Layout Guidelines ................................................. 28
6.1 Absolute Maximum Ratings ..................................... 6 10.2 Layout Example .................................................... 29
6.2 ESD Ratings ............................................................ 6 11 Device and Documentation Support ................. 30
6.3 Recommended Operating Conditions....................... 6 11.1 Device Support .................................................... 30
6.4 Thermal Information .................................................. 6 11.2 Documentation Support ....................................... 30
6.5 Electrical Characteristics........................................... 7 11.3 Related Links ........................................................ 31
6.6 Typical Characteristics .............................................. 9 11.4 Community Resources.......................................... 31
7 Detailed Description ............................................ 14 11.5 Trademarks ........................................................... 31
7.1 Overview ................................................................. 14 11.6 Electrostatic Discharge Caution ............................ 31
7.2 Functional Block Diagram ....................................... 14 11.7 Glossary ................................................................ 31
7.3 Feature Description................................................. 15 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 17 Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2015) to Revision D Page
• Added TI Design .................................................................................................................................................................... 1

• Changed MSOP to VSSOP throughout document ................................................................................................................ 1
• Changed Supply voltage parameter in Recommended Operating Conditions table to split single and dual supply
specifications into separate rows for clarity ............................................................................................................................ 6
• Changed last column header in Thermal Information table from DGK (VSSOP) to PW (TSSOP) ........................................ 6
• Changed Noise subsection of Electrical Characteristics table: changed Input voltage noise parameter typical
specification and changed first two en parameter typical specifications................................................................................. 7
• Changed Input Bias Current subsection of Electrical Characteristics table ........................................................................... 7
• Changed VO parameter test conditions in Electrical Characteristics table ............................................................................ 8
• Added ISC parameter specifications to Electrical Characteristics table ................................................................................. 8
• Changed Temperature Range subsection of Electrical Characteristics table ....................................................................... 8
• Changed third paragraph of Power Dissipation and Thermal Protection section for clarity ................................................ 23
• Changed second paragraph of Electrical Overstress section for clarity............................................................................... 23
• Added text reference for Equation 5 .................................................................................................................................... 27
Changes from Revision B (August 2010) to Revision C Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Added text to last bullet of Layout Guidelines section.......................................................................................................... 28
Changes from Revision A (April 2010) to Revision B Page
• Removed product-preview information for MSOP-8 package version of OPA1641............................................................... 1
2 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA1641 OPA1642 OPA1644

OPA1641, OPA1642, OPA1644
www.ti.com SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
Changes from Original (December 2009) to Revision A Page
• Removed product-preview information for OPA1644 device packages throughout document.............................................. 1
Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

OPA1641, OPA1642, OPA1644
5 Pin Configuration and Functions
OPA1641: D and DGK Packages

8-Pin SOIC and VSSOP
Top View
(1) (1)
NC 1 8 NC
-In 2 7 V+
+In 3 6 Out
(1)
V- 4 5 NC
(1) NC denotes no internal connection.
Pin Functions: OPA1641

PIN
I/O DESCRIPTION
NO. NAME
1 NC — No connection
2 –IN I Inverting input
3 +IN I Noninverting input
4 V– — Negative (lowest) power supply
6 OUT O Output
7 V+ — Positive (highest) power supply
OPA1642: D and DGK Packages

8-Pin SOIC and VSSOP
Top View
OUT A 1 8 V+
-In A 2 A 7 Out B
+In A 3 B 6 -In B
V- 4 5 +In B

PIN
I/O DESCRIPTION
NO. NAME
1 OUT A O Output, channel A
2 –IN A I Inverting input, channel A
3 +IN A I Noninverting input, channel A
5 +IN B I Noninverting input, channel B
6 –IN B I Inverting input, channel B
7 OUT B O Output, channel B

OPA1641, OPA1642, OPA1644
OPA1644: D and PW Packages

14-Pin SOIC and TSSOP
Top View
Out A 1 14 Out D
-In A 2 13 -In D
A D
+In A 3 12 +In D
V+ 4 11 V-
+ In B 5 10 + In C
B C
-In B 6 9 -In C
Out B 7 8 Out C

PIN
I/O DESCRIPTION
NO. NAME
1 OUT A O Output, channel A
2 –IN A I Inverting input, channel A
3 +IN A I Noninverting input, channel A
5 +IN B I Noninverting input, channel B
6 –IN B I Inverting input, channel B
7 OUT B O Output, channel B
8 OUT C O Output, channel C
9 –IN C I Inverting input, channel C
10 +IN C I Noninverting input, channel C
12 +IN D I Noninverting input, channel D
13 –IN D I Inverting input, channel D
14 OUT D O Output, channel D

OPA1641, OPA1642, OPA1644
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VS Supply voltage 40 V
(2)
VIN Input voltage (V–) – 0.5 (V+) + 0.5 V
IIN Input current (2) ±10 mA
VIN(DIFF) Differential input voltage ±VS V
(3)
IO Output short-circuit Continuous
TA Operating temperature –55 125 °C
TJ Junction temperature –65 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current-limited to 10 mA or less. The input voltage and output negative-voltage ratings can be exceeded if the input and output current
ratings are followed.
(3) Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±3000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Single supply 4.5 36
Supply voltage (V+, V–) V
Dual supply ±2.25 ±18
Specified temperature –40 85 °C
6.4 Thermal Information

OPA1641, OPA1642 OPA1644
THERMAL METRIC (1) D (SOIC) DGK (VSSOP) D (SOIC) PW (TSSOP) UNIT
8 PINS 8 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 160 180 97 135 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 75 55 56 45 °C/W
RθJB Junction-to-board thermal resistance 60 130 53 66 °C/W
ψJT Junction-to-top characterization parameter 9 n/a 19 n/a °C/W
ψJB Junction-to-board characterization parameter 50 120 46 60 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

OPA1641, OPA1642, OPA1644
6.5 Electrical Characteristics

at TA = 25°C, VS = 4.5 V to 36 (±2.25 V to ±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO PERFORMANCE
0.00005%
THD+N Total harmonic distortion + noise G = +1, f = 1 kHz, VO = 3 VRMS
–126 dB
SMPTE/DIN two-tone, 4:1 0.00004%
(60 Hz and 7 kHz), G = +1,
VO = 3 VRMS –128 dB
DIM 30 (3-kHz square wave and 0.00008%
IMD Intermodulation distortion 15-kHz sine wave), G = +1,
CCIF twin-tone 0.00007%
(19 kHz and 20 kHz), G = +1,
FREQUENCY RESPONSE
GBW Gain-bandwidth product G=1 11 MHz
SR Slew rate G=1 20 V/μs
Full-power bandwidth (1) VO = 1 VP 3.2 MHz
Overload recovery time (2) G = –10 600 ns
Channel separation (dual and quad) f = 1 kHz –126 dB
NOISE
Input voltage noise f = 20 Hz to 20 kHz 4.3 μVPP
f = 10 Hz 8
en Input voltage noise density f = 100 Hz 5.8 nV/√Hz
f = 1 kHz 5.1
In Input current noise density f = 1 kHz 0.8 fA/√Hz
OFFSET VOLTAGE
VOS Input offset voltage VS = ±18 V 1 3.5 mV
PSRR VOS vs power supply VS = ±2.25 V to ±18 V 0.14 2 μV/V
INPUT BIAS CURRENT
IB Input bias current VCM = 0 V ±2 ±20 pA
IOS Input offset current VCM = 0 V ±2 ±20 pA
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–)–0.1 (V+)–3.5 V
VCM = (V–) – 0.1 V to (V+) – 3.5 V,
CMRR Common-mode rejection ratio 120 126 dB
VS = ±18 V
INPUT IMPEDANCE
Differential 1013 || 8 Ω || pF
13
Common-mode VCM = (V–) – 0.1 V to (V+) – 3.5 V 10 || 6 Ω || pF
OPEN-LOOP GAIN
(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V,
120 134
RL = 10 kΩ
AOL Open-loop voltage gain dB
(V–) + 0.35 V ≤ VO ≤ (V+) – 0.35 V,
114 126
RL = 2 kΩ
(1) Full power bandwidth = SR / (2π × VP), where SR = slew rate.

(2) See Figure 19 and Figure 20.

OPA1641, OPA1642, OPA1644
Electrical Characteristics (continued)

at TA = 25°C, VS = 4.5 V to 36 (±2.25 V to ±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
RL = 10 kΩ, AOL ≥ 120 dB (V–)+0.2 (V+)–0.2
VO Voltage output swing from rail V
RL = 2 kΩ, AOL ≥ 114 dB (V–)+0.35 (V+)–0.35
IOUT Output current See Typical Characteristics
ZO Open-loop output impedance See Typical Characteristics
Source 36
ISC Short-circuit current mA
Sink –30
CLOAD Capacitive load drive See Typical Characteristics
POWER SUPPLY
VS Specified voltage ±2.25 ±18 V
IQ Quiescent current (per amplifier) IOUT = 0 A 1.8 2.3 mA
TEMPERATURE RANGE
Specified range –40 85 °C
Operating range –55 125 °C
8-pin SOIC package 138
8-pin VSSOP package 180
Thermal resistance °C/W
14-pin SOIC package 97
14-pin TSSOP package 135

OPA1641, OPA1642, OPA1644
6.6 Typical Characteristics

at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
100
Voltage Noise Density (nV/ÖHz)
100nV/div
10
1
0.1 1 10 100 1k 10k 100k
Frequency (Hz) Time (1s/div)
Figure 1. Input Voltage Noise Density vs Frequency Figure 2. 0.1-Hz to 10-Hz Noise
35 160
Maximum output
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
VS = ±15V voltage range 140
30
without slew-rate CMRR
120
Output Voltage (VPP)
25 induced distortion
100
20 -PSRR
80
15 +PSRR
60
VS = ±5V
10
40
5 VS = ±2.25V
20
0 0
10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
Figure 3. Maximum Output Voltage vs Frequency Figure 4. CMRR and PSRR vs Frequency
(Referred to Input)
140 180 30
120
Gain 20
100 135 G = +10
Phase (degrees)
80
Gain (dB)
10
Gain (dB)
60 90 G = +1
40 0
Phase
20 45
-10
0 G = -1
-20 0 -20
50 100 1k 10k 100k 1M 10M 100M 100k 1M 10M 100M
Figure 5. Gain and Phase vs Frequency Figure 6. Closed-Loop Gain vs Frequency

OPA1641, OPA1642, OPA1644
Typical Characteristics (continued)

0.001 -100 0.01 -80
VOUT = 3VRMS
Total Harmonic Distortion + Noise (dB)

VOUT = 3VRMS
Total Harmonic Distortion + Noise (%)

G = -1
G = -1
BW = 80kHz BW > 500kHz RL = 600W
RL = 2kW
G = +1
RL = 600W 0.001 -100
G = -1
G = -1
RL = 2kW
0.0001 RL = 600W -120 G = +1
RL = 600W
G = +1
0.0001 -120
RL = 2kW
G = +1
RL = 2kW
0.00001 -140 0.00001 -140
10 100 1k 10k 20k 10 100 1k 10k 100k
Figure 7. THD+N Ratio vs Frequency Figure 8. THD+N Ratio vs Frequency

0.01 -80 0.01 -80
BW = 80kHz Total Harmonic Distortion + Noise (dB) G = +1
1kHz Signal
Intermodulation Distortion (dB)

Intermodulation Distortion (%)
RSOURCE = 0W SMPTE/DIN
Two-Tone
0.001 -100 0.001 4:1 (60Hz and 7kHz) -100
DIM30
(3kHz square wave
and 15kHz sine wave)
0.0001 -120 0.0001 -120
G = -1, RL = 2kW CCIF Twin-Tone

G = +1, RL = 2kW (19kHz and 20kHz)
0.00001 -140 0.00001 -140
0.1 1 10 20 0.1 1 10 20
Output Amplitude (VRMS) Output Amplitude (VRMS)
Figure 9. THD+N Ratio vs Output Amplitude Figure 10. Intermodulation Distortion

vs Output Amplitude
-80
VS = ±15V
VOUT = 3VRMS
-90
G = +1
Channel Separation (dB)
Output
-100
RL = 600W
5V/div
-110
+18V
-120 RL = 2kW
OPA1641
-130 Output
-18V
RL = 5kW 37VPP
Sine Wave
-140 (±18.5V)
10 100 1k 10k 100k
Frequency (Hz) Time (0.4ms/div)
Figure 11. Channel Separation vs Frequency Figure 12. No Phase Reversal

OPA1641, OPA1642, OPA1644

G = +1 G = -1
CL = 100pF CL = 100pF
20mV/div
20mV/div
+15V
RI = 2kW RF = 2kW
OPA1641 +15V
OPA1641
-15V RL CL
CL
-15V
Time (100ns/div) Time (100ns/div)
Figure 13. Small-Signal Step Response (100 mV) Figure 14. Small-Signal Step Response (100 mV)
G = +1 G = -1
CL = 100pF CL = 100pF
2V/div
2V/div
Time (400ns/div) Time (400ns/div)
Figure 15. Large-Signal Step Response Figure 16. Large-Signal Step Response
VOUT G = -10 G = -10
VIN
5V/div
5V/div
20kW
20kW
2kW
VIN 2kW
OPA1641 VOUT VOUT

OPA1641
VIN VIN
VOUT
Time (0.4ms/div) Time (0.4ms/div)
Figure 17. Positive Overload Recovery Figure 18. Negative Overload Recovery

OPA1641, OPA1642, OPA1644

40 45
G = +1 ROUT = 0W RI = 2kW RF = 2kW ROUT = 0W
+15V
35 ROUT
40 +15V
OPA1641 ROUT
35 OPA1641
30 -15V
RL CL
CL
ROUT = 24W
30 -15V
Overshoot (%)
Overshoot (%)
25
25
20 ROUT = 24W
20
15 ROUT = 51W
ROUT = 51W 15
10 10
5 5
G = -1
0 0
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF) Capacitive Load (pF)
Figure 19. Small-Signal Overshoot vs Capacitive Load Figure 20. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) (100-mV Output Step)
0 80
70
-0.2
10kW 60
+IB
50
-0.4
IB and IOS (pA)
AOL (mV/V)
40
-0.6 30
2kW
20
-0.8 -IB
10
0
-1.0
-10
-IOS
-1.2 -20
-40 -15 10 35 60 85 -40 -15 10 35 60 85
Temperature (°C) Temperature (°C)
Figure 21. Open-Loop Gain vs Temperature Figure 22. IB and IOS vs Temperature
10 2.5
VS = ±18V
8
6 2.0
+IB
4 -IB
IB and IOS (pA)
2 1.5
IQ (mA)
0
IOS
-2 1.0
-4
-6 0.5
-8
Common-Mode Range
-10 0
-18 -12 -6 0 6 12 18 -40 -25 -10 5 20 35 50 65 80 95 110 125
Common-Mode Voltage (V) Temperature (°C)
Figure 23. IB and IOS vs Common-Mode Voltage Figure 24. Quiescent Current vs Temperature

OPA1641, OPA1642, OPA1644

2.00 60
1.75
50
1.50 ISC-SOURCE
40
1.25
ISC (mA)
IQ (mA)
1.00 30
ISC-SINK
0.75
20
0.50
10 VOUT = Midsupply
0.25 Specified Supply-Voltage Range
(includes self-heating)
0 0
0 4 8 12 16 20 24 28 32 36 -50 -25 0 25 50 75 100 125
Supply Voltage (V) Temperature (°C)
Figure 25. Quiescent Current vs Supply Voltage Figure 26. Short-Circuit Current vs Temperature
18.0 1k
17.5
17.0
16.5
Output Voltage (V)
100
16.0
ZO (W)
+85°C
-40°C +25°C +125°C
-16.0
10
-16.5
-17.0
-17.5
-18.0 1
0 10 20 30 40 50 10 100 1k 10k 100k 1M 10M 100M
Output Current (mA) Frequency (Hz)
Figure 27. Output Voltage vs Output Current Figure 28. Open-Loop Output Impedance vs Frequency

OPA1641, OPA1642, OPA1644
7 Detailed Description
7.1 Overview
The OPA164x family of operational amplifiers combine an ultra low noise JFET input stage with a rail-to-rail
output stage to provide high overall performance in audio applications. The internal topology is selected
specifically to deliver extremely low distortion, consume limited power, and accommodate small packages. These
amplifiers are well-suited for analog signal processing applications such as active filter circuits, pre-amplifiers,
and tone controls. The unique input stage design and semiconductor processes used in this device deliver
extremely high performance even in applications with high source impedance and wide common-mode voltage
swings.
7.2 Functional Block Diagram
V+
Pre-Output Driver OUT
IN- IN+
V-

OPA1641, OPA1642, OPA1644
7.3 Feature Description

7.3.1 Phase Reversal Protection
The OPA164x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPA164x prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 29.
5V/div Output
+18V
OPA1641
Output
-18V
37VPP
Sine Wave
(±18.5V)
Time (0.4ms/div)
Figure 29. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
7.3.2 Output Current Limit

The output current of the OPA164x series is limited by internal circuitry to 36 mA and –30 mA (sourcing and
sinking), to protect the device if the output is accidentally shorted. This short-circuit current depends on
temperature; see Figure 26.
Although uncommon for most modern audio applications to require 600-Ω load drive capability, many audio
operational amplifier applications continue to specify the total harmonic distortion (THD+N) at 600-Ω load for
comparative purposes. Figure 7 and Figure 8 provide typical THD+N measurement curves for the OPA164x
series, where the output drives a 3-VRMS signal into a 600-Ω load. However, correct device operation cannot be
ensured when driving 600-Ω loads at full supply. Depending on supply voltage and temperature, this operating
condition can possibly trigger the output current limit circuitry of the device.
7.3.3 EMI Rejection Ratio (EMIRR)

The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this document provides the EMIRR IN+, which specifically describes the EMIRR performance
when the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the
noninverting input is tested for EMIRR for the following three reasons:
• Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
• The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to the
noninverting input pin with no complex interactions from other components or connecting PCB traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in application report EMI
Rejection Ratio of Operational Amplifiers (SBOA128), available for download at www.ti.com.

OPA1641, OPA1642, OPA1644
Feature Description (continued)

The EMIRR IN+ of the OPA164x is plotted versus frequency in Figure 30. If available, any dual and quad
operational amplifier device versions have nearly identical EMIRR IN+ performance. The OPA164x unity-gain
bandwidth is 11 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
operational amplifier bandwidth.
140
120
100
EMIRR (dB) 80
60
40
20
0
10M 100M 1G 10G
Frequency (Hz) C003
Figure 30. OPA164x EMIRR vs Frequency
Table 1 lists the EMIRR IN+ values for the OPA164x at particular frequencies commonly encountered in real-
world applications. Applications listed in Table 1 can be centered on or operated near the particular frequency
shown. This information can be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 1. OPA164x EMIRR IN+ for Frequencies of Interest

FREQUENCY APPLICATION, ALLOCATION EMIRR IN+
400 MHz Mobile radio, mobile satellite, space operation, weather, radar, UHF 53.1 dB
GSM, radio communication and navigation, GPS (to 1.6 GHz), ISM,
900 MHz 72.2 dB
aeronautical mobile, UHF
1.8 GHz GSM, mobile personal comm. broadband, satellite, L-band 80.7 dB
2.4 GHz 802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur radio and satellite, S-band 86.8 dB
3.6 GHz Radiolocation, aero comm./nav., satellite, mobile, S-band 91.7 dB
802.11a/n, aero communication and navigation, mobile communication,
5 GHz 96.6 dB
space and satellite operation, C-band

OPA1641, OPA1642, OPA1644
7.3.3.1 EMIRR IN+ Test Configuration

Figure 31 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input pin using a transmission line. The operational amplifier is configured in a
unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A
large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this effect is
characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is sampled
and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can interfere with
multimeter accuracy. See EMI Rejection Ratio of Operational Amplifiers (SBOA128) for more details.
Ambient temperature: 25Û&
+VS
±
50 Low-Pass Filter
+
RF source
-VS
DC Bias: 0 V Sample /
Modulation: None (CW) Averaging Digital Multimeter
Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF
supply decoupling
Figure 31. EMIRR IN+ Test Configuration Schematic
7.4 Device Functional Modes

7.4.1 Operating Voltage
The OPA1641, OPA1642, and OPA1644 series of operational amplifiers can be used with single or dual supplies
from an operating range of VS = 4.5 V (±2.25 V) and up to VS = 36 V (±18 V). These devices do not require
symmetrical supplies; only a minimum supply voltage of 4.5 V (±2.25 V) is required. For VS less than ±3.5 V, the
common-mode input range does not include midsupply. Supply voltages higher than 40 V can permanently
damage the device; see the Absolute Maximum Ratings table for more information. Key parameters are specified
over the operating temperature range, TA = –40°C to +85°C. Key parameters that vary over the supply voltage or
temperature range are illustrated in the Typical Characteristics section.

OPA1641, OPA1642, OPA1644
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The OPA1641, OPA1642, and OPA1644 are unity-gain stable, audio operational amplifiers with very low noise,
input bias current, and input offset voltage. Applications with noisy or high-impedance power supplies require
decoupling capacitors placed close to the device pins. In most cases, 0.1-μF capacitors are adequate. Figure 32
shows a simplified schematic of the OPA1641.
V+
Pre-Output Driver OUT
IN- IN+
V-
Figure 32. Simplified Internal Schematic
8.1.1 Noise Performance

Figure 33 illustrates the total circuit noise for varying source impedances with the operational amplifier in a unity-
gain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPA1641, OPA1642, and OPA1644 are shown with total circuit noise calculated. The operational amplifier
contributes both a voltage noise component and a current noise component. The voltage noise is commonly
modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying
component of the input bias current and reacts with the source resistance to create a voltage component of
noise. Therefore, the lowest noise operational amplifier for a given application depends on the source
impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The
OPA1641, OPA1642, and OPA1644 family has both low voltage noise and extremely low current noise because
of the FET input of the operational amplifier. As a result, the current noise contribution of the OPA164x series is
negligible for any practical source impedance, which makes the OPA164x series of amplifiers better choices for
applications with high source impedance.
The equation in Figure 33 illustrates the calculation of the total circuit noise, where:
• en = voltage noise
• In = current noise
• RS = source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
• T = temperature in degrees Kelvin (K)
For more details on calculating noise, see the Basic Noise Calculations section.

OPA1641, OPA1642, OPA1644
Application Information (continued)
10k
Votlage Noise Spectral Density, EO

EO
OPA1611
1k
RS
100
OPA1641
Resistor Noise
10
2 2 2
EO = en + (in RS) + 4kTRS
1
100 1k 10k 100k 1M
Source Resistance, RS (W)
Figure 33. Noise Performance of the OPA1611 and OPA1641 in a Unity-Gain Buffer Configuration
8.1.2 Basic Noise Calculations

Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall operational amplifier noise performance. Total
noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 33. The source impedance is usually fixed; consequently, select the
operational amplifier and the feedback resistors to minimize the respective contributions to the total noise.
Figure 34 illustrates both noninverting (A) and inverting (B) operational amplifier circuit configurations with gain.
In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current
noise of the operational amplifier reacts with the feedback resistors to create additional noise components.
However, the extremely low current noise of the OPA164x means that the device current noise contribution can
be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Note that low
impedance feedback resistors do load the output of the amplifier. The equations for total noise are given in
Figure 34 for both configurations.

OPA1641, OPA1642, OPA1644
A) Noise in Noninverting Gain Configuration Noise at the output:

R2
2 2 2
2
R2 2
R2 2 2
R2
R1 EO = 1+ e +
n e1 + e2 + 1 + es2
R1 R1 R1
EO
RS
Where eS = 4kTRS = thermal noise of RS
e1 = 4kTR1 = thermal noise of R1

VS
B) Noise in Inverting Gain Configuration Noise at the output:
R2 2 2 2
2 R2 2 R2 2 2 R2
EO = 1+ en + e + e2 +
1 e s2
R1 R1 + RS R 1 + RS R 1 + RS
EO
RS
Where eS = 4kTRS = thermal noise of RS

VS
For the OPA164x series op amps at 1kHz, en = 5.1nV/ÖHz
Figure 34. Noise Calculation in Gain Configurations

OPA1641, OPA1642, OPA1644
8.1.3 Total Harmonic Distortion Measurements

The OPA164x series operational amplifiers have excellent distortion characteristics. THD + noise is below
0.00005% (G = 1, VO = 3 VRMS, BW = 80 kHz) throughout the audio frequency range, 20 Hz to 20 kHz, with a
2-kΩ load (see Figure 7).
The distortion produced by the OPA164x series operational amplifiers is below the measurement limit of many
commercially available distortion analyzers. However, a special test circuit (such as shown in Figure 35) can be
used to extend the measurement capabilities.
Operational amplifier distortion can be considered an internal error source that can be referred to the input.
Figure 35 shows a circuit that causes the operational amplifier distortion to be 101 times (or approximately
40 dB) greater than that normally produced by the operational amplifier. The addition of R3 to the otherwise
standard noninverting amplifier configuration alters the feedback factor or noise gain of the circuit. The closed-
loop gain is unchanged, but the feedback available for error correction is reduced by a factor of 101, thus
extending the resolution by 101. Note that the input signal and load applied to the operational amplifier are the
same as with conventional feedback without R3. Keep the value of R3 small to minimize any effect on distortion
measurements.
The validity of this technique can be verified by duplicating measurements at high gain or high frequency where
the distortion is within the measurement capability of the test equipment. Measurements for this document were
made with an audio precision system two distortion and noise analyzer that greatly simplifies such repetitive
measurements. The measurement technique can, however, be performed with manual distortion measurement
instruments.
space
R1 R2
SIGNAL DISTORTION
GAIN GAIN R1 R2 R3
1 101 ¥ 1kW 10W
R3 OPA1641 VO = 3VRMS
R2 11 101 100W 1kW 11W
Signal Gain = 1+
R1
R2
Distortion Gain = 1+
R1 II R3
Generator Analyzer
Output Input
Audio Precision
System Two(1) Load
with PC Controller
(1) For measurement bandwidth, see Figure 7 through Figure 10.
Figure 35. Distortion Test Circuit
8.1.4 Source Impedance and Distortion

In traditional JFET-input operational amplifiers, the impedance applied to the positive and negative inputs in
noninverting applications must be matched for lowest distortion. Legacy methods for fabricating the JFETs in the
FET input stage exhibit a varying input capacitance with applied common-mode input voltage. In inverting
configurations, the input does not vary with input voltage because the inverting input is held at virtual ground.
However, in noninverting applications, the inputs do vary, and the gate-to-source voltage is not constant. This
effect produces increased distortion as a result of the varying capacitance for unmatched source impedances.
However, the OPA164x family of amplifiers is designed to maintain a constant input capacitance with varying
common-mode voltage to prevent this mechanism of distortion. The variation of input capacitance with common-
mode voltage for a traditional amplifier is compared to the OPA164x family in Figure 36.

OPA1641, OPA1642, OPA1644
7.5
Common-Mode Capacitance (pF)

7
6.5
6 OPA164x Family
5.5
4.5
4
±10 ±8 ±6 ±4 ±2 0 2 4 6 8 10
Common-Mode Voltage (V) C004
Figure 36. Input Capacitance of the OPA164x Family of Amplifiers Compared to Traditional JFET-input
Amplifiers
By stabilizing the input capacitance, the distortion performance of the amplifier is greatly improved for
noninverting configurations with high source impedances. The measured performance of an OPA164x amplifier
is compared to a traditional JFET-input amplifier in Figure 37. The unity-gain configuration, high source
impedance, and large-signal amplitude produce additional distortion in the traditional amplifier.
1 -40

10 k
+
±
-50
5 VRMS
0.1 -60
-70
0.01 -80
-90
OPA164x Amplifier
0.001 -100
-110
0.0001 -120
10 100 1000 10000
Frequency (Hz) C005
Figure 37. Measured THD+N of the OPA164x Family of Amplifiers Compared to Traditional JFET-input
Amplifiers
8.1.5 Capacitive Load and Stability

The dynamic characteristics of the OPA164x are optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50 Ω,
for example) in series with the output.
Figure 19 and Figure 20 illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of
ROUT. Also, see Applications Bulletin AB-028, Feedback Plots Define Op Amp AC Performance (SBOA015)
available for download at www.ti.com for details of analysis techniques and application circuits.
8.1.6 Power Dissipation and Thermal Protection

The OPA164x series of operational amplifiers are capable of driving 2-kΩ loads with power-supply voltages of up
to ±18 V over the specified temperature range. In a single-supply configuration, where the load is connected to
the negative supply voltage, the minimum load resistance is 2.8 kΩ at a supply voltage of 36 V. For lower supply
voltages (either single-supply or symmetrical supplies), a lower load resistance can be used, as long as the
output current does not exceed 13 mA; otherwise, the device short-circuit current protection circuit can activate.

OPA1641, OPA1642, OPA1644
Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction
used in the OPA1641, OPA1642, and OPA1644 series of devices improves heat dissipation compared to
conventional materials. PCB layout can also help reduce a possible increase in junction temperature. Wide
copper traces help dissipate the heat by functioning as an additional heatsink. Temperature rise can be further
minimized by soldering the devices directly to the PCB rather than using a socket.
Although the output current is limited by internal protection circuitry, accidental shorting one or more output
channels of a device can result in excessive heating. For instance, when an output is shorted to mid-supply, the
typical short-circuit current of 36 mA leads to an internal power dissipation of over 600 mW at a supply of ±18 V.
In case of a dual OPA1642 in an VSSOP-8 package (thermal resistance θJA = 180°C/W), such a power
dissipation results in the die temperature to be 220°C above ambient temperature, when both channels are
shorted. This temperature increase will destroy the device.
To prevent such excessive heating that can destroy the device, the OPA164x series has an internal thermal
shutdown circuit that shuts down the device if the die temperature exceeds approximately 180°C. When this
thermal shutdown circuit activates, a built-in hysteresis of 15°C ensures that the die temperature must drop to
approximately 165°C before the device switches on again.
8.1.7 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 38 illustrates the ESD circuits contained in the OPA164x series (indicated by the dashed line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines where an internal absorption device is connected. This
protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device can activate.
The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the
OPA164x but below the device breakdown voltage level. When this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one illustrated in Figure 38, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, some of the internal ESD protection circuits can be biased on and conduct current. Any
such current flow occurs through steering diode paths and rarely involves the absorption device.
Figure 38 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the datasheet specifications recommend that applications
limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.

OPA1641, OPA1642, OPA1644
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies +VS and –VS are at 0 V. The amplifier behavior depends on the supply characteristic when at
0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current can be supplied by the input source through the current steering diodes. This state is not
a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance,
then the current through the steering diodes can become quite high. The current level depends on the ability of
the input source to deliver current, and any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes can be
added to the supply pins, as shown in Figure 38. The Zener voltage must be selected such that the diode does
not turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
(2)
TVS
RF
+VS
+V
OPA1641
RI
-In ESD Current-
Steering Diodes
(3) Op-Amp Out
RS
+In Core
Edge-Triggered ESD
Absorption Circuit RL
ID
(1)
VIN -V
-VS
(2)
TVS
(1) VIN = +VS + 500 mV.

(2) TVS: +VS(max) > VTVSBR (Min) > +VS
(3) Suggested value is approximately 1 kΩ.
Figure 38. Equivalent Internal ESD Circuitry and the Relation to a Typical Circuit Application

OPA1641, OPA1642, OPA1644
8.2 Typical Application

The noise and distortion performance of the OPA164x family of amplifiers is exceptional in applications with high
source impedances, which makes these devices an excellent choice in preamplifier circuits for moving magnet
phono cartridges. The high source impedance of the cartridge, and high gain required by the RIAA playback
curve at low frequency, requires an amplifier with both low input current noise and low input voltage noise.
+15 V
RC 1.5k LC 600mH C5
R5
OPA1642 100uF
++ 100 Output
R1 C1 -
VC 47k 150pF
R6
-15 V 100k
R2 R3
Moving-Magnet Phono Cartridge
118k 10k
C2 C3
27nF 7.5nF
R4
127
C4
100uF
Figure 39. Preamplifier Circuit for Vinyl Record Playback With Moving-Magnet Phono Cartridges
(Single Channel Shown)
8.2.1 Design Requirements

• Gain: 40 dB (1 kHz)
• RIAA Accuracy: ±0.5 dB (100 Hz to 20 kHz)
• Power Supplies: ±15 V
8.2.2 Detailed Design Procedure

Vinyl records are recorded using an equalization curve specified by the Recording Institute Association of
America (RIAA). The purpose of this equalization curve is to decrease the amount of space occupied by a grove
on the record and therefore maximize the amount of information able to be stored. Proper playback of music
stored on the record requires a preamplifier circuit that applies the inverse transfer function of the recording
equalization curve. The combination of the recording equalization and the playback equalization results in a flat
frequency response over the audio range; see Figure 40.

OPA1641, OPA1642, OPA1644
Typical Application (continued)
20
15
Playback Curve
10
5
Gain (dB)
Combined Response
-5
-10
Recording Curve
-15
-20
10 100 1000 10000
Frequency (Hz)
C009
Figure 40. RIAA Recording and Playback Curves Normalized at 1 kHz
The basic RIAA playback curve implements three time constants: 75 μs, 380 μs, and 3180 μs. An IEC
amendment is later added to the playback curve and implements a pole in the curve at 20 Hz with the intent of
protecting loudspeakers from excessive low frequency content. Rather than strictly adhering to the IEC
amendment, this design moves this pole to a lower frequency to improve low frequency response and still
providing protection for loudspeakers.
Resistor R1 and capacitor C1 are selected to provide the proper input impedance for the moving magnet
cartridge. Cartridge loading is specified by the manufacturer in the cartridge datasheet and is absolutely crucial
for proper response at high frequency. 47 kΩ is a common value for the input resistor, and the capacitive loading
is usually specified to 200 pF to 300 pF per channel. This capacitive loading specification includes the
capacitance of the cable connecting the turntable to the preamplifier, as well as any additional parasitic
capacitances at the preamplifier input. Therefore, the value of C1 must be less than the loading specification to
account for these additional capacitances.
The output network consisting of R5, R6, and C5 serves to ac couple the preamplifier circuit to any subsequent
electronics in the signal path. The 100-Ω resistor R5 limits in-rush current into coupling capacitor C5 and
prevents parasitic capacitance from cabling from causing instability. R6 prevents charge accumulation on C5.
Capacitor C5 is chosen to be the same value as C4; for simplicity however, the value of C5 must be large
enough to avoid attenuating low frequency information.
The feedback resistor elements must be selected to provide the correct response within the audio bandwidth. In
order to achieve the correct frequency response, the passive components in Figure 39 must satisfy Equation 1,
Equation 2, and Equation 3:
R2 u C2 3180Ps (1)
R3 u C3 75Ps (2)
R2 || R3 u C2 C3 318Ps (3)
R2, R3, and R4 must also be selected to meet the design requirements for gain. The gain at 1 kHz is determined
by subtracting 20 dB from gain of the circuit at very low frequency (near dc), as shown in Equation 4:
A1kHz ALF 20dB (4)

OPA1641, OPA1642, OPA1644
Typical Application (continued)

Therefore, the low frequency gain of the circuit must be 60 dB to meet the goal of 40 dB at 1 kHz and is
determined by resistors R2, R3, and R4 as shown in Equation 5:
R3 R 2
ALF 1 1000(60dB)
R4 (5)
Because there are multiple combinations of passive components that satisfy these equations, a spreadsheet or
other software calculation tool is the easiest method to examine resistor and capacitor combinations.
Capacitor C4 forces the gain of the circuit to unity at dc in order to limit the offset voltage at the output of the
preamplifier circuit. The high-pass corner frequency created by this capacitor is calculated by Equation 6:
1
FHP
2SR 4 C4 (6)
The circuit described in Figure 39 is constructed with 1% tolerance resistors and 5% tolerance NP0, C0G
ceramic capacitors without any additional hand sorting. The large value of C4 typically requires an electrolytic
type to be used. However, electrolytic capacitors have the potential to introduce distortion into the signal path.
This circuit is constructed using a bipolar electrolytic capacitor specifically intended for audio applications.
8.2.3 Application Curves

The deviation from the ideal RIAA transfer function curve is shown in Figure 41 and normalized to an ideal gain
of 40 dB at 1 kHz. The measured gain at 1 kHz is 0.05 dB less than the design goal, and the maximum deviation
from 100 Hz to 20 kHz is 0.18 dB. The deviation from the ideal curve can be improved by hand-sorting resistor
and capacitor values to their ideal values. The value of C4 can also be increased to reduce the deviation at low
frequency.
A spectrum of the preamplifier output signal is shown in Figure 42 for a 10 mVRMS, 1-kHz input signal (1-VRMS
output). All distortion harmonics are below the preamplifier noise floor.
0.5 0
-20
Magnitude Deviation from Ideal (dB)
0 -40
-60
Amplitude (dBV)
-0.5 -80
-100
-1 -120
-140
-1.5 -160
10 100 1000 10000 10 100 1000 10000
C006 C010
Figure 41. Measured Deviation from Ideal RIAA Response Figure 42. Output Spectrum for a 10 mVRMS, 1 kHz Input
Signal
9 Power Supply Recommendations

The OPA164x are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.

OPA1641, OPA1642, OPA1644
10 Layout
10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed
information, see Circuit Board Layout Techniques, SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 43, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

OPA1641, OPA1642, OPA1644
10.2 Layout Example
VIN +
RG VOUT
RF
(Schematic Representation)
Place components
Run the input traces close to device and to
as far away from each other to reduce
the supply lines parasitic errors VS+
as possible RF
N/C N/C
RG
GND ±IN V+ GND
VIN +IN OUTPUT
Use low-ESR, ceramic

V± N/C
bypass capacitor
Use low-ESR, GND VOUT

VS±
ceramic bypass Ground (GND) plane on another layer
capacitor
Figure 43. OPA1641 Layout Example

OPA1641, OPA1642, OPA1644
11 Device and Documentation Support
11.1 Device Support

11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs

TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/, are analog solutions
created by TI’s precision analog applications experts and offer the theory of operation, component selection,
simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful
circuits.
11.1.1.3 WEBENCH® Filter Designer

WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets optimized filter designs to be created using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, the WEBENCH® Filter Designer allows
complete multistage active filter solutions to be designed, optimized, and simulated within minutes.
11.2 Documentation Support

11.2.1 Related Documentation
For related documentation see the following:
• Circuit Board Layout Techniques, SLOA089
• Op Amps for Everyone, SLOD006
• Operational amplifier gain stability, Part 3: AC gain-error analysis, SLYT383
• Operational amplifier gain stability, Part 2: DC gain-error analysis, SLYT374
• Using infinite-gain, MFB filter topology in fully differential active filters, SLYT343
• Op Amp Performance Analysis, SBOS054
• Single-Supply Operation of Operational Amplifiers, SBOA059
• Tuning in Amplifiers, SBOA067
• Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046

OPA1641, OPA1642, OPA1644
11.3 Related Links

Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
OPA1641 Click here Click here Click here Click here Click here
11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
SoundPlus, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Blu-ray is a trademark of Blu-Ray Disc Assocation.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA1641AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 O1641A
OPA1641AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 1641
OPA1641AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 1641
OPA1641AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 O1641A
OPA1642AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 1642
OPA1642AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 1642
OPA1644AIPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 O1644A
OPA1644AIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 O1644A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA1641, OPA1642 :
• Automotive: OPA1641-Q1, OPA1642-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1641AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA1642AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA1642AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA1642AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA1644AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA1644AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA1641AIDR SOIC D 8 2500 853.0 449.0 35.0
OPA1642AIDGKR VSSOP DGK 8 2500 853.0 449.0 35.0
OPA1642AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0
OPA1642AIDR SOIC D 8 2500 853.0 449.0 35.0
OPA1644AIDR SOIC D 14 2500 853.0 449.0 35.0
OPA1644AIPWR TSSOP PW 14 2000 853.0 449.0 35.0
TUBE

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA1641AID D SOIC 8 75 506.6 8 3940 4.32
OPA1642AID D SOIC 8 75 506.6 8 3940 4.32
OPA1644AID D SOIC 14 50 506.6 8 3940 4.32
OPA1644AIPW PW TSSOP 14 90 508 8.5 3250 2.8
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated

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Product Sample & Technical Tools & Support & Reference

Folder Buy Documents Software Community Design

OPA1641, OPA1642, OPA1644

OPA164x SoundPlus™ High-Performance, JFET-Input Audio Operational Amplifiers

Simplified Internal Schematic Extremely Stable Input Capacitance

Pre-Output Driver OUT 5.5

Changes from Revision C (December 2015) to Revision D Page

• Added TI Design .................................................................................................................................................................... 1

Changes from Revision B (August 2010) to Revision C Page

Changes from Revision A (April 2010) to Revision B Page

• Removed product-preview information for MSOP-8 package version of OPA1641............................................................... 1

2 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated

Product Folder Links: OPA1641 OPA1642 OPA1644

Changes from Original (December 2009) to Revision A Page

• Removed product-preview information for OPA1644 device packages throughout document.............................................. 1

Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Pin Configuration and Functions

OPA1641: D and DGK Packages

(1) NC denotes no internal connection.

Pin Functions: OPA1641

OPA1642: D and DGK Packages

Pin Functions: OPA1642

4 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated

Product Folder Links: OPA1641 OPA1642 OPA1644

OPA1644: D and PW Packages

Pin Functions: OPA1644

Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 5

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated

Product Folder Links: OPA1641 OPA1642 OPA1644

6.5 Electrical Characteristics

(1) Full power bandwidth = SR / (2π × VP), where SR = slew rate.

Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 7

Electrical Characteristics (continued)

8 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated

Product Folder Links: OPA1641 OPA1642 OPA1644

6.6 Typical Characteristics

Figure 5. Gain and Phase vs Frequency Figure 6. Closed-Loop Gain vs Frequency

Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Characteristics (continued)

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

Total Harmonic Distortion + Noise (dB)

Figure 7. THD+N Ratio vs Frequency Figure 8. THD+N Ratio vs Frequency

Intermodulation Distortion (dB)

G = -1, RL = 2kW CCIF Twin-Tone

Figure 9. THD+N Ratio vs Output Amplitude Figure 10. Intermodulation Distortion

Figure 11. Channel Separation vs Frequency Figure 12. No Phase Reversal

10 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated

Product Folder Links: OPA1641 OPA1642 OPA1644

Typical Characteristics (continued)

Time (100ns/div) Time (100ns/div)

Time (400ns/div) Time (400ns/div)

VOUT G = -10 G = -10

OPA1641 VOUT VOUT

Time (0.4ms/div) Time (0.4ms/div)

Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 11