LIC Lab Manual

SSM COLL EGE OF ENGINEERING, KOMARAPALAYAM – 638 183.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INDEX
List of Experiments:
DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS

1. Series and Shunt feedback amplifiers Frequency response, Input and output impedance
2. RC Phase shift oscillator and Wien Bridge Oscillator
3. Hartley Oscillator and Colpitts Oscillator
4. RC Integrator and Differentiator circuits using Op Amp
5. Clippers and Clampers
6. Instrumentation amplifier
7. Active low pass, High pass & Band pass filters
8. PLL Characteristics and its use as frequency multiplier, clock synchronization
9. R 2R ladder type D -A converter using Op -Amp
SIMULATION USING SPICE (Using Transistor):
1. Tuned Collector Oscillator
2. Twin - T Oscillator / Wein Bridge Oscillator
3. Double and Stagger tuned Amplifiers
4. Bistable Multivibrator
5. Schmitt Trigger circuit with Predictable hysteresis
6. Analysis of power amplifier
Voltage shunt feedback amplifier
MODEL GRAPH:
VOLTAGE SHUNT FEEDBACK AMPLIFIER
Exp.No: 1
Date:
AIM:
To design and construct and test the voltage shunt feedback amplifier for the given
specification and plot the frequency response.
APPARATUS REQUIRED:
S.NO. APPARATUS RANGE QUANTITY

1. Function Generator 3MHz 1
2. Power Supply (0-30)V 1
3. CRO 30MHz 1
4. Transistor BC107 1
5. Resistor 56KΩ 1
12.2 KΩ 1
10 KΩ 1
5.6 KΩ 1
2.2 KΩ 1
470Ω 1
6. Capacitor 47µF 1
4.7 µF 1
2 µF 1
7. Bread board --- 1
8. Connecting wires --- As required
DESIGN:
GIVEN SPECIFICATION:
AV=50, S=20, f1=100Hz, f2=750 KHz, RL=10KΩ, β=0.1, VCC=10V
i.) Selection of Transistor:

Vcc = 2Vcc and BC107 is selected.
ii.) Selection of RC:

iii.)
TABULATION: Vi=
S.No. Frequency(Hz) Output Voltage,Vo Gain= Vo/Vi Gain in dB
20log(Vo/Vi)
CALCULATION:
f1= f2= Bandwidth= f2 - f1= KHz

iv.) Selection of R1&R2:
v.) Selection of RE:
vi.) Selection of feedback ratio:
vii.) Selection of Re1&Re2:
viii.) Selection of C1&C2:

THEORY:
It is a transresistance amplifier with a Norton’s equivalent in its circuit and a Thevenin’s

equivalent in its output circuit. In this output voltage is proportional to the input signal current and
the proportionality factor is independent on the source and load resistance and zero output
resistance.
For practical transresistance amplifier Ri<<Rs and Ro << RL. This feedback amplifier reduces
the frequency distortion and noise and non-linear distortion. Also the gain with feedback
decreases.
Gain
Rmf = Rm/ (1+ βRm)
Input Resistance
Rif = Ri/ (1+ βRm)
Output Resistance
Rof = Ro / (1+ βRm)
PROCEDURE:
 Circuit connections are given as per the circuit diagram.

 The input voltage is set to 2V.
 The output voltage is measured from the CRO for various frequencies.
 Gain is calculated.
 Frequency response curve is plotted and from the plot bandwidth is calculated.
RESULT:
Thus the voltage shunt feedback amplifier was designed and the frequency Response was plotted.
From the graph, f1 & f2 are noted.
Bandwidth= KHz
CIRCUIT DIAGRAM:
CURRENT SERIES FEEDBACK AMPLIFIER

VCC=+12v
56K 2.2K
2uF
4.7uF
BC107
180
10K CRO
12.2K
270 47uF
MODEL GRAPH:
CURRENT SERIES FEEDBACK AMPLIFIER
Exp.No:2
Date:
AIM:
To design and construct and test the current series feedback amplifier for the given
specification and plot the frequency response.
APPARATUS REQUIRED:

3. CRO 30MHz 1
12.2 KΩ 1
10 KΩ 1
2.2 KΩ 1
270Ω 1
180Ω 1
4.7 µF 1
2 µF 1
DESIGN:
AV=50, S=20, f1=100Hz, f2=750 KHz, RL=10KΩ, β=0.1, VCC=10V
i. Selection of Transistor:
Vcc = 2Vcc and BC107 is selected.
ii. Selection of RC:
iii.Selection of R1&R2:
iv.Selection of R1&R2:
v.Selection of RE:
vi.Selection of RE1& RE2:
vii.Selection of C1&C2:
viii.Feedback ratio:
TABULATION: Vi =
20log(Vo/Vi)
CALCULATION:
f1=
f2=
Bandwidth= f2 - f1
= KHz
THEORY:
The common emitter circuit with unbypassed RE is an example of current series feedback. In
configuration, resistor RE is common to base and emitter input circuit so as well as collector to
emitter output circuit and input current Ib as well as output current Ic both flow through The voltage
drop across RE, VE=(Ib+Ic)RE=IeRE=IcRE=IoRE.This voltage drop shows the output current.Io is being
sampled and it is converted to voltage by feedback network at input side voltage Vf is subtracted from
Vo to perpendicular Vi.Therefore, feedback applied in series voltage feedback(current).
PROCEDURE:

 The input voltage is set to 2V.
 The output voltage is measured from the CRO for various frequencies.
 Gain is calculated.
 Frequency response curve is plotted and from the plot bandwidth is calculated.
RESULT:
Thus the current series feedback amplifier was designed and the frequency response was
plotted. From the graph, f1 & f2 are noted.
Bandwidth= KHz
CIRCUIT DIAGRAM:
RC PHASE SHIFT OSCILLATOR
VCC=+5v
56K 2.2K
0.01uF 0.01uF 0.01uF
BC107
6.8K 6.8K 2.2K
12.2K CRO
470 47uF
MODEL GRAPH:
TABULATION:
Output waveform Amplitude(V) Time period(ms)
CALCULATION:
Obtained frequency of oscillation, fo= 1 / T = Hz

RC PHASE SHIFT OSCILLATOR
Exp.No:3
Date:
AIM:
To design and construct and test the RC phase shift oscillator for the given specification and
plot the output waveform.
APPARATUS REQUIRED:

2. CRO 30MHz 1
12.2 KΩ 1
6.8 KΩ 2
3.3 KΩ 1
2.2 KΩ 1
470Ω 1
0.01 µF 3
DESIGN:
AV=50, S=20, fo=1 KHz, β=0.1, VCC=10V
BC107 is selected.
iii.) Selection of R1&R2:
iv.) Selection of RE:
v.) Selection of CE:
vi.) Selection of R’:

THEORY:
RC phase shift oscillator basically consists of an amplifier and a feedback network

consisting of resistors and capacitors arranged in ladder fashion. Hence, such an oscillator is called
ladder type RC phase shift oscillator.
Transistorised RC phase shift oscillator which uses a CE single stage amplifier a phase shifting
network consisting of three identical RC sections. The output of the feedback network gets loaded
due to low input resistance of a transistor. Hence, an emitter follower stage can be used before the
common emitter amplifier stage .The voltage shunt feedback denoted by R3 connected in series
with amplifier input resistance.
Output of the amplifier is given as an input of the feedback network while the output of
the feedback network is given as an input to amplifier.
R = hie+R3
If the resistance R1&R2 are not neglected, then
Ri’= R1 II R2 II hie
Frequency of oscillation for the RC phase shift oscillator is given by,
fo= 1/ [2πRC√ (4k+6)]
PROCEDURE:

 Power supply is given to the circuit.
 Amplitude and Time period of the output waveform is noted from the CRO
 Frequency of oscillation is calculated.
 Output waveform is plotted in the graph.
RESULT:
Thus the RC phase shift oscillator is designed and tested and the time response was plotted.
Designed frequency of oscillation = 1 KHz
Obtained frequency of oscillation =

CIRCUIT DIAGRAM:
WEIN BRIDGE OSCILLATOR
MODEL GRAPH:
TABULATION:
Output waveform Amplitude(V) Time period(µs)
CALCULATION:
Obtained frequency of oscillation, fo= 1 / T
= MHZ
Exp.No:4
Date:
AIM:
To design and construct and test the Wein bridge oscillator for the given specification and
plot the output waveform.
APPARATUS REQUIRED:

2. CRO 30MHz 1
4. Resistor 15K 2
100K 3
22K,12K,4K,1K,500,20K,1.5K,220K 1
5. Capacitor 0.01 µF 5
DESIGN:
Frequency of oscillation for the Wein bridge oscillator is given by,
fo= 1/ [2πRC]
=1KHz
C=0.01µF
R= 1/ [2πfoC]
THEORY:
Wein Bridge Oscillator uses a non inverting amplifier and hence does not produce any phase
shift during amplifier stage as total phase shift req. is 0. In wein bridge oscillator type no phase
shift is necessary through Feedback. Thus the total phase shift around a loop is 0.
PROCEDURE:

 Amplitude and Time period of the output waveform is noted from the CRO.
RESULT:
Thus the Wein bridge oscillator is designed and tested and the time response was
plotted.
CIRCUIT DIAGRAM:
HARTLEY OSCILLATOR
VCC=+5v
56K 2.2K
0.1uF
0.1uF
BC107
12.2K
470 10µf CRO
L1 L2
1 2 1 2
(0 mH - 1H)) (0 mH - 1H))
100pF
MODEL GRAPH:
TABULATION:
CALCULATION:
= MHz
HARTLEY OSCILLATOR
Exp.No:5
Date:
AIM:
To design and construct and test the Hartley oscillator for the given specification and plot
the output waveform.
APPARATUS REQUIRED:

2. CRO 30MHz 1
3. Transistor 2N3666 1
Or
BC107
12.2 KΩ 1
2.2 KΩ 1
470Ω 1
0.1 µF 2
100pF 1
6. Decade Inductance Box (0 mH – 1H) 2
DESIGN:
AV=50, S=20, fo=150 KHz, β=0.1, VCC=10V

BC107 is selected.
vi.) Selection of L1,L2&C:

THEORY:
A LC oscillator which uses two inductive reactances and one capacitive reactance in its
feedback network is Hartley oscillator. The amplifier stage uses transistor as an active device in
common emitter configuration. The resistances R1&R2 are the biasing resistances. The RFC is the
radio frequency choke. Its reactance value is very high frequencies, hence it can be treated as open
circuit while for dc conditions, the reactance is zero hence causes no problem for dc capacitors.
Frequency of oscillation for the Hartley oscillator is given by,
fo= 1/ [2π√ (LeqC)]
PROCEDURE:

RESULT:
Thus the Hartley oscillator is designed and tested and the time response was plotted.
Designed frequency of oscillation = 150 MHz
Obtained frequency of oscillation = MHz

CIRCUIT DIAGRAM:
VCC=+5V
56K 2.2K
0.1uF
BC107
12.2K
470 10uF
CRO
100pF 100pF
1 2
(0 mH - 1 H)
MODEL GRAPH
TABULATION:
CALCULATION:
= MHz
COLPITT’S OSCILLATOR
Exp.No:6
Date:
AIM:
To design and construct and test the Colpitt’s oscillator for the given specification and plot
the output waveform.
APPARATUS REQUIRED:

2. CRO 30MHz 1
3. Transistor 2N3666 1
Or
BC107
12.2 KΩ 1
2.2 KΩ 1
470Ω 1
0.1 µF 1
100pF 2
6. Decade Inductance Box (0 mH – 1H) 1
DESIGN:
AV=50, S=20, fo=150 KHz, β=0.1, VCC=10V

BC107 is selected.
vi.) Selection of C1,C2&L:

THEORY:
A LC oscillator which uses two inductive reactances and one capacitive reactance in its
feedback network is Colpitt’s oscillator. The amplifier stage uses transistor as an active device in
common emitter configuration. The resistances R1&R2 are the biasing resistances. The RFC is the
radio frequency choke. Its reactance value is very high frequencies, hence it can be treated as open
circuit while for dc conditions, the reactance is zero hence causes no problem for dc capacitors.
Frequency of oscillation for the Colpitt’s oscillator is given by,
fo= 1/ [2π√ (CeqL)]
PROCEDURE:

RESULT:
Thus the Colpitts oscillator is designed and tested and the time response was
plotted.
Designed frequency of oscillation= 100 MHz
Obtained frequency of oscillation= MHz

CIRCUIT DIAGRAM:
Differentiator:
Tabulation : Amplitude Frequency Theoretical Practical

Input
Sine
Square
INTEGRATOR AND DIFFERENTIATOR

Exp.No:7
Date:
AIM: To design an Integrator and Differentiator circuit using Op-amp.
APPARATUS REQUIRED:

2. CRO 30MHz 1
3. Op-amp μA741 1
10 KΩ 3
0.1 µF 1
100pF 2
6. 1
Theory:
Differentiator:
An op-amp differentiator or a differentiating amplifier is a circuit configuration which
produces output voltage amplitude that is proportional to the rate of change of the applied input
voltage.A differentiator with only RC network is called a passive differentiator, whereas a
differentiator with active circuit components like transistors and operational amplifiers is called an
active differentiator. Active differentiators have higher output voltage and much lower output
resistance than simple RC differentiators. An op-amp differentiator is an inverting amplifier,
which uses a capacitor in series with the input voltage. Differentiating circuits are usually designed
to respond for triangular and rectangular input waveforms. For a sine wave input, the output of a
differentiator is also a sine wave, which is out of phase by 180o with respect to the input (cosine
wave).
Integrator:
Tabulation : Amplitude Frequency Theoretical Practical

Input
Sine
Square
MODEL GRAPH:
Differentiators have frequency limitations while operating on sine wave inputs; the circuit
attenuates all low frequency signal components and allows only high frequency components at the
output. In other words, the circuit behaves like a high-pass filter.
Op-amp differentiating and integrating circuits are inverting amplifiers, with appropriately placed
capacitors. Integrator circuits are usually designed to produce a triangular wave output from a
square wave input. Integrating circuits have frequency limitations
INTEGRATOR:
In an integrating circuit, the output is the integration of the input voltage with respect to
time. A passive integrator is a circuit which does not use any active devices like op-amps or
transistors.
An integrator circuit which consists of active devices is called an Active integrator. An active
integrator provides a much lower output resistance and higher output voltage than is possible with
a simple RC circuit.
Op-amp differentiating and integrating circuits are inverting amplifiers, with appropriately placed
capacitors. Integrator circuits are usually designed to produce a triangular wave output from a
square wave input. Integrating circuits have frequency limitations while operating on sine wave
input signals.
PROCEDURE:
Differentiator:
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply sine wave at the input terminals of the circuit using function Generator.
4. Connect channel-1 of CRO at the input terminals and channel-2 at the output terminals.
5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase shifted from the
sine wave input) and note down the position, the amplitude and the time period of VIN & VO
6. Now apply the square wave as input signal.
7. Observe the output of the circuit on the CRO which is a spike wave and note down the position,
the amplitude and the time period of VIN & VO
8. Plot the output voltages corresponding to sine and square wave inputs.
Integrator:
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply sine wave at the input terminals of the circuit using function Generator.
4. Connect channel-1 of CRO at the input terminals and channel-2 at the output terminals.
5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase shifted from the
sine wave input) and note down the position, the amplitude and the time period of Vin & Vo.
6. Now apply the square wave as input signal.
7. Observe the output of the circuit on the CRO which is a triangular wave and note down the
position, the amplitude and the time period of Vin &Vo.
8. Plot the output voltages corresponding to sine and square wave inputs.
Result: Thus the Differentiator and Integrator circuits have been constructed and the output was
verified successfully.
CIRCUIT DIAGRAM:
NEGATIVE CLIPPER
IN4148
1 2
Vin 6.8K CRO
POSITIVE CLIPPER
IN4148
2 1
Vin 6.8K CRO

CLIPPER AND CLAMPER
Exp.No:8
Date:
AIM:
To construct clipper and clamper circuits and plot the output waveform.
APPARATUS REQUIRED:

2. CRO 30MHz 1
3. Diode IN4148 1
4. Resistor 6.8KΩ 1
10 KΩ 1
5. Capacitor 1µF 1
THEORY:
CLIPPER:
The circuits which are used to clip off unwanted portion of the waveform without distorting
the remaining part of the waveform are called clippers. The half wave rectifier is the best and
simplest type of clipper circuit.
There are two types of clippers:
 Positive clipper
 Negative clipper
POSITIVE CLIPPER
A clipper which clips off the positive part of the input is called positive clipper. For
positive half cycle of input V1 > 0V, and diode is reverse biased. Hence it acts as a open circuit and
Vo=0. For negative half cycle of input, V1 < 0V and diode conducts. Assuming ideal diode and the
output voltage is same as the input voltage. Thus entire negative half cycle is available at the
output.
NEGATIVE CLAMPER
1uF
Vin IN4148 10K CRO

2
POSITIVE
1uF
CLAMPER
Vin IN4148 10K CRO

1
MODEL GRAPH:
NEGATIVE CLIPPER
A clipper which clips off the negative part of input is called the negative clipper. For
positive half cycle V1 > 0V and diode conduct. Assuming ideal diode the output is same as the
input voltage. Thus entire positive half cycle is available at the output.
CLAMPERS:
The circuits which are used to add a dc level as per the requirements to the ac output signal
is called the clamper circuits. The basic elements of the clamper circuits are diode, capacitor and
resistor. This clamper circuit is also called as the dc restorer or dc inserter circuits
By changing the orientation of the diode in negative clamper, the positive clamper is
achieved.
Vo=Vm for Vi=0
Vo=2Vm for Vi=Vm
Vo=0 for Vi=0
PROCEDURE:

 Input is given to the circuit and the output for the clipper and clamper is noted in the CRO.
CLIPPER
NEGATIVE CLIPPER
waveform Amplitude(V) Time period(ms)
POSITIVE CLIPPER
NEGATIVE CLAMPER
Clamper:
POSITIVE CLAMPER

RESULT:
Thus the clipper and clamper circuits have been constructed and the output
was verified successfully.

INSTRUMENTATION AMPLIFIER
Exp.No:9
Date:
AIM: To design an instrumentation amplifier and obtain the output for various gain.
APPARATUS REQUIRED:
2. CRO 30MHz 1
3. Op-amp μA741 1
4. Resistor 1KΩ 2
10 KΩ,20KΩ 3
Theory :
Instrumentation amplifier is a kind of differential amplifier with additional input buffer

stages. The addition of input buffer stages makes it easy to match (impedance matching) the
amplifier with the preceding stage. Instrumentation are commonly used in industrial test and
measurement application. The instrumentation amplifier also has some useful features like low
offset voltage, high CMRR (Common mode rejection ratio), high input resistance, high gain etc.
The two non-inverting amplifiers form a differential input stage acting as buffer amplifiers with a
gain of 1 + 2R2/R1 for differential input signals and unity gain for common mode input signals.
Since amplifiers A1 and A2 are closed loop negative feedback amplifiers, we can expect the
voltage at Va to be equal to the input voltage V1. Likewise, the voltage at Vb to be equal to the
value at V2.
As the op-amps take no current at their input terminals (virtual earth), the same current
must flow through the three resistor network of R2, R1 and R2 connected across the op-amp
outputs. This means then that the voltage on the upper end of R1 will be equal to V1and the
voltage at the lower end of R1 to be equal to V2.
The voltage output from the differential op-amp A3 acting as a subtractor, is simply the
difference between its two inputs ( V2 – V1 ) and which is amplified by the gain of A3which may be
one, unity, (assuming that R3 = R4). Then we have a general expression for overall voltage gain of
the instrumentation amplifier circuit as:
CIRCUIT DIAGRAM
Tabulation:
Theoretical Practical
Amplitude Time Amplitude Time
INPUT
OUTPUT
Model Graph
Procedure:
1. Connections are given as per the circuit diagram.
2. Input signal is connected to the circuit from the signal generator.
3. The input and output signals of the circuit observed from the dual channels 1 and 2 of the CRO.
4. Suitable voltage sensitivity and time-base on CRO is selected.
5. Change the gain setting resistor value and observe the output.
Result: Thus the Instrumentation Amplifier circuits have been constructed and the output
was verified successfully.

Low Pass filter Circuit:
Output:
LOW PASS, HIGH PASS AND BAND PASS FILTERS
Exp.No:10
Date:
AIM: To design Low pass, High pass and Band pass active filters using Op-amp and obtain
frequency response.
APPARATUS REQUIRED:
2. CRO 30MHz 1
3. Function Generator
4. Op-amp μA741 1
5. Resistor 1KΩ 2
10 KΩ,20KΩ 3
Theory:
A filter is often used in electronic circuits to block (or allow) a select frequency to the circuit. An
op-amp is used to design a filters, so it is called Active filters. There are Four types active filters
like Low pass, High pass, band pass and band stop . A low pass filter is used in circuits that only
allow low frequencies to pass through (below the Cutoff frequency). It is often used to block high
frequencies and AC current in a circuit.A high pass filter is used in circuits that only require high
frequencies to operate (above the cut off frequency). It blocks most low frequencies & DC
component.A band pass filter is a combination of a high pass and a low pass filter. It allows only a
select range of frequencies to pass through. It is designed such a way that the cut off frequency of
the low pass filter is higher than the cut off frequency of the high pass filter, hence allowing only a
select range of the frequencies to pass through.
Procedure:
1. Connections are given as per the circuit diagram.
2. Input signal is connected to the circuit from the signal generator.
3. The input and output signals of the filter channels 1 and 2 of the CRO are connected.
4. Suitable voltage sensitivity and time-base on CRO is selected.
5. The correct polarity is checked.
6. The above steps are repeated for second order filter.
Low Pass Filter
Tabulation
20log(Vo/Vi)
High Pass Filter Circuit:
Model Graph :
High Pass Filter:

The high pass filter is the complement of the low pass filter. Thus the high pass filter can be
obtained by interchanging R and C in the circuit of low pass configuration. A high pass filter
allows only frequencies above a certain bread point to pass through and at terminates the low
frequency components. The range of frequencies beyond its lower cut off frequency fL is called
stop band.
Band Pass Filter Circuit:
BPF:-
The BPF is the combination of high and low pass filters and this allows a specified range of
frequencies to pass through. It has two stop bands in range of frequencies between 0 to fL and
beyond fH. The band b/w fL and fHis called pass band. Hence its bandwidth is (fL-fH). This filter
has a maximum gain at the resonant frequency (fr) which is defined as
High Pass Filter
Tabulation
20log(Vo/Vi)
Band Pass Filter :
Model Graph
Band Pass Filter
Tabulation
20log(Vo/Vi)
Result: Result: Thus the Low pass, High pass and Band pass active filters using Op-amp have
been constructed and frequency response was obtained.
CIRCUIT DIAGRAM
Pin Diagram
PLL CHARACTERISTICS AND ITS USE AS FREQUENCY MULTIPLIER, CLOCK

SYNCHRONIZATION.
Exp.No:11
Date:
AIM: 1. To study the PLL characteristics.

2. To use PLL as frequency multiplier and clock synchronization.
APPARATUS REQUIRED:
2. CRO 30MHz 1
4. PLL IC565 1
5. Resistor 10 KΩ 2
0.01 µF 2
1 µF 1
Theory:
The PLL IC 565 is usable over the frequency range 0.1 Hz to 500 kHz. It has highly stable centre
frequency and is able to achieve a very linear FM detection. The output of VCO is capable of
producing TTL compatible square wave. The dual supply is in the range of ±6V to ±12V. The IC
can also be operated from single supply in the range 12V to 24V
The phase locked loop consists of a phase detector, a voltage control oscillator and, in between
them, a low pass filter is fixed. The input signal „Vi‟ with an input frequency „Fi‟ is conceded by
a phase detector. Basically the phase detector is a comparator which compares the input frequency
fi through the feedback frequency fo. The output of the phase detector is (fi+fo) which is a DC
voltage. The out of the phase detector, i.e., DC voltage is input to the low pass filter (LPF); it
removes the high frequency noise and produces a steady DC level, i.e., Fi-Fo. The Vf is also a
dynamic characteristic of the PLL.
The following figure shows the pin-out and the internal block schematic of PLL IC LM 565.
Procedure:
p the circuit stage by stage on the breadboard
-p ,1Khz square wave

Result: Thus the PLL characteristic was studied and PLL as frequency multiplier and clock
synchronization output was verified Successfully..
To design 3 bit R-2R Digital to Analog converter to convert analog voltage of binary bit 100.
R-2R LADDER TYPE D- A CONVERTER USING OP-AMP.
Exp.No:12
Date:
AIM: To design R-2R Ladder Type D- A Converter using Op-amp and observe the output.
APPARATUS REQUIRED :

2. CRO 30MHz 1
4. PLL IC565 1
5. Resistor 5KΩ,2. 2
Theory:
A digital-to-analog converter (DAC, D/A, D2A or D-to-A) is a circuit that converts digital data
(usually binary) into an analog signal (current or voltage). One important specification of a DAC is
its resolution. It can be defined by the numbers of bits or its step size. Wide range of resistors used
Weighted Resistor type DAC. This can be avoided by using R-2R ladder type DAC where only
two values of resistors are required.
Basic Block diagram of DAC.
If binary bit 011 :
Tabulation: Vref = -5V

D1 D2 D3 Theoretical Practical
V0 V0
0 0 0
0 0 1
0 1 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Procedure:
-5V ref if bit=1.
Result: Thus the R-2R Ladder Type D- A Converter using Op-amp was designed and the output
was verified successfully..
TUNED COLLECTOR OSCILLATOR:
MODEL GRAPH:
TUNED COLLECTOR OSCILLATOR
Exp.No:13
Date:
AIM:
To simulate Tuned Collector Oscillator circuit using PSPICE.
COMPONENTS & EQUIPMENTS REQUIRED:
S.No Components / Software
1 Personal Computer
2 PSPICE Software
THEORY:
Tuned collector oscillation is a type of transistor LC oscillator where the tuned circuit
(tank) consists of a transformer and a capacitor is connected in the collector circuit of the
transistor. Tuned collector oscillator is of course the simplest and the basic type of LC oscillators.
The tuned circuit connected at the collector circuit behaves like a purely resistive load at resonance
and determines the oscillator frequency.The common applications of tuned collector oscillator are
RF oscillator circuits, mixers, frequency demodulators, signal generators etc.
PROCEDURE:
1. Open Orcad-> Capture CIS ->File->New-> Project

2. Place->Part , select the required components for the circuit to be designed
from the library.
3. Select R,C components from the Analog.olb and edit the values as per the
circuit diagram.
4. Select Transistor Q2N2222 from bipolar.olb
5. For the DC supply select VDC from source.olb and edit the value as 12V for
VCC
6. Connect the placed components by using the option Place->wire.
7. Pspice -> New Simulation profile -> name->create
8. Analysis ->Time Domain
9. Enter Run to time and maximum step size value.
10. Pspice-> Run.
11. Plot->Add plot to window, two plot windows will be displayed.
12. Keep the cursor in the first plot window , Trace-> Add Trace -
V(Q1:b),V(Q2:b).
13. Keep the cursor in the second plot window ,Trace-> Add Trace –
>(Q1:c),V(Q2:c).
RESULT:
Thus the given tuned collector oscillator circuit was simulated using PSPICE tool and the
output graphs were obtained.
CIRCUIT DIAGRAM:
TWIN-T OSCILLATOR
MODEL GRAPH:
TWIN-T OSCILLATOR
Exp.No:14
Date:
AIM:
To simulate Twin – T Oscillator circuit using PSPICE.
1 Personal Computer
2 PSPICE Software
THEORY:
The "Twin-T" oscillator as it uses two "T" RC circuits operated in parallel. One circuit is
an R-C-R "T" which acts as a low-pass filter. The second circuit is a C-R-C "T" which operates as
a high-pass filter. Together, these circuits form a bridge which is tuned at the desired frequency of
oscillation. The signal in the C-R-C branch of the Twin-T filter is advanced, in the R-C-R -
delayed, so they may cancel one another for frequency 1
f = ----------- x = 2
2πRC
if it is connected as a negative feedback to an amplifier, and x>2, the amplifier becomes an
oscillator.
PROCEDURE:

2. Place->Part , select the required components for the circuit to be designed from
the library.
3. Select R,C components from the Analog.olb and edit the values as per the circuit
diagram.
5. For the DC supply select VDC from source.olb and edit the value as 12V for VCC
10. Pspice-> Run.
12. Keep the cursor in the first plot window , Trace-> Add Trace ->V(Q1:b),V(Q2:b).
13. Keep the cursor in the second plot window ,Trace-> Add Trace ->(Q1:c),V(Q2:c
RESULT:
Thus the given Twin T oscillator circuit was simulated using PSPICE tool and the output
graphs were obtained.
CIRCUIT DIAGRAM:
MODEL GRAPH:
Exp.No:15
Date:
AIM:
To simulate Wein Bridge Oscillator circuit using PSPICE.
1 Personal Computer
2 PSPICE Software
THEORY:
A Wien bridge oscillator is a type of electronic oscillator that generates sine waves. It can
generate a large range of frequencies. The oscillator is based on a bridge circuit originally
developed by Max Wien in 1891 for the measurement of impedances.[1] The bridge comprises
four resistors and two capacitors. The oscillator can also be viewed as a positive gain amplifier
combined with a bandpass filter that provides positive feedback. Automatic gain control,
intentional non-linearity and incidental non-linearity limit the output amplitude in various
implementations of the oscillator.The condition that R1=R2=R and C1=C2=C, the frequency of
oscillation is given by,
1
f = -----------
2πRC
and the condition of stable oscillation is given by,
Rb = Rf / 2
PROCEDURE:
from the library.
7. Pspice-> Run.
8. Plot->Add plot to window.
9. Keep the cursor in the first plot window , Trace-> Add the required Trace
RESULT:
Thus the given Wein Bridge oscillator circuit was simulated using PSPICE tool and output
graphs were obtained.
CIRCUIT DIAGRAM:
DOUBLE AND STAGGER TUNED AMPLIFIER
MODEL GRAPH:
DOUBLE AND STAGGER TUNED AMPLIFIER

Exp.No:16
Date:
AIM:
To simulate the Double Tuned and Stagger tuned amplifier using PSPICE.
1 Personal Computer
2 PSPICE Software
THEORY:
DOUBLE-TUNED AMPLIFIER :
A double-tuned amplifier is a tuned amplifier with transformer coupling between the
amplifier stages in which the inductances of both the primary and secondary windings are tuned
separately with a capacitor across each. The scheme results in a wider bandwidth and steeper skirts
than a single tuned circuit would achieve.
There is a critical value of transformer coupling coefficient at which the frequency response of
the amplifier is maximally flat in the pass band and the gain is maximum at the resonant
frequency. Designs frequently use a coupling greater than this (over-coupling) in order to achieve
an even wider bandwidth at the expense of a small loss of gain in the centre of the pass band.
Cascading multiple stages of double-tuned amplifiers results in a reduction of the bandwidth

of the overall amplifier. Two stages of double-tuned amplifier have 80% of the bandwidth of a
single stage. An alternative to double tuning that avoids this loss of bandwidth is staggered tuning.
Stagger-tuned amplifiers can be designed to a prescribed bandwidth that is greater than the
bandwidth of any single stage. However, staggered tuning requires more stages and has lower gain
than double tuning.
STAGGER TUNED AMPLIFIER:
Staggered tuning is a technique used in the design of multi-stage tuned amplifiers whereby
each stage is tuned to a slightly different frequency. In comparison to synchronous tuning (where
each stage is tuned identically) it produces a wider bandwidth at the expense of reduced gain.
PROCEDURE:
the library.
7. Pspice-> Run.
8. Plot->Add plot to window.
9. Keep the cursor in the first plot window , Trace-> Add the required Trace
RESULT:
Thus the given Double tuned and stagger tuned amplifier circuit was simulated using PSPICE
tool and output were obtained.
cIRCUIT DIAGRAM:
BISTABLE MULTIVIBRATOR
MODEL GRAPH:
BISTABLE MULTIVIBRATOR
Exp.No:17
Date:
AIM:
To simulate the Bistable multivibrator using PSPICE.
1 Personal Computer
2 PSPICE Software
THEORY:
The Bistable Multivibrator is another type of two state device similar to the Monostable
Multivibrator we looked at in the previous tutorial but the difference this time is that both states are
stable.
PROCEDURE:
from the library.
3. Select R,C components from the Analog.olb and edit the values as per the
circuit diagram.
5. For the DC supply select VDC from source.olb and edit the value as 12V for VCC

10. Pspice-> Run.
12. Keep the cursor in the first plot window , Trace-> Add Trace -
>V(Q1:b),V(Q2:b).
13. Keep the cursor in the second plot window ,Trace-> Add Trace -
>(Q1:c),V(Q2:c).
RESULT:
Thus the given Bistable multivibrator circuit was simulated using PSPICE tool and output
were obtained.
CIRCUIT DIAGRAM:
SCHMITT TRIGGER
MODEL GRAPH:
SCHMITT TRIGGER
Exp.No:18
Date:
AIM:
To simulate the Schmitt trigger using PSPICE.
1 Personal Computer
2 PSPICE Software
THEORY:
Schmitt trigger is a comparator circuit with hysteresis implemented by applying positive
feedback to the noninverting input of a comparator or differential amplifier. It is an active circuit
which converts an analog input signal to a digital output signal. The circuit is named a "trigger"
because the output retains its value until the input changes sufficiently to trigger a change. In the
non-inverting configuration, when the input is higher than a chosen threshold, the output is high.
When the input is below a different (lower) chosen threshold the output is low, and when the input
is between the two levels the output retains its value. This dual threshold action is called hysteresis
and implies that the Schmitt trigger possesses memory and can act as a bistable multivibrator (latch
or flip-flop). There is a close relation between the two kinds of circuits: a Schmitt trigger can be
converted into a latch and a latch can be converted into a Schmitt trigger.
Schmitt trigger devices are typically used in signal conditioning applications to remove noise
from signals used in digital circuits, particularly mechanical contact bounce. They are also used in
closed loop negative feedback configurations to implement relaxation oscillators, used in function
generators and switching power supplies.
PROCEDURE:
1. Open Orcad-> Capture CIS ->File->New-> Project.
the library.
diagram.
4. Select Transistor Q2N2222 from bipolar.olb.

VCC.
7. Pspice -> New Simulation profile -> name->create.
8. Analysis ->Time Domain.

10. Pspice-> Run.
>(Q1:c),V(Q2:c).
RESULT:
Thus the given Schmitt trigger circuit was simulated using PSPICE tool and output were
obtained.
CIRCUIT DIAGRAM:
CLASS C POWER AMPLIFIER
MODEL GRAPH:
ANALYSIS OF POWER AMPLIFIER
Exp.No:19
Date:
AIM:
To simulate the analysis of power amplifier using PSPICE.
1 Personal Computer
2 PSPICE Software
THEORY:
The main function of the power amplifier, which are also known as a “large signal amplifier”
is to deliver power, which is the product of voltage and current to the load. Basically a power
amplifier is also a voltage amplifier the difference being that the load resistance connected to the
output is relatively low, for example a loudspeaker of 4Ω or 8Ω resulting in high currents flowing
through the collector of the transistor.
Because of these high load currents the output transistor(s) used for power amplifier output
stages such as the 2N3055 need to have higher voltage and power ratings than the general ones
used for small signal amplifiers such as the BC107. Since we are interested in delivering maximum
AC power to the load, while consuming the minimum DC power possible from the supply we are
mostly concerned with the “conversion efficiency” of the amplifier.
The most commonly used type of power amplifier configuration is the Class C Amplifier.
The Class A amplifier is the simplest form of power amplifier that uses a single switching
transistor in the standard common emitter circuit configuration as seen previously to produce an
inverted output. The transistor is always biased “ON” so that it conducts during one complete
cycle of the input signal waveform producing minimum distortion and maximum amplitude of the
output signal.
PROCEDURE:
1. Open Orcad-> Capture CIS ->File->New-> Project.
the library.
diagram.
4. Select Transistor Q2N2222 from bipolar.olb.

VCC.
7. Pspice -> New Simulation profile -> name->create.
8. Analysis ->Time Domain.

10. Pspice-> Run.
>(Q1:c),V(Q2:c).
RESULT:
Thus the given analysis of power amplifier circuit was simulated using PSPICE tool and output
were obtained.

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SSM COLL EGE OF ENGINEERING, KOMARAPALAYAM – 638 183.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS

Voltage shunt feedback amplifier

VOLTAGE SHUNT FEEDBACK AMPLIFIER

S.NO. APPARATUS RANGE QUANTITY

AV=50, S=20, f1=100Hz, f2=750 KHz, RL=10KΩ, β=0.1, VCC=10V

i.) Selection of Transistor:

ii.) Selection of RC:

S.No. Frequency(Hz) Output Voltage,Vo Gain= Vo/Vi Gain in dB

f1= f2= Bandwidth= f2 - f1= KHz

iv.) Selection of R1&R2:

v.) Selection of RE:

vi.) Selection of feedback ratio:

vii.) Selection of Re1&Re2:

viii.) Selection of C1&C2:

It is a transresistance amplifier with a Norton’s equivalent in its circuit and a Thevenin’s

Rmf = Rm/ (1+ βRm)

Rif = Ri/ (1+ βRm)

Rof = Ro / (1+ βRm)

 Circuit connections are given as per the circuit diagram.

CURRENT SERIES FEEDBACK AMPLIFIER

CURRENT SERIES FEEDBACK AMPLIFIER

S.NO. APPARATUS RANGE QUANTITY

AV=50, S=20, f1=100Hz, f2=750 KHz, RL=10KΩ, β=0.1, VCC=10V

ii. Selection of RC:

vi.Selection of RE1& RE2:

S.No. Frequency(Hz) Output Voltage,Vo Gain= Vo/Vi Gain in dB

 Circuit connections are given as per the circuit diagram.

RC PHASE SHIFT OSCILLATOR

0.01uF 0.01uF 0.01uF

6.8K 6.8K 2.2K

Output waveform Amplitude(V) Time period(ms)

Obtained frequency of oscillation, fo= 1 / T = Hz

RC PHASE SHIFT OSCILLATOR

S.NO. APPARATUS RANGE QUANTITY

AV=50, S=20, fo=1 KHz, β=0.1, VCC=10V

i.) Selection of Transistor:

ii.) Selection of RC:

iii.) Selection of R1&R2:

iv.) Selection of RE:

v.) Selection of CE:

vi.) Selection of R’:

RC phase shift oscillator basically consists of an amplifier and a feedback network

If the resistance R1&R2 are not neglected, then

Frequency of oscillation for the RC phase shift oscillator is given by,

fo= 1/ [2πRC√ (4k+6)]

 Circuit connections are given as per the circuit diagram.

Designed frequency of oscillation = 1 KHz

Obtained frequency of oscillation =

WEIN BRIDGE OSCILLATOR

Output waveform Amplitude(V) Time period(µs)

Obtained frequency of oscillation, fo= 1 / T

WEIN BRIDGE OSCILLATOR

S.NO. APPARATUS RANGE QUANTITY

Frequency of oscillation for the Wein bridge oscillator is given by,

 Circuit connections are given as per the circuit diagram.

Output waveform Amplitude(V) Time period(µs)