What Is DFT in VLSI
What Is DFT in VLSI
What Is DFT in VLSI
Design-for-testability (DFT)
Why DFT?
To make design testable and to find the physical defect in the silicon chip
after manufacturing.
Attempt to reduce the high cost in time and effort required to generate test
vector sequences for VLSI circuits.
DFT Techniques
DFT techniques are broadly classified into two types:
Ad-hoc techniques
These are a collection of techniques or set of rules (do’s and don’ts) in the chip
design process learned from design experience to make design testability more
comfortable to accomplish.
Advantages
Test vector generation is simplified
Very easy to implement, no design rule or constraints and area overhead is
very less.
Drawbacks
Are not always reusable, since each design has its specific requirements and
testability problems.
It doesn’t guarantee high testability levels regardless of the circuit.
Not systematic enough to enable a uniform approach to testable circuit
design.
Structured techniques
In this technique, extra logic and signals are added to the circuit to allow the test
according to some predefined procedure.
Advantage
In contrast to Ad-hoc, structured DFT implies that the same design approach can
always be used and assure good testability levels, regardless of the circuit function.
This technique is the only solution to modern world DFT problems.
Disadvantage
Usually consists of accepting that some design rules are enforced and that
additional silicon area and propagation delays are tolerated.
Examples
Following are a few examples of structured DFT which we will cover extensively
in future lessons:
Scan Path
Partial Scan
Level Sensitive Scan
BIST
Boundary Scan
Hence the circuit now has two operation modes: Normal mode and Test mode.
Normal Mode
In normal mode, Scan Flip-Flops are configured to
perform capture operation.
Test Mode
In test mode, the scan flip-flops are first configured to
perform shift operation so we can shift-in our test pattern.
And then the scan flip-flops are configured to capture the response from the
logic.
Finally, we configure the flip-flops to perform the shift-out operation so
that we can observe the values in the Scan flip-flops.
Purpose of testing using scan: Scan testing is carried out for various
reasons, two most prominent of them are:
The idea of the Internal Scan is to connect internal Flip-Flops and latches so that
we can observe them in test mode. Scan remains one of the most popular structured
techniques for digital circuits. This above process is known as Scan chain
Insertion. In the VLSI industry, it is also known as DFT Insertion or DFT
synthesis.
To enable scan test for a chip additional test logic must be inserted it is scan
insertion .
Clocked-scan cell:
It is also mainly used to replace D-FF, but it is selected by two independent clks.
A data clock DCK; a shift clock SCK;
The main advantage is that it will not affect the timing of the data path, but
requires one more clock routing.
Scan Replacement:
After scan configuration, scan replacement replaces storage element with
functionally equivalent scan cell
The design at this time is called scan-ready design.
The inputs of these scan cells are usually connected to the outputs of the same scan
cell to avoid floating. These connections are removed at the stitch stage.
Currently, partial scan replacement can also be implemented in the RTL stage.
Scan Reordering
Reacts the reorder of scan cells in the scan chain. Before physical implementation,
a random scan order is used by design.
When performing physical implementation, scan order can use intra_scan_chain
reordering (scan cell is only in this scan
Re order within the chain) and inter_scan_chain reordering (scan cell reorder
between different scan chains)
Scan stitching
Stitch all scan cells together to form a scan chain. Connect the output of each scan
cell to the input of the next level.
Connect the input of the first scan cell to the primary input, and the output of the
last scan cell to the primary output.
In the process of stitching, some lock_up latches and lock_up FFs need to be
inserted to ensure that the shift operation is correct.
After scan stitch, scan synthesis has been completed,
Scan extraction is mainly used to extract all instances from scan design to ensure
the integrity of the scan chain.
And ensure that all design changes are integrated into scan design.
Scan Verification
1) Hold time violation in shift operate, if two scan cells are at the same clock, CTS
is required to ensure that there is a clock skew
The value of minimum. If the clock is an asynchronous clock, the lock_up latch
needs to be inserted.
2) Wrong scan initialization sequence, cannot enter test mode.
3) Check and repair of incomplete scan design rule, set/reset of reg and enable/gate
of clock, etc.
4) The error of scan synthesis, put the positive before the negative, etc.
Tessent TestKompress creates and embeds compression logic (EDT logic) and
generates compressed test patterns as follows:
• Decompressor — Feeds a large number of scan chains in your core design from a
small number of scan channels, and decompresses EDT scan patterns as they are
shifted in.
The decompressor resides between the channel inputs (connected to the tester) and
the scan chain inputs of the core. Its main parts are an LFSM and a phase shifter.
• Compactor — compacts the test responses from the scan chains in your core
design into a small number of scan output channels as they are shifted out. The
compactor resides between the core scan chain outputs and the channel outputs
connected to the tester. It primarily consists of spatial compactor(s) and gating
logic.
But there are two problems that we may encounter –
a. ‘X’ contamination due to unknown value propagation
b. Fault Aliasing due to bad Probability of Aliasing (PAL)
a fault is aliased when it is observed by an even number of scan cells
that happened to line up at the same location in different scan chains
that are compacted to the same output channel.
Bypassing the EDT logic enables you to apply uncompressed test patterns to the
design to:
• Debug compressed test patterns.
• Apply additional custom uncompressed scan chains.
• Apply test patterns from other ATPG tools.
Bypass logic can also be inserted in the core netlist at scan insertion time. This
allows you to place the multiplexers and lockup cells required to operate the
bypass mode inside the core netlist instead of the EDT logic.
Test Data Volume ≈ Number of Scan Cells in all the Scan Chains × Scan
Patterns
ATPG stands for Automatic Test Pattern Generation. Test patterns, sometimes
called test vectors, are sets of 1s and 0s placed on primary input pins during the
manufacturing test process to determine if the chip is functioning properly. When
the test pattern is applied, the Automatic Test Equipment (ATE) determines if the
circuit is free from manufacturing defects by comparing the fault-free output—
which is also contained in the test pattern—with the actual output measured by the
ATE.
The goal of ATPG is to create a set of patterns that achieves a given test coverage,
where test coverage is the total percentage of testable faults the pattern set actually
detects.
ATPG consists of two main steps: 1) generating patterns and, 2) performing fault
simulation to determine which faults the patterns detect. The two most typical
methods for pattern generation are random and deterministic.
ATPG Tool Inputs and Outputs the ATPG tool uses multiple inputs to produce test
patterns, a fault list, and ATPG information files.
Inputs :
Design
The supported design data format is gate-level Verilog. Other inputs also include
1) a cell model from the design library and 2) a previously-saved, flattened model.
Library
The design library contains descriptions of all the cells used in the design. The tool
uses the library to translate the design data into a flat, gate-level simulation model
for use by the fault simulator and test generator.
Fault List
The tool can read in an external fault list. The tool uses this list of faults and their
current status as a starting point for test generation.
Test Patterns
The tool can read in an external fault list. The tool uses this list of faults and their
current status as a starting point for test generation.
Outputs:
Test Patterns
The tool generates files containing test patterns. They can generate these patterns
in a number of different simulator and ASIC vendor formats.
Fault List
This is an ASCII-readable file that contains internal fault information in the
standard Mentor Graphics fault format.
On -chip clock controller is the logic inserted on the SOC for controlling clocks
during silicon testing for defects on ATE (Automatic test Equipment). OCC
enables the AT-speed/Transition testing of the Logic by generating two clock
pulses at speed during capture phase. So OCC enables the pulse control of the
clock during Test mode through clock chain (chain comprising all the OCC logic
flops in a chain)
Without OCC you need to provide At-speed pulses through Top pins called PADS.
But Pads has limitation in terms of maximum frequency they can support. OCC on
other hand uses internal PLL clock for generating 2 pulses for test.
The standard OCC performs all three OCC functions: clock selection, clock
chopping control, and clock gating.
Depending on your design style, you may need to guide the Clock Tree Synthesis
(CTS) not to balance the flops and latches in the OCC with the clock tree it drives.
Clock skew is two different flip flops receive the clock signal at slightly different
time due to difference in clock net length but clock jitter is on the same flip flop
but the position of clock edge moves edge to edge due to some noise in oscillator.
Clock Jitter: Sometimes some external sources like noise, voltage variations may
cause to disrupt the natural periodicity or frequency of the clock. This deviation
from the natural location of the clock is termed to be clock jitter.
Setup Time: If the data or signal changes just before the active edge of the clock
then we say that setup time has been violated.
Hold Time: If the data or signal changes after the active edge of the clock then we
say that hold time has been violated.
Setup time is frequency dependent (depends on clock period) whereas hold time is
frequency independent (doesn’t depends on clock period).
Setup Time and Hold Time: If the data or signal changes just before and after the
active edge of the clock respectively then we say that setup time/ hold time has
been violated.
Causes for Setup Time: Setup violations can happen as a result of slow conditions
(slow process, high temperature) leading to signals arriving too late in the clock
period.
Strategy to Fix Setup Time: Reduce Delay.
Try to make use of libraries derived from NAND logic.
Restructuring/Re-timing would be the best way to optimize the logic.
For a critical path with a capture flop and a launch flop.
Causes for Hold Time Violations: Hold violations can happen as a result of fast
conditions (fast process, low temperature) leading to signals arriving too early in
the clock period.
Strategy to Fix Hold Time:
Insert buffers.
Use data-path cells with higher threshold voltages.
Lock up Latches
A positive skew degrades hold timing and a negative skew aids hold timing.
False paths:
Paths in the design which doesn't require timing analysis are called false paths.
Multicycle path:
Paths in the design which can have some timing exception to propagate from the
start point to end point for specific number of clocks. Which means the data from
start point to end point will changes only once per specified number of clock, those
paths are called multicycle paths.
Clock gating logic can also be used to generate the clock pulse. In many circuits,
clock gating logic serving multiple purposes like reduce power consumption and
improve design performance
Clock gating is a common technique for reducing clock power by shutting off the
clock to modules by a clock enable signal. Clock gating functionally requires only
an AND or OR gate.
Since the enable signal can change any time, which may not be synchronous with
the clock signal, it can cause a glitch in the gated clock. To avoid this
situation, a latch is added in front of the logic gate in order to synchronize the
enable signal with the clock edge.
There are two types of clock gating styles available. They are: 1) Latch-based
clock gating 2) Latch-free clock gating. The latch-free clock gating style uses a
simple AND or OR gate (depending on the edge on which flip-flops are triggered).
While creating fault site list, tool identifies fault which are dependent to each other
and consider them as equivalent faults.
If 4 faults are equivalent, then tool mark one of them as a real fault and rest three
of them are marked as collapsed to the real fault. This concept is called fault
collapsing.
After we generate all the test patterns, we need to validate those test patterns. So,
we can trust those test patterns as golden test patterns. Thus we run simulation
those test patterns with fault. This process is called fault simulation.
What is launch off shift and launch off capture in DFT? (VLSI)
If we have the lunching clock pulse with Shift enable =1 then we call it Lunch off
shift (LOS). Similarly, If we have the lunching clock pulse with Shift enable =0
then we call it Lunch off capture (LOC). Both method will test the fault site but
they have their own pros and cons.
It is necessary that the timing path should be same as the functional path. i.e.,
clocks should be the same in both functional & at-speed test mode. Whatever
methodology (Launch on Shift / Launch on Capture) is required to meet this
requirement should be implemented. There are other critical factors that will also
drive to LOS / LOC implementation.
a) For LOS the scan enable has to closed at functional frequency (which may result
in gate count increase with addition of large buffers), whereas in LOC the timing
on scan enable can relaxed between the last shift and launch cycle.
b) LOS atpg run time is less compared to the LOC for pattern generation.
c) Pattern count in LOS in less than the LOC.
d) Test/fault coverage for LOS is higher than the LOC.
I) Launch on last shift - In this method, during the last shift itself, we will shift in
the required value in to the flop which will create the required transition on the
intended node.
Advantages: 1) Tool has the controllability to put the required value in to the flop
to cause transition.
2) We will get good coverage as we are launching the value through SD path.
Disadvantages: 1) Scan-enable need to change at-speed, we have to implement
II) Launch on capture - In this method, the flop which creates the launch on the
intended node will get the value through D path. Scan-enable will be low during
this time.
A fault model tries to model the impact of different type of physical effects which
can occur on silicon. Corresponding to the type of fault which we are targeting,
different type of fault models are used. Following are some commonly used fault
models
1. Single Stuck at 0 /Single stuck at 1
2. Multiple stuck at
3. Bridging
4. Stuck Open
5. Transition fault model
6. Path delay fault model
1. Stuck-at Faults
This is the most common fault model used in industry. It models manufacturing
defects which occurs when a circuit node is shorted to VDD (stuck-at-1 fault) or
GND (stuck-at-0 fault) permanently. The fault can be at the input or output of a
gate.
2. At-speed Faults
It models the manufacturing defects that behave as gross delays on gate input-
output ports. So each port is tested for logic 0-to-1 transition delay (slow-to-rise
fault) or logic 1-to-0 transition delay (slow-to-fall fault). Like stuck-at faults, the
at-speed fault can be at the input or output of a gate. The reason for transition-delay
at a node is some manufacturing defect at that node (more resistive node). The
reason for path-delay is some manufacturing defect that is distributed throughout
the path (more resistive path).
Fault Coverage: the fault coverage is the percentage detected of all faults.it gives
no credit for undetectable faults.
Fault Coverage=(DT+(NP+AP)*PT_credit)/total faults.
DT-Detected
-DR-detected robustly
-DS-detected by simulation-
DI-Detected by implication
PT-Possibly detected
-AP-ATPG untestable possibly detected.
NP-not analysed, possibly detected.
UD-Undetectable
-UU-undectable unused-
UT-Undectable tied-
UB undetectable tied-
UR undetectable redundant
AU-ATPG untestable-
AN-ATPG untestable not detected.
ND- not detected-
NC-not controlled.-
NO-not observed.
Where to use a lock-up latch: As mentioned above, a lock-up latch is used where
there is high probability of hold failure in scan-shift modes. So, possible scenarios
where lockup latches are to be inserted are:
Scan chains from different clock domains: In this case, since, the two
domains do not interact functionally, so both the clock skew and uncommon
clock path will be large.
Flops within same domain, but at remote places: Flops within a scan
chain which are at remote places are likely to have more uncommon clock
path.
Advantages of inserting lockup latches:
Inserting lock-up latches helps in easier hold timing closure for scan-shift
mode
Robust method of hold timing closure where uncommon path is high
between launch and capture flops
Power efficient and area efficient
It improves yield as it enables the device to handle more variations.
For flops triggering on positive edge of the clock, you need to have latch
transparent when clock is low (negative level-sensitive lockup latch)
For flops triggering on negative edge of the clock, you need to have latch
transparent when clock is high (positive level-sensitive lockup latch)
On further back tracing the scan_clk and RESET_L signals, below source
test_mode – X and scan_clk – 1 is observed.
F {
“scan_clk” = P; //scan clock is pulsing, it will override the value in C section, so
clock will pulse in capture cycle.
}
Solution 1:
C {
“All_in” = 00 \r4 N 1011;
}
F {
“scan_clk” = P;
“test_mode” = 1 //It should be throughout 1 for all the process.
}
Scenario 2:
In “load_unload” procedure – Clock should be pulsing for shift procedures.
In below scenario clock is defined constant 1.
C {
“All_in” = 11 \r8 N;
}
Shift {
V {
"Clock" = 11;
}}
Solution 2:
C {
“All_in” = 00 \r4 N 1011;
}
Shift {
V {
"Clock" = PP; // clock should be pulsing while shifting
}}
Scenario 3:
If the scan clock frequency is different than the required frequency, then change
the clock period in _WFT table, as shown below:
“scan_clk" { P { '0ns' D; '35ns' U; '65ns' D; } }
"clk" { P { '0ns' D; '25ns' U; '75ns' D; } }
Change the period in ns for the up and down section of the respected scan clock
according to the required frequency.
SPF is also used to feed instructions and data bits to the UTDR (user defined test
data register bits) and for initialization/test setup purpose as well.