ADS

ADS1242
®
124 ADS

ADS1243
2 ®
124
3

SBAS235H – DECEMBER 2001 – REVISED OCTOBER 2013

24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES DESCRIPTION
● 24 BITS NO MISSING CODES The ADS1242 and ADS1243 are precision, wide dynamic
● SIMULTANEOUS 50Hz AND 60Hz REJECTION range, delta-sigma, analog-to-digital (A/D) converters with
(–90dB MINIMUM) 24-bit resolution operating from 2.7V to 5.25V supplies.
● 0.0015% INL These delta-sigma, A/D converters provide up to 24 bits of no
● 21 BITS EFFECTIVE RESOLUTION missing code performance and effective resolution of 21 bits.
(PGA = 1), 19 BITS (PGA = 128) The input channels are multiplexed. Internal buffering can be
● PGA GAINS FROM 1 TO 128 selected to provide a very high input impedance for direct
● SINGLE-CYCLE SETTLING connection to transducers or low-level voltage signals. Burn-
● PROGRAMMABLE DATA OUTPUT RATES out current sources are provided that allow for the detection
of an open or shorted sensor. An 8-bit digital-to-analog
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 5V converter (DAC) provides an offset correction with a range of
50% of the FSR (Full-Scale Range).
● ON-CHIP CALIBRATION
● SPI™ COMPATIBLE The Programmable Gain Amplifier (PGA) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
● 2.7V TO 5.25V SUPPLY RANGE
of 128. The A/D conversion is accomplished with a second-order
● 600µW POWER CONSUMPTION delta-sigma modulator and programmable FIR filter that pro-
● UP TO EIGHT INPUT CHANNELS vides a simultaneous 50Hz and 60Hz notch. The reference input
● UP TO EIGHT DATA I/O is differential and can be used for ratiometric conversion.
The serial interface is SPI compatible. Up to eight bits of data
APPLICATIONS I/O are also provided that can be used for input or output. The
● INDUSTRIAL PROCESS CONTROL ADS1242 and ADS1243 are designed for high-resolution
measurement applications in smart transmitters, industrial
● LIQUID /GAS CHROMATOGRAPHY
process control, weight scales, chromatography, and portable
● BLOOD ANALYSIS
instrumentation.
● SMART TRANSMITTERS
VDD VREF+ VREF– XIN XOUT
● PORTABLE INSTRUMENTATION
● WEIGHT SCALES VDD
Clock Generator

2µA Offset
DAC

AIN0/D0
AIN1/D1 A = 1:128
AIN2/D2 IN+
AIN3/D3 2nd-Order Digital
MUX BUF + PGA Controller Registers
IN– Modulator Filter
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7

ADS1243 SCLK
Only 2µA Serial Interface DIN
DOUT
GND CS

GND PDWN DRDY

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001-2013, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
VDD to GND ........................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary DISCHARGE SENSITIVITY
Input Current ................................................................. 10mA, Continuous
AIN .................................................................... GND – 0.5V to VDD + 0.5V This integrated circuit can be damaged by ESD. Texas Instru-
Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V ments recommends that all integrated circuits be handled with
Digital Output Voltage to GND ................................... –0.3V to VDD + 0.3V appropriate precautions. Failure to observe proper handling
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C and installation procedures can cause damage.
Storage Temperature Range .......................................... –60°C to +100°C
ESD damage can range from subtle performance degradation
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may to complete device failure. Precision integrated circuits may be
cause permanent damage to the device. Exposure to absolute maximum
more susceptible to damage because very small parametric
conditions for extended periods may affect device reliability.
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.

DIGITAL CHARACTERISTICS: TMIN to TMAX, VDD 2.7V to 5.25V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital Input/Output
Logic Family CMOS
Logic Level: VIH 0.8 • VDD VDD V
VIL(1) GND 0.2 • VDD V
VOH IOH = 1mA VDD – 0.4 V
VOL IOL = 1mA GND GND + 0.4 V
Input Leakage: IIH VI = VDD 10 µA
IIL VI = 0 –10 µA
Master Clock Rate: fOSC 1 5 MHz
Master Clock Period: tOSC 1/fOSC 200 1000 ns

NOTE: (1) VIL for XIN is GND to GND + 0.05V.

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ELECTRICAL CHARACTERISTICS: VDD = 5V
All specifications TMIN to TMAX, VDD = +5V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

ADS1242
ADS1243

PARAMETER CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT (AIN0 – AIN7)

Analog Input Range Buffer OFF GND – 0.1 VDD + 0.1 V
Buffer ON GND + 0.05 VDD – 1.5 V
Full-Scale Input Range (In+) – (In–), See Block Diagram, RANGE = 0 ±VREF /PGA V
RANGE = 1 ±VREF /(2 • PGA) V
Differential Input Impedance Buffer OFF 5/PGA MΩ
Buffer ON 5 GΩ
Bandwidth
fDATA = 3.75Hz –3dB 1.65 Hz
fDATA = 7.50Hz –3dB 3.44 Hz
fDATA = 15.00Hz –3dB 14.6 Hz
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9 pF
Input Leakage Current Modulator OFF, T = 25°C 5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range RANGE = 0 ±VREF /(2 • PGA) V
RANGE = 1 ±VREF /(4 • PGA) V

Offset DAC Monotonicity 8 Bits

Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 1 ppm/°C
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error (1) 7.5 ppm of FS
Offset Drift(1) 0.02 ppm of FS/°C
Gain Error (1) 0.005 %
Gain Error Drift(1) 0.5 ppm/°C
Common-Mode Rejection at DC 100 dB
fCM = 60Hz, fDATA = 15Hz 130 dB
fCM = 50Hz, fDATA = 15Hz 120 dB
Normal-Mode Rejection fSIG = 50Hz, fDATA = 15Hz 100 dB
fSIG = 60Hz, fDATA = 15Hz 100 dB
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆VOUT /VDD)(2) 80 95 dB
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0 VDD V
VREF VREF ≡ (REF IN+) – (REF IN–), RANGE = 0 0.1 2.5 2.6 V
RANGE = 1 0.1 VDD V
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection fVREFCM = 60Hz, fDATA = 15Hz 120 dB
Bias Current(3) VREF = 2.5V 1.3 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage VDD 4.75 5.25 V
Current PGA = 1, Buffer OFF 240 375 µA
PGA = 128, Buffer OFF 450 800 µA
PGA = 1, Buffer ON 290 425 µA
PGA = 128, Buffer ON 960 1400 µA
SLEEP Mode 60 µA
Read Data Continuous Mode 230 µA
PDWN 0.5 nA
Power Dissipation PGA = 1, Buffer OFF 1.2 1.9 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C

NOTES: (1) Calibration can minimize these errors.

(2) ∆VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.

ADS1242, 1243 3
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ELECTRICAL CHARACTERISTICS: VDD = 3V
All specifications TMIN to TMAX, VDD = +3V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise specified.

ADS1242
ADS1243

PARAMETER CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT (AIN0 – AIN7)

Analog Input Range Buffer OFF GND – 0.1 VDD + 0.1 V
Buffer ON GND + 0.05 VDD – 1.5 V
Full-Scale Input Voltage Range (In+) – (In–) See Block Diagram, RANGE = 0 ±VREF /PGA V
RANGE = 1 ±VREF /(2 • PGA) V
Input Impedance Buffer OFF 5/PGA MΩ
Buffer ON 5 GΩ
Bandwidth
fDATA = 3.75Hz –3dB 1.65 Hz
fDATA = 7.50Hz –3dB 3.44 Hz
fDATA = 15.00Hz –3dB 14.6 Hz
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9 pF
Input Leakage Current Modulator OFF, T = 25°C 5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range RANGE = 0 ±VREF /(2 • PGA) V
RANGE = 1 ±VREF /(4 • PGA) V

Offset DAC Monotonicity 8 Bits

Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error(1) 15 ppm of FS
Offset Drift(1) 0.04 ppm of FS/°C
Gain Error(1) 0.01 %
Gain Error Drift(1) 1.0 ppm/°C
Common-Mode Rejection at DC 100 dB
fCM = 60Hz, fDATA = 15Hz 130 dB
fCM = 50Hz, fDATA = 15Hz 120 dB
Normal-Mode Rejection fSIG = 50Hz, fDATA = 15Hz 100 dB
fSIG = 60Hz, fDATA = 15Hz 100 dB
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆VOUT /VDD)(2) 75 90 dB
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0 VDD V
VREF VREF ≡ (REF IN+) – (REF IN–), RANGE = 0 0.1 1.25 1.30 V
RANGE = 1 0.1 2.5 2.6 V
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection fVREFCM = 60Hz, fDATA = 15Hz 120 dB
Bias Current(3) VREF = 1.25 0.65 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage VDD 2.7 3.3 V
Current PGA = 1, Buffer OFF 190 375 µA
PGA = 128, Buffer OFF 460 700 µA
PGA = 1, Buffer ON 240 375 µA
PGA = 128, Buffer ON 870 1325 µA
SLEEP Mode 75 µA
Read Data Continuous Mode 113 µA
PDWN = 0 0.5 nA
Power Dissipation PGA = 1, Buffer OFF 0.6 1.2 mW
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C

NOTES: (1) Calibration can minimize these errors.

(2) ∆VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.

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PIN CONFIGURATION (ADS1242) PIN CONFIGURATION (ADS1243)
Top View TSSOP Top View TSSOP

VDD 1 20 DRDY

VDD 1 16 DRDY XIN 2 19 SCLK

XIN 2 15 SCLK XOUT 3 18 DOUT

XOUT 3 14 DOUT PDWN 4 17 DIN

PDWN 4 13 DIN VREF+ 5 16 CS

ADS1242 ADS1243
VREF+ 5 12 CS VREF– 6 15 GND

VREF– 6 11 GND AIN0/D0 7 14 AIN3/D3

AIN0/D0 7 10 AIN3/D3 AIN1/D1 8 13 AIN2/D2

AIN1/D1 8 9 AIN2/D2 AIN4/D4 9 12 AIN7/D7

AIN5/D5 10 11 AIN6/D6

PIN DESCRIPTIONS (ADS1242) PIN DESCRIPTIONS (ADS1243)

PIN PIN
NUMBER NAME DESCRIPTION NUMBER NAME DESCRIPTION

1 VDD Power Supply 1 VDD Power Supply

2 XIN Clock Input
2 XIN Clock Input
3 XOUT Clock Output, used with crystal or ceramic
3 XOUT Clock Output, used with crystal or ceramic resonator.
resonator. 4 PDWN Active LOW. Power Down. The power down func-
4 PDWN Active LOW. Power Down. The power down func- tion shuts down the analog and digital circuits.
tion shuts down the analog and digital circuits. 5 VREF+ Positive Differential Reference Input
6 VREF– Negative Differential Reference Input
5 VREF+ Positive Differential Reference Input
7 AIN0/D0 Analog Input 0/Data I/O 0
6 VREF– Negative Differential Reference Input 8 AIN1/D1 Analog Input 1/Data I/O 1
7 AIN0/D0 Analog Input 0/Data I/O 0 9 AIN4/D4 Analog Input 4/Data I/O 4
8 AIN1/D1 Analog Input 1/Data I/O 1 10 AIN5/D5 Analog Input 5/Data I/O 5
9 AIN2/D2 Analog Input 2/Data I/O 2 11 AIN6/D6 Analog Input 6/Data I/O 6
12 AIN7/D7 Analog Input 7/Data I/O 7
10 AIN3/D3 Analog Input 3/Data I/O 3
13 AIN2/D2 Analog Input 2/Data I/O 2
11 GND Ground 14 AIN3/D3 Analog Input 3/Data I/O 3
12 CS Active LOW, Chip Select 15 GND Ground
13 DIN Serial Data Input, Schmitt Trigger 16 CS Active LOW, Chip Select
14 DOUT Serial Data Output 17 DIN Serial Data Input, Schmitt Trigger
18 DOUT Serial Data Output
15 SCLK Serial Clock, Schmitt Trigger
19 SCLK Serial Clock, Schmitt Trigger
16 DRDY Active LOW, Data Ready 20 DRDY Active LOW, Data Ready

ADS1242, 1243 5
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TIMING DIAGRAMS

CS

t3 t1 t2 t10

SCLK

t4 t5 t6 t2
t11
DIN MSB LSB

t7 t8 t9
(Command or Command and Data)
DOUT MSB(1) LSB(1)

NOTE: (1) Bit order = 0.

SCLK Reset Waveform ADS1242 or ADS1243

Resets On
Falling Edge 300 • tOSC < t12 < 500 • tOSC
t13 t13 t13 : > 5 • tOSC
SCLK 550 • tOSC < t14 < 750 • tOSC
1050 • tOSC < t15 < 1250 • tOSC
t12 t14 t15

DIAGRAM 1.

t16
tDATA

DRDY PDWN
t17 t18

SCLK

t19

DIAGRAM 2.

TIMING CHARACTERISTICS TABLE

SPEC DESCRIPTION MIN MAX UNITS

t1 SCLK Period 4 tOSC Periods

3 DRDY Periods
t2 SCLK Pulse Width, HIGH and LOW 200 ns
t3 CS low to first SCLK Edge; Setup Time(2) 0 ns
t4 DIN Valid to SCLK Edge; Setup Time 50 ns
t5 Valid DIN to SCLK Edge; Hold Time 50 ns
t6 Delay between last SCLK edge for DIN and first SCLK edge for DOUT:
RDATA, RDATAC, RREG, WREG 50 tOSC Periods
t 7(1) SCLK Edge to Valid New DOUT 50 ns
t 8(1) SCLK Edge to DOUT, Hold Time 0 ns
t9 Last SCLK Edge to DOUT Tri-State 6 10 tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10 CS LOW time after final SCLK edge.
Read from the device 0 tOSC Periods
Write to the device 8 tOSC Periods
t11 Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC 4 tOSC Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 2 DRDY Periods
SELFCAL 4 DRDY Periods
RESET (also SCLK Reset) 16 tOSC Periods
t16 Pulse Width 4 tOSC Periods
t17 Allowed analog input change for next valid conversion. 5000 tOSC Periods
t18 DOR update, DOR data not valid. 4 tOSC Periods
t19 First SCLK after DRDY goes LOW:
RDATAC Mode 10 tOSC Periods
Any other mode 0 tOSC Periods

NOTES: (1) Load = 20pF 10kΩ to GND.

(2) CS may be tied LOW.

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ADS1242, 1243
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TYPICAL CHARACTERISTICS
All specifications VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

EFFECTIVE NUMBER OF BITS vs PGA SETTING EFFECTIVE NUMBER OF BITS vs PGA SETTING
21.5 22
DR = 10
21.0 21
20.5 DR = 10
DR = 01 20
20.0

ENOB (rms)
ENOB (rms)

19.5 19
DR = 01
19.0 18
DR = 00
18.5 DR = 00
17
18.0 Buffer ON
Buffer OFF 16
17.5
17.0 15
1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128

PGA Setting PGA Setting

EFFECTIVE NUMBER OF BITS vs PGA SETTING NOISE vs INPUT SIGNAL

20.5 2.0

20.0 1.8
DR = 10
1.6
19.5 Noise (rms, ppm of FS)
1.4
19.0
ENOB (rms)

DR = 01 1.2
18.5
1.0
18.0
0.8
DR = 00
17.5 0.6
17.0 0.4
Buffer OFF, VREF = 1.25V
16.5 0.2
16.0 0
1 2 4 8 16 32 64 128 –2.5 –1.5 –0.5 0.5 1.5 2.5

PGA Setting VIN (V)

COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO

vs FREQUENCY vs FREQUENCY
140 140

120 120

100 100
CMRR (dB)

PSRR (dB)

80 80

60 60

40 40

20 20
Buffer ON Buffer ON
0 0
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Frequency of Power Supply (Hz) Frequency of Power Supply (Hz)

ADS1242, 1243 7
SBAS235H www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

OFFSET vs TEMPERATURE GAIN vs TEMPERATURE

(Cal at 25°C) (Cal at 25°C)
50 1.00010
PGA1 PGA16
1.00006
0

Gain (Normalized)
Offset (ppm of FS)

1.00002
–50
0.99998
PGA64
–100
0.99994
PGA128
–150
0.99990

–200 0.99986
–50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90
Temperature (°C) Temperature (°C)

CURRENT vs TEMPERATURE
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Buffer Off)
10 260
8
–40°C 250
6
4 240
INL (ppm of FS)

+85°C
Current (µA)

2 230
0
220
–2
–4 210
+25°C
–6
200
–8
–10 190
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 –50 –30 –10 10 30 50 70 90
VIN (V) Temperature (°C)

CURRENT vs VOLTAGE SUPPLY CURRENT vs SUPPLY

350 300

300 Normal Normal 250

4.91MHz 2.45MHz
250
200
Normal
Current (µA)

SLEEP
IDIGITAL (µA)

200 Normal
4.91MHz 4.91MHz 2.45MHz
SLEEP
150 2.45MHz 150
SLEEP
100 4.91MHz
100
50
Power Down
50
0 SLEEP
Power Down 2.45MHz
–50 0
3.0 3.25 3.5 3.75 4.0 4.25 4.5 4.75 5.0 3.0 3.5 4.0 4.5 5.0
VDD (V) VDD (V)

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ADS1242, 1243
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TYPICAL CHARACTERISTICS (Cont.)
All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

OFFSET DAC
OFFSET vs TEMPERATURE
NOISE HISTOGRAM (Cal at 25°C)
3500 200
10k Readings
VIN = 0V 170
3000
140
Number of Occurrences

Offset (ppm of FSR)

2500 110
80
2000
50
1500 20

1000 –10
–40
500
–70
0 –100
–3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –50 –30 –10 10 30 50 70 90
ppm of FS Temperature (°C)

OFFSET DAC
GAIN vs TEMPERATURE OFFSET DAC
(Cal at 25°C) NOISE vs SETTING
1.00020 0.8
1.00016
0.7
1.00012
Noise (rms, ppm of FS) 0.6
1.00008
Gain (Normalized)

1.00004 0.5
1.00000
0.4
0.99996
0.99992 0.3
0.99988
0.2
0.99984
0.99980 0.1
0.99976 0
–50 –30 –10 10 30 50 70 90 –128 –96 –64 –32 0 32 64 96 128
Temperature (°C) Offset DAC Setting

ADS1242, 1243 9
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OVERVIEW channel. With this method, it is possible to have up to seven
single-ended input channels or four independent differential
INPUT MULTIPLEXER input channels for the ADS1243, and three single-ended
The input multiplexer provides for any combination of differ- input channels or two independent differential input channels
ential inputs to be selected on any of the input channels, as for the ADS1242.
shown in Figure 1. For example, if AIN0 is selected as the The ADS1242 and ADS1243 feature a single-cycle settling
positive differential input channel, any other channel can be digital filter that provides valid data on the first conversion
selected as the negative terminal for the differential input after a new channel selection. In order to minimize the
settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY. In
other words, issuing a MUX change through the WREG
AIN0/D0
command immediately after DRDY goes LOW minimizes the
settling error. Increasing the time between the conversion
beginning (DRDY goes LOW) and the MUX change com-
AIN1/D1 mand (tDELAY) results in a settling error in the conversion
VDD

data, as shown in Figure 2.

Burnout Current Source
AIN2/D2

BURNOUT CURRENT SOURCES

AIN3/D3 The Burnout Current Sources can be used to detect sensor
short-circuit or open-circuit conditions. Setting the Burnout
Input Current Sources (BOCS) bit in the SETUP register activates
AIN4/D4 Buffer
two 2µA current sources called burnout current sources. One
of the current sources is connected to the converter’s nega-
AIN5/D5 tive input and the other is connected to the converter’s
positive input.
Burnout Current Source

AIN6/D6 Figure 3 shows the situation for an open-circuit sensor. This

GND is a potential failure mode for many kinds of remotely con-
nected sensors. The current source on the positive input acts
AIN7/D7
as a pull-up, causing the positive input to go to the positive
analog supply, and the current source on the negative input
ADS1243 acts as a pull-down, causing the negative input to go to
Only
ground. The ADS1242/43 therefore outputs full-scale (7FFFFF
Hex).
FIGURE 1. Input Multiplexer Configuration.
Figure 4 shows a short-circuited sensor. Since the inputs are

New Conversion Begins, Previous Conversion Data

Complete Previous Conversion New Conversion Complete

DRDY

tDELAY

SCLK

DIN MSB LSB

SETTLING ERROR vs DELAY TIME

fCLK = 2.4576MHz
10

0.1
Settling Error (%)

0.01

0.001

0.0001

0.00001

0.000001
0 2 4 6 8 10 12 14 16
Delay Time, tDELAY (ms)

FIGURE 2. Input Multiplexer Configuration.

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 current required by the buffer depends on the PGA setting.
VDD When the PGA is set to 1, the buffer uses approximately
50µA; when the PGA is set to 128, the buffer uses approxi-

2µA
mately 500µA.

VDD
PGA
OPEN CIRCUIT ADC CODE = 0x7FFFFFH The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
0V
effective resolution of the A/D converter. For instance, with a
2µA
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1µV. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. VDD
current increases with PGA settings higher than 4.

FIGURE 3. Burnout detection while sensor is open-circuited.

OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
shorted and at the same potential, the ADS1242/43 signal range of the PGA using the Offset DAC (ODAC) register. The
outputs are approximately zero. (Note that the code for ODAC register is an 8-bit value; the MSB is the sign and the
shorted inputs is not exactly zero due to internal series seven LSBs provide the magnitude of the offset. Using the
resistance, low-level noise and other error sources.) offset DAC does not reduce the performance of the A/D
INPUT BUFFER converter. For more details on the ODAC in the ADS1242/43,
please refer to TI application report SBAA077 (available
through the TI website).
VDD
MODULATOR
2µA The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
VDD/2 the external clock (fOSC). The frequency division is deter-
mined by the SPEED bit in the SETUP register, as shown in
SHORT
ADC CODE ≅ 0 Table I.
CIRCUIT

VDD/2

2µA SPEED DR BITS 1st NOTCH

fOSC BIT fMOD 00 01 10 FREQ.
2.4576MHz 0 19,200Hz 15Hz 7.5Hz 3.75Hz 50/60Hz
1 9,600Hz 7.5Hz 3.75Hz 1.875Hz 25/30Hz
4.9152MHz 0 38,400Hz 30Hz 15Hz 7.5Hz 100/120Hz
FIGURE 4. Burnout detection while sensor is short-circuited. 1 19,200Hz 15Hz 7.5Hz 3.75Hz 50/60Hz

TABLE I. Output Configuration.

The input impedance of the ADS1242/43 without the buffer
enabled is approximately 5MΩ/PGA. For systems requiring
CALIBRATION
very high input impedance, the ADS1242/43 provides a
chopper-stabilized differential FET-input voltage buffer. When The offset and gain errors can be minimized with calibration.
activated, the buffer raises the ADS1242/43 input impedance The ADS1242 and ADS1243 support both self and system
to approximately 5GΩ. calibration.
The buffer’s input range is approximately 50mV to Self-calibration of the ADS1242 and ADS1243 corrects inter-
VDD – 1.5V. The buffer’s linearity will degrade beyond this nal offset and gain errors and is handled by three commands:
range. Differential signals should be adjusted so that both SELFCAL, SELFGAL, and SELFOCAL. The SELFCAL com-
signals are within the buffer’s input range. mand performs both an offset and gain calibration. SELFGCAL
performs a gain calibration and SELFOCAL performs an
The buffer can be enabled using the BUFEN pin or the
offset calibration, each of which takes two tDATA periods to
BUFEN bit in the ACR register. The buffer is on when the
complete. During self-calibration, the ADC inputs are discon-
BUFEN pin is high and the BUFEN bit is set to one. If the
nected internally from the input pins. The PGA must be set to
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
1 prior to issuing a SELFCAL or SELFGCAL command. Any
set to zero, the buffer is also disabled.
PGA is allowed when issuing a SELFOCAL command. For
The buffer draws additional current when activated. The

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example, if using PGA = 64, first set PGA = 1 and issue
SELFGCAL. Afterwards, set PGA = 64 and issue SELFOCAL. XIN
For operation with a reference voltage greater than C1
(VDD – 1.5) volts, the buffer must also be turned off during Crystal

gain self-calibration to avoid exceeding the buffer input XOUT

range. C2

System calibration corrects both internal and external offset

and gain errors. While performing system calibration, the
appropriate signal must be applied to the inputs. The system
FIGURE 5. Crystal Connection.
offset calibration command (SYSOCAL) requires a zero input
differential signal (see Table IV, page 18). It then computes
the offset that nullifies the offset in the system. The system CLOCK PART
gain calibration command (SYSGCAL) requires a positive SOURCE FREQUENCY C1 C2 NUMBER
full-scale input signal. It then computes a value to nullify the Crystal 2.4576 0-20pF 0-20pF ECS, ECSD 2.45 - 32
gain error in the system. Each of these calibrations takes two Crystal 4.9152 0-20pF 0-20pF ECS, ECSL 4.91
tDATA periods to complete. System gain calibration is recom- Crystal 4.9152 0-20pF 0-20pF ECS, ECSD 4.91
mended for the best gain calibration at higher PGAs. Crystal 4.9152 0-20pF 0-20pF CTS, MP 042 4M9182

Calibration should be performed after power on, a change in TABLE II. Recommended Crystals.
temperature, or a change of the PGA. The RANGE bit (ACR bit
2) must be zero during calibration.
DIGITAL FILTER
Calibration removes the effects of the ODAC; therefore, dis-
The ADS1242 and ADS1243 have a 1279 tap linear phase
able the ODAC during calibration, and enable again after
Finite Impulse Response (FIR) digital filter that a user can
calibration is complete.
configure for various output data rates. When a 2.4576MHz
At the completion of calibration, the DRDY signal goes low, crystal is used, the device can be programmed for an output
indicating the calibration is finished. The first data after data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions,
calibration should be discarded since it may be corrupt from the digital filter rejects both 50Hz and 60Hz interference. Figure
calibration data remaining in the filter. The second data is 6 shows the digital filter frequency response for data output
always valid. rates of 15Hz, 7.5Hz, and 3.75Hz.
If a different data output rate is desired, a different crystal
EXTERNAL VOLTAGE REFERENCE frequency can be used. However, the rejection frequencies
The ADS1242 and ADS1243 require an external voltage shift accordingly. For example, a 3.6864MHz master clock with
reference. The selection for the voltage reference value is the default register condition has:
made through the ACR register. (3.6864MHz/2.4576MHz) • 15Hz = 22.5Hz data output rate
The external voltage reference is differential and is repre- and the first and second notch is:
sented by the voltage difference between the pins: +VREF
1.5 • (50Hz and 60Hz) = 75Hz and 90Hz
and –VREF. The absolute voltage on either pin, +VREF or
–VREF, can range from GND to VDD. However, the following
limitations apply: DATA I/O INTERFACE
For VDD = 5.0V and RANGE = 0 in the ACR, the differential The ADS1242 has four pins and the ADS1243 has eight pins
VREF must not exceed 2.5V. that serve a dual purpose as both analog inputs and data
I/O. These pins are configured through the IOCON, DIR, and
For VDD = 5.0V and RANGE = 1 in the ACR, the differential
DIO registers and can be individually configured as either
VREF must not exceed 5V.
analog inputs or data I/O. See Figure 7 (page 14) for the
For VDD = 3.0V and RANGE = 0 in the ACR, the differential equivalent schematic of an Analog/Data I/O pin.
VREF must not exceed 1.25V.
The IOCON register defines the pin as either an analog input
For VDD = 3.0V and RANGE = 1 in the ACR, the differential or data I/O. The power-up state is an analog input. If the pin
VREF must not exceed 2.5V. is configured as an analog input in the IOCON register, the
DIR and DIO registers have no effect on the state of the pin.
CLOCK GENERATOR If the pin is configured as data I/O in the IOCON register,
The clock source for the ADS1242 and ADS1243 can be then DIR and DIO are used to control the state of the pin.
provided from a crystal, oscillator, or external clock. When the The DIR register controls the direction of the data pin, either
clock source is a crystal, external capacitors must be provided as an input or output. If the pin is configured as an input in
to ensure start-up and stable clock frequency. This is shown in the DIR register, then the corresponding DIO register bit
both Figure 5 and Table II. XOUT is only for use with external reflects the state of the pin. Make sure the pin is driven to a
crystals and it should not be used as a clock driver for external logic one or zero when configured as an input to prevent
circuitry.

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 ADS1242 AND ADS1243 FREQUENCY RESPONSE FROM 45Hz to 65Hz
FILTER RESPONSE WHEN fDATA = 15Hz WHEN fDATA = 15Hz
0 –40
–20 –50

–40 –60
–70
–60

Magnitude (dB)
–80
Gain (dB)

–80
–90
–100
–100
–120
–110
–140
–120
–160 –130
–180 –140
0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 65
Frequency (Hz) Frequency (Hz)

ADS1242 AND ADS1243 FREQUENCY RESPONSE FROM 45Hz to 65Hz

FILTER RESPONSE WHEN fDATA = 7.5Hz WHEN fDATA = 7.5Hz
0 –40

–20 –50

–40 –60
–70
–60

Magnitude (dB)
–80
Gain (dB)

–80
–90
–100
–100
–120
–110
–140 –120
–160 –130
–180 –140
0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 65
Frequency (Hz) Frequency (Hz)

ADS1242 AND ADS1243 FREQUENCY RESPONSE FROM 45Hz to 65Hz

FILTER RESPONSE WHEN fDATA = 3.75Hz WHEN fDATA = 3.75Hz
0 –40
–20 –50

–40 –60

–60 –70
Magnitude (dB)

–80
Gain (dB)

–80
–90
–100
–100
–120
–110
–140
–120
–160 –130
–180 –140
0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 65
Frequency (Hz) Frequency (Hz)

fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1

ATTENUATION
DATA –3dB
OUTPUT RATE BANDWIDTH fIN = 50 ± 0.3Hz fIN = 60 ± 0.3Hz fIN = 50 ± 1Hz fIN = 60 ± 1Hz
15Hz 14.6Hz –80.8dB –87.3dB –68.5dB –76.1dB
7.5Hz 3.44Hz –85.9dB –87.4dB –71.5dB –76.2dB
3.75Hz 1.65Hz –93.8dB –88.6dB –86.8dB –77.3dB

FIGURE 6. Filter Frequency Responses.

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excess current dissipation. If the pin is configured as an Data Input (DIN) and Data Output (DOUT)
output in the DIR register, then the corresponding DIO The data input (DIN) and data output (DOUT) receive and send
register bit value determines the state of the output pin data from the ADS1242 and ADS1243. DOUT is high imped-
(0 = GND, 1 = VDD). ance when not in use to allow DIN and DOUT to be connected
It is still possible to perform A/D conversions on a pin together and driven by a bidirectional bus. Note: the Read
configured as data I/O. This may be useful as a test mode, Data Continuous Mode (RDATAC) command should not be
where the data I/O pin is driven and an A/D conversion is issued when DIN and DOUT are connected. While in RDATAC
done on the pin. mode, DIN looks for the STOPC or RESET command. If
either of these 8-bit bytes appear on DOUT (which is con-
nected to DIN), the RDATAC mode ends.
IOCON
DIR DATA READY ( DRDY) PIN
The DRDY line is used as a status signal to indicate when
data is ready to be read from the internal data register.
DIO WRITE
DRDY goes LOW when a new data word is available in the
AINx/Dx
DOR register. It is reset HIGH when a read operation from
To Analog Mux
the data register is complete. It also goes HIGH prior to the
DIO READ
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
FIGURE 7. Analog/Data Interface Pin.
The status of DRDY can also be obtained by interrogating bit
7 of the ACR register (address 2H). The serial interface can
SERIAL PERIPHERAL INTERFACE
operate in 3-wire mode by tying the CS input LOW. In this
The Serial Peripheral Interface (SPI) allows a controller to case, the SCLK, DIN, and DOUT lines are used to communi-
communicate synchronously with the ADS1242 and ADS1243. cate with the ADS1242 and ADS1243. This scheme is
The ADS1242 and ADS1243 operate in slave-only mode. suitable for interfacing to microcontrollers. If CS is required
The serial interface is a standard four-wire SPI (CS , SCLK, as a decoding signal, it can be generated from a port bit of
DIN and DOUT) interface. the microcontroller.
Chip Select (CS )
The chip select (CS ) input must be externally asserted DSYNC OPERATION
before communicating with the ADS1242 or ADS1243. CS Synchronization can be achieved through the DSYNC
must stay LOW for the duration of the communication. command. When the DSYNC command is sent, the digital
Whenever CS goes HIGH, the serial interface is reset. CS filter is reset on the edge of the last SCLK of the DSYNC
may be hard-wired LOW. command. The modulator is held in RESET until the next
Serial Clock (SCLK) edge of SCLK is detected. Synchronization occurs on the
next rising edge of the system clock after the first SCLK
The serial clock (SCLK) features a Schmitt-triggered input
following the DSYNC command.
and is used to clock DIN and DOUT data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within three DRDY pulses, the POWER-UP—SUPPLY VOLTAGE RAMP RATE
serial interface resets on the next SCLK pulse and starts a
The power-on reset circuitry was designed to accommodate
new communication cycle. A special pattern on SCLK resets
digital supply ramp rates as slow as 1V/10ms. To ensure
the entire chip; see the RESET section for additional informa-
proper operation, the power supply should ramp monotoni-
tion.
cally.

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ADS1242 AND ADS1243
REGISTERS
The operation of the device is set up through individual multiplexer settings, calibration settings, data rate, etc. The
registers. Collectively, the registers contain all the informa- 16 registers are shown in Table III.
tion needed to configure the part, such as data format,

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00H SETUP ID ID ID ID BOCS PGA2 PGA1 PGA0

01H MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
02H ACR DRDY U/B SPEED BUFEN BIT ORDER RANGE DR1 DR0
03H ODAC SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
04H DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0
05H DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0
06H IOCON IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
07H OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
08H OCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08
09H OCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
0AH FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
0BH FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08
0CH FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
0DH DOR2 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
0EH DOR1 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR09 DOR08
0FH DOR0 DOR07 DOR16 FSR21 DOR04 DOR03 DOR02 DOR01 DOR00

TABLE III. Registers.

DETAILED REGISTER DEFINITIONS MUX (Address 01H) Multiplexer Control Register

SETUP (Address 00H) Setup Register Reset Value = 01H
Reset Value = iiii0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
ID ID ID ID BOCS PGA2 PGA1 PGA0
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
bit 7-4 Factory Programmed Bits Select
bit 3 BOCS: Burnout Current Source 0000 = AIN0 (default)
0 = Disabled (default) 0001 = AIN1
1 = Enabled 0010 = AIN2
0011 = AIN3
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier
0100 = AIN4
Gain Selection
0101 = AIN5
000 = 1 (default)
0110 = AIN6
001 = 2
0111 = AIN7
010 = 4
1111 = Reserved
011 = 8
100 = 16 bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
101 = 32 Select
110 = 64 0000 = AIN0
111 = 128 0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1111 = Reserved

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ACR (Address 02H) Analog Control Register ODAC (Address 03 ) Offset DAC
Reset Value = X0H Reset Value = 00H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

DRDY U/B SPEED BUFEN BIT ORDER RANGE DR1 DR0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0

bit 7 DRDY: Data Ready (Read Only)

bit 7 Sign
This bit duplicates the state of the DRDY pin.
0 = Positive
bit 6 U/B: Data Format 1 = Negative
0 = Bipolar (default)
1 = Unipolar VREF  OSET [6 : 0] 
Offset = •  RANGE = 0
2 • PGA  127 
U/B ANALOG INPUT DIGITAL OUTPUT (Hex)
+FSR 0x7FFFFF
VREF  OSET [6 : 0] 
0 Zero 0x000000 Offset = •  RANGE = 1
–FSR 0x800000 4 • PGA  127 
+FSR 0xFFFFFF
1 Zero 0x000000
NOTE: The offset DAC must be enabled after calibration or the calibration
–FSR 0x000000
nullifies the effects.

bit 5 SPEED: Modulator Clock Speed

DIO (Address 04H) Data I/O
0 = fMOD = fOSC/128 (default)
Reset Value = 00H
1 = fMOD = fOSC/256
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 4 BUFEN: Buffer Enable
0 = Buffer Disabled (default) DIO 7 DIO 6 DIO 5 DIO 4 DIO 3 DIO 2 DIO 1 DIO 0
1 = Buffer Enabled
If the IOCON register is configured for data, a value written
bit 3 BIT ORDER: Data Output Bit Order to this register appears on the data I/O pins if the pin is
0 = Most Significant Bit Transmitted First (default) configured as an output in the DIR register. Reading this
1 = Least Significant Bit Transmitted First register returns the value of the data I/O pins.
Data is always shifted in or out MSB first. Bits 4 to 7 are not used in ADS1242.
bit 2 RANGE: Range Select
0 = Full-Scale Input Range equal to ±V REF DIR (Address 05H) Direction Control for Data I/O
(default). Reset Value = FFH
1 = Full-Scale Input Range equal to ±1/2 VREF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

NOTE: This allows reference voltages as high as DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
VDD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0. Each bit controls whether the corresponding data I/O pin is
bit 1-0 DR1: DR0: Data Rate an output (= 0) or input (= 1). The default power-up state is
(fOSC = 2.4576MHz, SPEED = 0) as inputs.
00 = 15Hz (default) Bits 4 to 7 are not used in ADS1242.
01 = 7.5Hz
10 = 3.75Hz IOCON (Address 06H) I/O Configuration Register
11 = Reserved Reset Value = 00H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

bit 7-0 IO7: IO0: Data I/O Configuration

0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bits 4 to 7 are not used in ADS1242.

OCR0 (Address 07H) Offset Calibration Coefficient

(Least Significant Byte)
Reset Value = 00H

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00

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OCR1 (Address 08H) Offset Calibration Coefficient FSR2 (Address 0CH) Full-Scale Register
(Middle Byte) (Most Significant Byte)
Reset Value = 00H Reset Value = 55H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16

OCR2 (Address 09H) Offset Calibration Coefficient DOR2 (Address 0DH) Data Output Register
(Most Significant Byte) (Most Significant Byte) (Read Only)
Reset Value = 00H Reset Value = 00H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16

FSR0 (Address 0AH) Full-Scale Register DOR1 (Address 0EH) Data Output Register
(Least Significant Byte) (Middle Byte) (Read Only)
Reset Value = 59H Reset Value = 00H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR09 DOR08

FSR1 (Address 0BH) Full-Scale Register DOR0 (Address 0FH) Data Output Register
(Middle Byte) (Least Significant Byte) (Read Only)
Reset Value = 55H Reset Value = 00H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 DOR07 DOR06 DOR05 DOR04 DOR03 DOR02 DOR01 DOR00

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ADS1242 AND ADS1243 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of Operands:
the ADS1242 and ADS1243. Some of the commands are n = count (0 to 127)
stand-alone commands (for example, RESET) while others
require additional bytes (for example, WREG requires the r = register (0 to 15)
count and data bytes). x = don’t care

COMMANDS DESCRIPTION OP CODE 2nd COMMAND BYTE

RDATA Read Data 0000 0001 (01H) —
RDATAC Read Data Continuously 0000 0011 (03H) —
STOPC Stop Read Data Continuously 0000 1111 (0FH) —
RREG Read from REG “rrrr” 0001 r r r r (1xH) xxxx_nnnn (# of regs-1)
WREG Write to REG “rrrr” 0101 r r r r (5xH) xxxx_nnnn (# of regs-1)
SELFCAL Offset and Gain Self Cal 1111 0000 (F0H) —
SELFOCAL Self Offset Cal 1111 0001 (F1H) —
SELFGCAL Self Gain Cal 1111 0010 (F2H) —
SYSOCAL Sys Offset Cal 1111 0011 (F3H) —
SYSGCAL Sys GainCal 1111 0100 (F4H) —
WAKEUP Wakup from SLEEP Mode 1111 1011 (FB H) —
DSYNC Sync DRDY 1111 1100 (FCH) —
SLEEP Put in SLEEP Mode 1111 1101 (FDH) —
RESET Reset to Power-Up Values 1111 1110 (FEH) —

NOTE: The received data format is always MSB first; the data out format is set by the BIT ORDER bit in the ACR register.

TABLE IV. Command Summary.

RDATA–Read Data RDATAC–Read Data Continuous

Description: Read the most recent conversion result from the Description: Read Data Continuous mode enables the con-
Data Output Register (DOR). This is a 24-bit value. tinuous output of new data on each DRDY. This command
Operands: None eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOPC
Bytes: 1
command or the RESET command. Wait at least 10 fOSC after
Encoding: 0000 0001
DRDY falls before reading.
Data Transfer Sequence:
Operands: None
Bytes: 1
DIN 0000 0001 • • •(1) xxxx xxxx xxxx xxxx xxxx xxxx Encoding: 0000 0011
Data Transfer Sequence:
DOUT MSB Mid-Byte LSB Command terminated when “uuuu uuuu” equals STOPC or
RESET.
NOTE: (1) For wait time, refer to timing specification.
DRDY

DIN 0000 0011 • • •(1) uuuu uuuu uuuu uuuu uuuu uuuu

•••
DOUT MSB Mid-Byte LSB

DRDY •••

DOUT MSB Mid-Byte LSB

NOTE: (1) For wait time, refer to timing specification.

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STOPC–Stop Continuous SELFCAL–Offset and Gain Self Calibration
Description: Ends the continuous data output mode. Issue Description: Starts the process of self calibration. The Offset
after DRDY goes LOW. Calibration Register (OCR) and the Full-Scale Register (FSR)
Operands: None are updated with new values after this operation.
Bytes: 1 Operands: None
Encoding: 0000 1111 Bytes: 1
Data Transfer Sequence: Encoding: 1111 0000
Data Transfer Sequence:
DRDY

DIN 1111 0000

DIN xxx 0000 1111

RREG–Read from Registers SELFOCAL–Offset Self Calibration

Description: Output the data from up to 16 registers starting Description: Starts the process of self-calibration for offset.
with the register address specified as part of the instruction. The Offset Calibration Register (OCR) is updated after this
The number of registers read will be one plus the second byte operation.
count. If the count exceeds the remaining registers, the ad- Operands: None
dresses wrap back to the beginning. Bytes: 1
Operands: r, n Encoding: 1111 0001
Bytes: 2 Data Transfer Sequence:
Encoding: 0001 rrrr xxxx nnnn
Data Transfer Sequence:
DIN 1111 0001
Read Two Registers Starting from Register 01H (MUX)

DIN 0001 0001 0000 0001 • • •(1) xxxx xxxx xxxx xxxx
SELFGCAL–Gain Self Calibration
Description: Starts the process of self-calibration for gain.
DOUT MUX ACR
The Full-Scale Register (FSR) is updated with new values after
NOTE: (1) For wait time, refer to timing specification. this operation.
Operands: None
Bytes: 1
WREG–Write to Registers
Encoding: 1111 0010
Description: Write to the registers starting with the register Data Transfer Sequence:
address specified as part of the instruction. The number of
registers that will be written is one plus the value of the second
byte. DIN 1111 0010

Operands: r, n
Bytes: 2
Encoding: 0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 04H (DIO)

DIN 0101 0100 xxxx 0001 Data for DIO Data for DIR

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SYSOCAL–System Offset Calibration DSYNC–Sync DRDY
Description: Initiates a system offset calibration. The input Description: Synchronizes the ADS1242 and ADS1243 to an
should be set to 0V, and the ADS1242 and ADS1243 compute external event.
the OCR value that compensates for offset errors. The Offset Operands: None
Calibration Register (OCR) is updated after this operation. The
Bytes: 1
user must apply a zero input signal to the appropriate analog
inputs. The OCR register is automatically updated afterwards. Encoding: 1111 1100
Data Transfer Sequence:
Operands: None
Bytes: 1
DIN 1111 1100
Encoding: 1111 0011
Data Transfer Sequence:

SLEEP–Sleep Mode
DIN 1111 0011
Description: Puts the ADS1242 and ADS1243 into a low
power sleep mode. To exit sleep mode, issue the WAKEUP
SYSGCAL–System Gain Calibration command.
Operands: None
Description: Starts the system gain calibration process. For
a system gain calibration, the input should be set to the Bytes: 1
reference voltage and the ADS1242 and ADS1243 compute Encoding: 1111 1101
the FSR value that will compensate for gain errors. The FSR Data Transfer Sequence:
is updated after this operation. To initiate a system gain
calibration, the user must apply a full-scale input signal to the
DIN 1111 1101
appropriate analog inputs. FCR register is updated automati-
cally.
Operands: None RESET–Reset to Default Values
Bytes: 1
Description: Restore the registers to their power-up values.
Encoding: 1111 0100
This command stops the Read Continuous mode.
Data Transfer Sequence:
Operands: None
Bytes: 1
DIN 1111 0100
Encoding: 1111 1110
Data Transfer Sequence:

WAKEUP
DIN 1111 1110
Description: Wakes the ADS1242 and ADS1243 from SLEEP
mode.
Operands: None
Bytes: 1
Encoding: 1111 1011
Data Transfer Sequence:

DIN 1111 1011

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APPLICATION EXAMPLES load cell output can be directly applied to the differential
inputs of ADS1242.
GENERAL-PURPOSE WEIGHT SCALE
Figure 8 shows a typical schematic of a general-purpose HIGH PRECISION WEIGHT SCALE
weight scale application using the ADS1242. In this ex- Figure 9 shows the typical schematic of a high-precision
ample, the internal PGA is set to either 64 or 128 (depending weight scale application using the ADS1242. The front-end
on the maximum output voltage of the load cell) so that the differential amplifier helps maximize the dynamic range.

2.7V ~ 5.25V
EMI Filter

VDD VDD
VREF+

EMI Filter
AIN0

Load Cell DRDY

SCLK
MSP430x4xx
DOUT
ADS1242 SPI or other
DOUT Microprocessor

CS

EMI Filter
AIN1

XIN MCLK

VREF– XOUT
GND GND
EMI Filter

FIGURE 8. Schematic of a General-Purpose Weight Scale.

2.7V ~ 5.25V 2.7V ~ 5.25V

EMI Filter

VDD VDD
VREF+

EMI Filter
RI
OPA2335 AIN0
Load Cell
RF DRDY
SCLK
MSP430x4xx
CI ADS1242 DOUT
RG SPI or other
ADS1243
DIN Microprocessor
RF
CS

RI
EMI Filter OPA2335 AIN1

XIN MCLK
XOUT
VREF–
GND GND
EMI Filter

G = 1 + 2 • RF/RG

FIGURE 9. Block Diagram for a High-Precision Weight Scale.

ADS1242, 1243 21
SBAS235H www.ti.com
DEFINITION OF TERMS fMOD =
fosc
=
fosc
mfactor 128 • 2 SPEED
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows: PGA SETTING SAMPLING FREQUENCY

1, 2, 4, 8 fOSC
Analog Input Voltage—the voltage at any one analog input f SAMP =
mfactor
relative to GND.
fOSC • 2
16 f SAMP =
Analog Input Differential Voltage—given by the following mfactor
equation: (IN+) – (IN–). Thus, a positive digital output is fOSC • 4
32 f SAMP =
produced whenever the analog input differential voltage is mfactor
positive, while a negative digital output is produced whenever fOSC • 8
64, 128 f SAMP =
the differential is negative. mfactor

For example, when the converter is configured with a 2.5V

reference and placed in a gain setting of 1, the positive fSAMP—the frequency, or switching speed, of the input sam-
full-scale output is produced when the analog input differen- pling capacitor. The value is given by one of the following
tial is 2.5V. The negative full-scale output is produced when equations:
the differential is –2.5V. In each case, the actual input
voltages must remain within the GND to VDD range. fDATA—the frequency of the digital output data produced by
the ADS1242 and ADS1243, fDATA is also referred to as the
Conversion Cycle—the term conversion cycle usually refers
Data Rate.
to a discrete A/D conversion operation, such as that per-
formed by a successive approximation converter. As used Full-Scale Range (FSR)—as with most A/D converters, the
here, a conversion cycle refers to the tDATA time period. full-scale range of the ADS1242 and ADS1243 is defined as
the input, that produces the positive full-scale digital output
Data Rate—The rate at which conversions are completed.
minus the input, that produces the negative full-scale digital
See definition for fDATA.
output.
fosc For example, when the converter is configured with a 2.5V
fDATA =
128 • 2 SPEED
• 1280 • 2 DR reference and is placed in a gain setting of 2, the full-scale
SPEED = 0, 1 range is: [1.25V (positive full-scale) minus –1.25V (negative
DR = 0, 1, 2 full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight—this is the theoretical
fOSC—the frequency of the crystal oscillator or CMOS com- amount of voltage that the differential voltage at the analog
patible input signal at the XIN input of the ADS1242 and input has to change in order to observe a change in the
ADS1243. output data of one least significant bit. It is computed as
fMOD—the frequency or speed at which the modulator of the follows:
ADS1242 and ADS1243 is running. This depends on the
Full − ScaleRange
SPEED bit as given by the following equation: LSB Weight =
2N – 1

SPEED = 0 SPEED = 1 where N is the number of bits in the digital output.

mfactor 128 256
tDATA—the inverse of fDATA, or the period between each data
output.

+5V SUPPLY ANALOG INPUT(1) GENERAL EQUATIONS

DIFFERENTIAL PGA OFFSET FULL-SCALE DIFFERENTIAL PGA SHIFT
GAIN SETTING FULL-SCALE RANGE INPUT VOLTAGES(2) RANGE RANGE INPUT VOLTAGES(2) RANGE
1 5V ±2.5V ±1.25V
2 2.5V ±1.25V ±0.625V
4 1.25V ±0.625V ±312.5mV
8 0.625V ±312.5mV ±156.25mV RANGE = 0
16 312.5mV ±156.25mV ±78.125mV VREF ± VREF ± VREF
32 156.25mV ±78.125mV ±39.0625mV PGA 2 • PGA 4 • PGA
64 78.125mV ±39.0625mV ±19.531mV
128 39.0625mV ±19.531mV ±9.766mV RANGE = 1

NOTES: (1) With a +2.5V reference. (2) Refer to electrical specification for analog input voltage range.

TABLE VI. Full-Scale Range versus PGA Setting.

22
ADS1242, 1243
www.ti.com SBAS235H
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

10/13 H 21 Application Examples Changed Figure 9; switched plus and minus in upper op amp.
10 Overview Changed 1st paragraph of Input Multiplexer subsection.
2/07 G
15 Registers Deleted 1xxx from Mux Register definition.
12/06 F 14 Overview Added DSYNC Operation subsection.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

ADS1242, 1243 23
SBAS235H www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ADS1242IPWR ACTIVE TSSOP PW 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS
1242
ADS1242IPWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS
1242
ADS1243IPWR ACTIVE TSSOP PW 20 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243

ADS1243IPWRG4 ACTIVE TSSOP PW 20 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243

ADS1243IPWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243

ADS1243IPWTG4 ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1243

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS1243 :

NOTE: Qualified Version Definitions:

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1242IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
ADS1242IPWT TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
ADS1243IPWR TSSOP PW 20 2500 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
ADS1243IPWT TSSOP PW 20 250 180.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1242IPWR TSSOP PW 16 2500 367.0 367.0 35.0
ADS1242IPWT TSSOP PW 16 250 210.0 185.0 35.0
ADS1243IPWR TSSOP PW 20 2500 356.0 356.0 35.0
ADS1243IPWT TSSOP PW 20 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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