Ads1241 Datasheet

ADS
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ADS1240
ADS
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ADS1241
SBAS173F – JUNE 2001 – REVISED OCTOBER 2013
24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES DESCRIPTION
● 24 BITS NO MISSING CODES The ADS1240 and ADS1241 are precision, wide dynamic range,
● SIMULTANEOUS 50Hz AND 60Hz REJECTION delta-sigma, Analog-to-Digital (A/D) converters with 24-bit resolution
(–90dB MINIMUM) operating from 2.7V to 5.25V power supplies. The delta-sigma A/D
● 0.0015% INL converter provides up to 24 bits of no missing code performance and
effective resolution of 21 bits.
● 21 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128) The input channels are multiplexed. Internal buffering can be
selected to provide very high input impedance for direct connection
● PGA GAINS FROM 1 TO 128 to transducers or low-level voltage signals. Burnout current sources
● SINGLE CYCLE SETTLING are provided that allow for detection of an open or shorted sensor.
● PROGRAMMABLE DATA OUTPUT RATES An 8-bit Digital-to-Analog (D/A) converter provides an offset cor-
● EXTERNAL DIFFERENTIAL REFERENCE rection with a range of 50% of the Full-Scale Range (FSR).
OF 0.1V TO 5V The Programmable Gain Amplifier (PGA) provides selectable gains of
● ON-CHIP CALIBRATION 1 to 128, with an effective resolution of 19 bits at a gain of 128. The
A/D conversion is accomplished with a 2nd-order delta-sigma modu-
● SPI™ COMPATIBLE
lator and programmable Finite-Impulse Response (FIR) filter that
● 2.7V TO 5.25V SUPPLY RANGE provides a simultaneous 50Hz and 60Hz notch. The reference input
● 600µW POWER CONSUMPTION is differential and can be used for ratiometric conversion.
● UP TO EIGHT INPUT CHANNELS The serial interface is SPI compatible. Up to eight bits of data
● UP TO EIGHT DATA I/O I/O are also provided that can be used for input or output. The
ADS1240 and ADS1241 are designed for high-resolution measure-
ment applications in smart transmitters, industrial process control,
APPLICATIONS weigh scales, chromatography, and portable instrumentation.
● INDUSTRIAL PROCESS CONTROL
● WEIGH SCALES AVDD AGND VREF+ VREF– XIN XOUT
● LIQUID /GAS CHROMATOGRAPHY

● BLOOD ANALYSIS AVDD
Clock Generator
● SMART TRANSMITTERS
2µA Offset
● PORTABLE INSTRUMENTATION DAC
AIN0/D0
AIN1/D1 A = 1:128
AIN2/D2
AIN3/D3 2nd-Order Digital
MUX BUF + PGA Controller Registers
Modulator Filter
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7 POL
AINCOM SCLK
Serial Interface DIN
ADS1241
Only DOUT
2µA
CS
AGND
BUFEN DVDD DGND PDWN DSYNC RESET DRDY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001-2006, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
AVDD to DGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V DISCHARGE SENSITIVITY
Input Current ............................................................... 100mA, Momentary
DGND to AGND .................................................................... –0.3V to 0.3V This integrated circuit can be damaged by ESD. Texas Instru-
Input Current ................................................................. 10mA, Continuous ments recommends that all integrated circuits be handled with
AIN ................................................................. AGND –0.5V to AVDD + 0.5V appropriate precautions. Failure to observe proper handling
Digital Input Voltage to DGND ................................. –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND .............................. –0.3V to DVDD + 0.3V and installation procedures can cause damage.
Maximum Junction Temperature ................................................... +150°C
ESD damage can range from subtle performance degradation
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +150°C to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade changes could cause the device not to meet its published
device reliability. specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
DIGITAL CHARACTERISTICS: –40°C to +85°C, DVDD 2.7V to 5.25V

PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Input/Output
Logic Family CMOS
Logic Level: VIH 0.8 • DVDD DVDD V
VIL DGND 0.2 • DVDD V
VOH IOH = 1mA DVDD – 0.4 V
VOL IOL = 1mA DGND DGND + 0.4 V
Input Leakage: IIH VI = DVDD 10 µA
IIL VI = 0 –10 µA
Master Clock Rate: fOSC 1 5 MHz
Master Clock Period: tOSC 1/fOSC 200 1000 ns
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ADS1240, 1241
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ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +2.5V, unless otherwise specified.
ADS1240
ADS1241
ANALOG INPUT (AIN0 – AIN7, AINCOM)

Analog Input Range Buffer OFF AGND – 0.1 AVDD + 0.1 V
Buffer ON AGND + 0.05 AVDD – 1.5 V
Full-Scale Input Range (In+) – (In–), See Block Diagram, RANGE = 0 ±VREF /PGA V
RANGE = 1 ±VREF /(2 • PGA) V
Differential Input Impedance Buffer OFF 5/PGA MΩ
Buffer ON 5 GΩ
Bandwidth
fDATA = 3.75Hz –3dB 1.65 Hz
fDATA = 15.00Hz –3dB 14.6 Hz
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9 pF
Input Leakage Current Modulator OFF, T = 25°C 5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range RANGE = 0 ±VREF /(2 • PGA) V
Offset Monotonicity 8 Bits

Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 1 ppm/°C
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error (1) 7.5 ppm of FS
Offset Drift(1) 0.02 ppm of FS/°C
Gain Error 0.005 %
Gain Error Drift(1) 0.5 ppm/°C
Common-Mode Rejection at DC 100 dB
fCM = 60Hz, fDATA = 15Hz 130 dB
Normal-Mode Rejection fSIG = 50Hz, fDATA = 15Hz 100 dB
fSIG = 60Hz, fDATA = 15Hz 100 dB
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆VOUT /∆VDD)(2) 80 95 dB
VOLTAGE REFERENCE INPUT
VREF VREF ≡ (REF IN+) – (REF IN–), RANGE = 0 0.1 2.5 2.6 V
Reference Input Range REF IN+, REF IN– 0 AVDD V
RANGE = 1 0.1 AVDD V
Common-Mode Rejection fVREFCM = 60Hz, fDATA = 15Hz 120 dB
Bias Current(3) VREF = 2.5V 1.3 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AVDD 4.75 5.25 V
Analog Current PDWN = 0, or SLEEP 1 nA
PGA = 1, Buffer OFF 120 250 µA
PGA = 1, Buffer ON 160 300 µA
Digital Current Normal Mode, DVDD = 5V 80 125 µA
SLEEP Mode, DVDD = 5V 60 µA
Read Data Continuous Mode, DVDD = 5V 230 µA
PDWN 0.5 nA
Power Dissipation PGA = 1, Buffer OFF, DVDD = 5V 1.1 1.9 mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
ADS1240, 1241 3
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ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +1.25V, unless otherwise specified.
ADS1240
ADS1241
ANALOG INPUT (AIN0 – AIN7, AINCOM)

Analog Input Range Buffer OFF AGND – 0.1 AVDD + 0.1 V
Buffer ON AGND + 0.05 AVDD – 1.5 V
Full-Scale Input Voltage Range (In+) – (In–) See Block Diagram, RANGE = 0 ±VREF /PGA V
Input Impedance Buffer OFF 5/PGA MΩ
Differential Buffer ON 5 GΩ
Bandwidth
fDATA = 15.00Hz –3dB 14.6 Hz
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9 pF
Input Leakage Current Modulator OFF, T = 25°C 5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range RANGE = 0 ±VREF /(2 • PGA) V
Offset DAC Monotonicity 8 Bits

Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error(1) 15 ppm of FS
Offset Drift(1) 0.04 ppm of FS/°C
Gain Error 0.01 %
Gain Error Drift(1) 1.0 ppm/°C
Normal-Mode Rejection fSIG = 50Hz, fDATA = 15Hz 100 dB
fSIG = 60Hz, fDATA = 15Hz 100 dB
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆VOUT /∆VDD)(2) 75 90 dB
VOLTAGE REFERENCE INPUT
VREF VREF ≡ (REF IN+) – (REF IN–), RANGE = 0 0.1 1.25 1.30 V
Reference Input Range REF IN+, REF IN– 0 AVDD V
RANGE = 1 0.1 2.5 2.6 V
Common-Mode Rejection fVREFCM = 60Hz, fDATA = 15Hz 120 dB
Bias Current(3) VREF = 1.25 0.65 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AVDD 2.7 3.3 V
Analog Current PDWN = 0, or SLEEP 1 nA
Digital Current Normal Mode, DVDD = 3V 50 100 µA
SLEEP Mode, DVDD = 3V 40 µA
Read Data Continuous Mode, DVDD = 3V 113 µA
PDWN = 0 0.5 nA
Power Dissipation PGA = 1, Buffer OFF, DVDD = 3V 0.6 1.2 mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
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ADS1240, 1241
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PIN CONFIGURATION (ADS1240) PIN CONFIGURATION (ADS1241)
Top View SSOP Top View SSOP
DVDD 1 28 BUFEN
DVDD 1 24 BUFEN DGND 2 27 DRDY
DGND 2 23 DRDY XIN 3 26 SCLK
XIN 3 22 SCLK XOUT 4 25 DOUT
XOUT 4 21 DOUT RESET 5 24 DIN
RESET 5 20 DIN DSYNC 6 23 CS
DSYNC 6 19 CS PDWN 7 22 POL

ADS1240 ADS1241
PDWN 7 18 POL DGND 8 21 AVDD
DGND 8 17 AVDD VREF+ 9 20 AGND
VREF+ 9 16 AGND VREF– 10 19 AINCOM
VREF– 10 15 AINCOM AIN0/D0 11 18 AIN3/D3
AIN0/D0 11 14 AIN3/D3 AIN1/D1 12 17 AIN2/D2
AIN1/D1 12 13 AIN2/D2 AIN4/D4 13 16 AIN7/D7
AIN5/D5 14 15 AIN6/D6
PIN DESCRIPTIONS (ADS1240) PIN DESCRIPTIONS (ADS1241)

PIN PIN
NUMBER NAME DESCRIPTION NUMBER NAME DESCRIPTION
1 DVDD Digital Power Supply 1 DVDD Digital Power Supply

2 DGND Digital Ground
3 XIN Clock Input
3 XIN Clock Input 4 XOUT Clock Output, used with external crystals.
4 XOUT Clock Output, used with external crystals. 5 RESET Active LOW, resets the entire device.
5 RESET Active LOW, resets the entire device. 6 DSYNC Active LOW, Synchronization Control
6 DSYNC Active LOW, Synchronization Control 7 PDWN Active LOW, Power Down. The power down func-
7 PDWN Active LOW, Power Down. The power down func- tion shuts down the analog and digital circuits.
tion shuts down the analog and digital circuits. 8 DGND Digital Ground
9 VREF+ Positive Differential Reference Input
10 VREF– Negative Differential Reference Input
9 VREF+ Positive Differential Reference Input
11 AIN0/D0 Analog Input 0 / Data I/O 0
10 VREF– Negative Differential Reference Input 12 AIN1/D1 Analog Input 1 / Data I/O 1
11 AIN0/D0 Analog Input 0 / Data I/O 0 13 AIN4/D4 Analog Input 4 / Data I/O 4
15 AINCOM Analog Input Common, connect to AGND if unused.
16 AGND Analog Ground 19 AINCOM Analog Input Common, connect to AGND if unused.
17 AVDD Analog Power Supply 20 AGND Analog Ground
18 POL Serial Clock Polarity 21 AVDD Analog Power Supply
19 CS Active LOW, Chip Select 22 POL Serial Clock Polarity
20 DIN Serial Data Input, Schmitt Trigger 23 CS Active LOW, Chip Select
24 DIN Serial Data Input, Schmitt Trigger
21 DOUT Serial Data Output
25 DOUT Serial Data Output
22 SCLK Serial Clock, Schmitt Trigger 26 SCLK Serial Clock, Schmitt Trigger
23 DRDY Active LOW, Data Ready 27 DRDY Active LOW, Data Ready
24 BUFEN Buffer Enable 28 BUFEN Buffer Enable
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SBAS173F www.ti.com
TIMING DIAGRAMS
CS
t3 t1 t2 t10
SCLK
(POL = 0)
SCLK
(POL = 1)
t4 t5 t6 t2
t11
DIN MSB LSB
t7 t8 t9
(Command or Command and Data)
DOUT MSB(1) LSB(1)
NOTE: (1) Bit order = 0.
SCLK Reset Waveform ADS1240 or ADS1241

Resets On
Falling Edge 300 • tOSC < t12 < 500 • tOSC
t13 t13 t13 : > 5 • tOSC
SCLK 550 • tOSC < t14 < 750 • tOSC
1050 • tOSC < t15 < 1250 • tOSC
t12 t14 t15
DIAGRAM 1.
t16
tDATA
DRDY RESET, DSYNC, PDWN

t17 t18
SCLK
t19
DIAGRAM 2.
TIMING CHARACTERISTICS TABLE

SPEC DESCRIPTION MIN MAX UNITS
t1 SCLK Period 4 tOSC Periods

3 DRDY Periods
t2 SCLK Pulse Width, HIGH and LOW 200 ns
t3 CS low to first SCLK Edge; Setup Time(2) 0 ns
t4 DIN Valid to SCLK Edge; Setup Time 50 ns
t5 Valid DIN to SCLK Edge; Hold Time 50 ns
t6 Delay between last SCLK edge for DIN and first SCLK edge for DOUT:
RDATA, RDATAC, RREG, WREG 50 tOSC Periods
t7(1) SCLK Edge to Valid New DOUT 50 ns
t8(1) SCLK Edge to DOUT, Hold Time 0 ns
t9 Last SCLK Edge to DOUT Tri-State 6 10 tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10 CS LOW time after final SCLK edge.
Read from the device 0 tOSC Periods
Write to the device 8 tOSC Periods
t11 Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC 4 tOSC Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 2 DRDY Periods
SELFCAL 4 DRDY Periods
RESET (also SCLK Reset or RESET Pin) 16 tOSC Periods
t16 Pulse Width 4 tOSC Periods
t17 Allowed analog input change for next valid conversion. 5000 tOSC Periods
t18 DOR update, DOR data not valid. 4 tOSC Periods
t19 First SCLK after DRDY goes LOW:
RDATAC Mode 10 tOSC Periods
Any other mode 0 tOSC Periods
NOTES: (1) Load = 20pF 10kΩ to DGND.

(2) CS may be tied LOW.
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ADS1240, 1241
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TYPICAL CHARACTERISTICS
All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS vs PGA SETTING EFFECTIVE NUMBER OF BITS vs PGA SETTING
21.5 22
DR = 10
21.0 21
20.5 DR = 10
DR = 01 20
20.0
ENOB (rms)
ENOB (rms)
19.5 19
DR = 01
19.0 18
DR = 00
18.5 DR = 00
17
18.0 Buffer ON
Buffer OFF 16
17.5
17.0 15
1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128
PGA Setting PGA Setting
EFFECTIVE NUMBER OF BITS vs PGA SETTING NOISE vs INPUT SIGNAL

20.5 2.0
20.0 1.8
DR = 10
19.5 1.6
Noise (rms, ppm of FS)
1.4
19.0
ENOB (rms)
DR = 01 1.2
18.5
1.0
18.0
0.8
DR = 00
17.5
0.6
17.0 0.4
Buffer OFF, VREF = 1.25V
16.5 0.2
16.0 0
1 2 4 8 16 32 64 128 –2.5 –1.5 –0.5 0.5 1.5 2.5
PGA Setting VIN (V)
COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO

vs FREQUENCY vs FREQUENCY
140 140
120 120
100 100
CMRR (dB)
PSRR (dB)
80 80
60 60
40 40
20 20
Buffer ON Buffer ON
0 0
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Frequency of Power Supply (Hz) Frequency of Power Supply (Hz)
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SBAS173F www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
OFFSET vs TEMPERATURE GAIN vs TEMPERATURE

(Cal at 25°C) (Cal at 25°C)
50 1.00010
PGA1 PGA16
1.00006
0
Gain (Normalized)
Offset (ppm of FS)
1.00002
–50
0.99998
PGA64
–100
0.99994
PGA128
–150
0.99990
–200 0.99986
–50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90
Temperature (°C) Temperature (°C)
INTEGRAL NONLINEARITY vs INPUT SIGNAL ANALOG CURRENT vs TEMPERATURE

10 150
8 140
–40°C AVDD = 5
6 130
4 120
INL (ppm of FS)
+85°C
Current (µA)
2 110
0 100
AVDD = 3
–2 90
–4 80
+25°C
–6 70
Buffer OFF
–8 60
–10 50
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 –50 –30 –10 10 30 50 70 90
VIN (V) Temperature (°C)
ANALOG CURRENT vs PGA DIGITAL CURRENT vs SUPPLY

900 300
AVDD = 5V, Buffer = ON
800
Buffer = OFF 250
700
600 200
Normal
IANALOG (µA)
SLEEP
IDIGITAL (µA)
Normal
500 4.91MHz 4.91MHz 2.45MHz
AVDD = 3V, Buffer = ON 150
400
Buffer = OFF
300 100
200
50
100 SLEEP
Power Down 2.45MHz
0 0
1 2 4 8 16 32 64 128 3.0 3.5 4.0 4.5 5.0
PGA Setting VDD (V)
8
ADS1240, 1241
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TYPICAL CHARACTERISTICS (Cont.)
OFFSET DAC
OFFSET vs TEMPERATURE
NOISE HISTOGRAM (Cal at 25°C)
3500 200
10k Readings
VIN = 0V 170
3000
140
Number of Occurrences
Offset (ppm of FSR)

2500 110
80
2000
50
1500 20
–10
1000
–40
500 –70
–100
0 –50 –30 –10 10 30 50 70 90
–3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Temperature (°C)
ppm of FS
OFFSET DAC
GAIN vs TEMPERATURE OFFSET DAC
(Cal at 25°C) NOISE vs SETTING
1.00020 0.8
1.00016
0.7
1.00012
Noise (rms, ppm of FS) 0.6
1.00008
Gain (Normalized)
1.00004 0.5
1.00000
0.4
0.99996
0.99992 0.3
0.99988
0.2
0.99984
0.99980 0.1
0.99976 0
–50 –30 –10 10 30 50 70 90 –128 –96 –64 –32 0 32 64 96 128
Temperature (°C) Offset DAC Setting
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SBAS173F www.ti.com
OVERVIEW channel. With this method, it is possible to have up to eight
single-ended input channels or four independent differential
INPUT MULTIPLEXER input channels for the ADS1241, and four single-ended input
The input multiplexer provides for any combination of differ- channels or two independent differential input channels for
ential inputs to be selected on any of the input channels, as the ADS1240. Note that AINCOM can be treated as an input
shown in Figure 1. For example, if AIN0 is selected as the channel.
positive differential input channel, any other channel can be The ADS1240 and ADS1241 feature a single-cycle settling
selected as the negative terminal for the differential input digital filter that provides valid data on the first conversion
after a new channel selection. In order to minimize the
settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY. In
AIN0/D0 other words, issuing a MUX change through the WREG
command immediately after DRDY goes LOW minimizes the
settling error. Increasing the time between the conversion
AIN1/D1
AVDD
beginning (DRDY goes LOW) and the MUX change com-
mand (tDELAY) results in a settling error in the conversion
Burnout Current Source
AIN2/D2 data, as shown in Figure 2.
AIN3/D3 BURNOUT CURRENT SOURCES

The Burnout Current Sources can be used to detect sensor
Input
AIN4/D4 Buffer
short-circuit or open-circuit conditions. Setting the Burnout
Current Sources (BOCS) bit in the SETUP register activates
two 2µA current sources called burnout current sources. One
AIN5/D5
of the current sources is connected to the converter’s nega-
Burnout Current Source
tive input and the other is connected to the converter’s
AIN6/D6 positive input.
AGND
Figure 3 shows the situation for an open-circuit sensor. This
AIN7/D7 is a potential failure mode for many kinds of remotely con-
nected sensors. The current source on the positive input acts
as a pull-up, causing the positive input to go to the positive
ADS1241 AINCOM
Only analog supply, and the current source on the negative input
acts as a pull-down, causing the negative input to go to
ground. The ADS1240/41 therefore outputs full-scale (7FFFFF
FIGURE 1. Input Multiplexer Configuration. Hex).
New Conversion Begins, Previous Conversion Data

Complete Previous Conversion New Conversion Complete
DRDY
tDELAY
SCLK
(POL = 0)
DIN MSB LSB
SETTLING ERROR vs DELAY TIME

fCLK = 2.4576MHz
10.000000
1.000000
0.100000
Settling Error (%)
0.010000
0.001000
0.000100
0.000010
0.000001
0 2 4 6 8 10 12 14 16
Delay Time, tDELAY (ms)
FIGURE 2. Input Multiplexer Configuration.
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The buffer draws additional current when activated. The
AVDD current required by the buffer depends on the PGA setting.
When the PGA is set to 1, the buffer uses approximately
50µA; when the PGA is set to 128, the buffer uses approxi-
2µA
mately 500µA.
AVDD
PGA
OPEN CIRCUIT ADC CODE = 0x7FFFFFH
The Programmable Gain Amplifier (PGA) can be set to gains
0V of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
effective resolution of the A/D converter. For instance, with a
2µA
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1µV. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. AVDD
current increases with PGA settings higher than 4.
FIGURE 3. Burnout detection while sensor is open-circuited.
OFFSET DAC
Figure 4 shows a short-circuited sensor. Since the inputs are
The input to the PGA can be shifted by half the full-scale input
shorted and at the same potential, the ADS1240/41 signal
range of the PGA using the Offset DAC (ODAC) register. The
outputs are approximately zero. (Note that the code for
ODAC register is an 8-bit value; the MSB is the sign and the
shorted inputs is not exactly zero due to internal series
seven LSBs provide the magnitude of the offset. Using the
resistance, low-level noise and other error sources.)
offset DAC does not reduce the performance of the A/D
converter. For more details on the ODAC, please refer to TI
application report SBAA077.
AVDD
MODULATOR
2µA The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
AVDD/2
the external clock (fOSC). The frequency division is deter-
SHORT mined by the SPEED bit in the SETUP register, as shown in
ADC CODE ≅ 0
CIRCUIT Table I.
AVDD/2
SPEED DR BITS 1st NOTCH

2µA
fOSC BIT fMOD 00 01 10 FREQ.
2.4576MHz 0 19,200Hz 15Hz 7.5Hz 3.75Hz 50/60Hz
1 9,600Hz 7.5Hz 3.75Hz 1.875Hz 25/30Hz
4.9152MHz 0 38,400Hz 30Hz 15Hz 7.5Hz 100/120Hz
1 19,200Hz 15Hz 7.5Hz 3.75Hz 50/60Hz
FIGURE 4. Burnout detection while sensor is short-circuited.
TABLE I. Output Configuration.
INPUT BUFFER
CALIBRATION
The input impedance of the ADS1240/41 without the buffer
enabled is approximately 5MΩ/PGA. For systems requiring The offset and gain errors can be minimized with calibration.
very high input impedance, the ADS1240/41 provides a The ADS1240 and ADS1241 support both self and system
chopper-stabilized differential FET-input voltage buffer. When calibration.
activated, the buffer raises the ADS1240/41 input impedance Self-calibration of the ADS1240 and ADS1241 corrects inter-
to approximately 5GΩ. nal offset and gain errors and is handled by three commands:
The buffer’s input range is approximately 50mV to AVDD – SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL com-
1.5V. The buffer’s linearity will degrade beyond this range. mand performs both an offset and gain calibration. SELFGCAL
Differential signals should be adjusted so that both signals performs a gain calibration and SELFOCAL performs an
are within the buffer’s input range. offset calibration, each of which takes two tDATA periods to
complete. During self-calibration, the ADC inputs are discon-
The buffer can be enabled using the BUFEN pin or the
nected internally from the input pins. The PGA must be set to
BUFEN bit in the ACR register. The buffer is on when the
1 prior to issuing a SELFCAL or SELFGCAL command. Any
BUFEN pin is high and the BUFEN bit is set to one. If the
PGA is allowed when issuing a SELFOCAL command. For
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
example, if using PGA = 64, first set PGA = 1 and issue
set to zero, the buffer is also disabled.
ADS1240, 1241 11
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SELFGCAL. Afterwards set PGA = 64 and issue SELFOCAL.
For operation with a reference voltage greater than (AVDD –
XIN
1.5) volts, the buffer must also be turned off during gain self- C1
calibration to avoid exceeding the buffer input range. Crystal
System calibration corrects both internal and external offset XOUT

and gain errors. While performing system calibration, the C2
appropriate signal must be applied to the inputs. The system

offset calibration command (SYSOCAL) requires a zero input
differential signal (see Table IV, page 18). It then computes
FIGURE 5. Crystal Connection.
the offset that nullifies the offset in the system. The system
gain calibration command (SYSGCAL) requires a positive
full-scale input signal. It then computes a value to nullify the CLOCK PART
gain error in the system. Each of these calibrations takes two SOURCE FREQUENCY C1 C2 NUMBER
tDATA periods to complete. System gain calibration is recom- Crystal 2.4576 0-20pF 0-20pF ECS, ECSD 2.45 - 32
mended for the best gain calibration at higher PGAs. Crystal 4.9152 0-20pF 0-20pF ECS, ECSL 4.91
Crystal 4.9152 0-20pF 0-20pF ECS, ECSD 4.91
Calibration should be performed after power on, a change in
Crystal 4.9152 0-20pF 0-20pF CTS, MP 042 4M9182
temperature, or a change of the PGA. The RANGE bit (ACR bit
2) must be zero during calibration. TABLE II. Recommended Crystals.
Calibration removes the effects of the ODAC; therefore, dis-
able the ODAC during calibration, and enable again after DIGITAL FILTER
calibration is complete. The ADS1240 and ADS1241 have a 1279 tap linear phase
At the completion of calibration, the DRDY signal goes low, Finite Impulse Response (FIR) digital filter that a user can
indicating the calibration is finished. The first data after configure for various output data rates. When a 2.4576MHz
calibration should be discarded since it may be corrupt from crystal is used, the device can be programmed for an output
calibration data remaining in the filter. The second data is data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions,
always valid. the digital filter rejects both 50Hz and 60Hz interference. Figure
6 shows the digital filter frequency response for data output
rates of 15Hz, 7.5Hz, and 3.75Hz.
EXTERNAL VOLTAGE REFERENCE
The ADS1240 and ADS1241 require an external voltage If a different data output rate is desired, a different crystal
reference. The selection for the voltage reference value is frequency can be used. However, the rejection frequencies
made through the ACR register. shift accordingly. For example, a 3.6864MHz master clock with
the default register condition has:
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +VREF (3.6864MHz/2.4576MHz) • 15Hz = 22.5Hz data output rate
and –VREF. The absolute voltage on either pin, +VREF or and the first and second notch is:
–VREF, can range from AGND to AVDD. However, the follow- 1.5 • (50Hz and 60Hz) = 75Hz and 90Hz
ing limitations apply:
For AVDD = 5.0V and RANGE = 0 in the ACR, the differential DATA I/O INTERFACE
VREF must not exceed 2.5V.
The ADS1240 has four pins and the ADS1241 has eight pins
For AVDD = 5.0V and RANGE = 1 in the ACR, the differential that serve a dual purpose as both analog inputs and data
VREF must not exceed 5V. I/O. These pins are powered from AVDD and are configured
For AVDD = 3.0V and RANGE = 0 in the ACR, the differential through the IOCON, DIR, and DIO registers. These pins
VREF must not exceed 1.25V. can be individually configured as either analog inputs or data
For AVDD = 3.0V and RANGE = 1 in the ACR, the differential I/O. See Figure 7 (page 14) for the equivalent schematic of
VREF must not exceed 2.5V. an Analog/Data I/O pin.
The IOCON register defines the pin as either an analog input
CLOCK GENERATOR or data I/O. The power-up state is an analog input. If the pin
is configured as an analog input in the IOCON register, the
The clock source for the ADS1240 and ADS1241 can be DIR and DIO registers have no effect on the state of the pin.
provided from a crystal, oscillator, or external clock. When the
clock source is a crystal, external capacitors must be provided If the pin is configured as data I/O in the IOCON register,
to ensure start-up and stable clock frequency. This is shown in then DIR and DIO are used to control the state of the pin.
both Figure 5 and Table II. XOUT is only for use with external The DIR register controls the direction of the data pin, either
crystals and it should not be used as a clock driver for external as an input or output. If the pin is configured as an input in
the DIR register, then the corresponding DIO register bit
circuitry.
reflects the state of the pin. Make sure the pin is driven to a
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ADS1240 AND ADS1241 FREQUENCY RESPONSE FROM 45Hz to 65Hz
FILTER RESPONSE WHEN fDATA = 15Hz WHEN fDATA = 15Hz
0 –40
–20 –50
–40 –60
–70
–60
Magnitude (dB)
–80
Gain (dB)
–80
–90
–100
–100
–120
–110
–140
–120
–160 –130
–180 –140
0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 65
Frequency (Hz) Frequency (Hz)

FILTER RESPONSE WHEN fDATA = 7.5Hz WHEN fDATA = 7.5Hz
0 –40
–20 –50
–40 –60
–70
–60
Magnitude (dB)
–80
Gain (dB)
–80
–90
–100
–100
–120
–110
–140 –120
–160 –130
–180 –140
0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 65

FILTER RESPONSE WHEN fDATA = 3.75Hz WHEN fDATA = 3.75Hz
0 –40
–20 –50
–40 –60
–60 –70
Magnitude (dB)
–80
Gain (dB)
–80
–90
–100
–100
–120
–110
–140
–120
–160 –130
–180 –140
0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 65
fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1
ATTENUATION
DATA –3dB
OUTPUT RATE BANDWIDTH fIN = 50 ± 0.3Hz fIN = 60 ± 0.3Hz fIN = 50 ± 1Hz fIN = 60 ± 1Hz
15Hz 14.6Hz –80.8dB –87.3dB –68.5dB –76.1dB
7.5Hz 3.44Hz –85.9dB –87.4dB –71.5dB –76.2dB
3.75Hz 1.65Hz –93.8dB –88.6dB –86.8dB –77.3dB
FIGURE 6. Filter Frequency Responses.
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logic one or zero when configured as an input to prevent Data Continuous Mode (RDATAC) command should not be
excess current dissipation. If the pin is configured as an issued when DIN and DOUT are connected. While in RDATAC
output in the DIR register, then the corresponding DIO mode, DIN looks for the STOPC or RESET command. If
register bit value determines the state of the output pin either of these 8-bit bytes appear on DOUT (which is con-
(0 = AGND, 1 = AVDD). nected to DIN), the RDATAC mode ends.
It is still possible to perform A/D conversions on a pin
configured as data I/O. This may be useful as a test mode, DATA READY DRDY PIN
where the data I/O pin is driven and an A/D conversion is
The DRDY line is used as a status signal to indicate when
done on the pin.
data is ready to be read from the internal data register.
DRDY goes LOW when a new data word is available in the
IOCON DOR register. It is reset HIGH when a read operation from
DIR the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
DIO WRITE while the register is being updated.
AINx/Dx The status of DRDY can also be obtained by interrogating bit
To Analog Mux
7 of the ACR register (address 2H). The serial interface can
DIO READ operate in 3-wire mode by tying the CS input LOW. In this
case, the SCLK, DIN, and DOUT lines are used to communi-
cate with the ADS1240 and ADS1241. This scheme is
FIGURE 7. Analog/Data Interface Pin.
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port bit of
SERIAL PERIPHERAL INTERFACE the microcontroller.
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1240 and ADS1241. DSYNC OPERATION
The ADS1240 and ADS1241 operate in slave-only mode.
Synchronization can be achieved either through the DSYNC
The serial interface is a standard four-wire SPI (CS , SCLK,
pin or the DSYNC command. When the DSYNC pin is used,
DIN and DOUT) interface that supports both serial clock
the digital circuitry is reset on the falling edge of DSYNC.
polarities (POL pin).
While DSYNC is LOW, the serial interface is deactivated.
Chip Select (CS ) Reset is released when DSYNC is taken HIGH. Synchroni-
The chip select (CS ) input must be externally asserted zation occurs on the next rising edge of the system clock
before communicating with the ADS1240 or ADS1241. CS after DSYNC is taken HIGH.
must stay LOW for the duration of the communication. When the DSYNC command is sent, the digital filter is reset
Whenever CS goes HIGH, the serial interface is reset. CS on the edge of the last SCLK of the DSYNC command. The
may be hard-wired LOW. modulator is held in RESET until the next edge of SCLK is
Serial Clock (SCLK) detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK following the DSYNC
The serial clock (SCLK) features a Schmitt-triggered input
command.
and is used to clock DIN and DOUT data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within 3 DRDY pulses, the serial POWER-UP—SUPPLY VOLTAGE RAMP RATE
interface resets on the next SCLK pulse and starts a new The power-on reset circuitry was designed to accommodate
communication cycle. A special pattern on SCLK resets the digital supply ramp rates as slow as 1V/10ms. To ensure
entire chip; see the RESET section for additional information. proper operation, the power supply should ramp monotoni-
Clock Polarity (POL) cally.
The clock polarity input (POL) controls the polarity of SCLK.
When POL is LOW, data is clocked on the falling edge of RESET
SCLK and SCLK should be idled LOW. Likewise, when POL The user can reset the registers to their default values in
is HIGH, the data is clocked on the rising edge of SCLK and three different ways: by asserting the RESET pin; by issuing
SCLK should be idled HIGH. the RESET command; or by applying a special waveform on
the SCLK (the SCLK Reset Waveform, as shown in the
Data Input (DIN) and Data Output (DOUT)
Timing Diagram). Note: if both POL and SCLK pins are held
The data input (DIN) and data output (DOUT) receive and send high, applying the SCLK Reset Waveform to the CS pin also
data from the ADS1240 and ADS1241. DOUT is high imped- resets the part.
ance when not in use to allow DIN and DOUT to be connected
together and driven by a bidirectional bus. Note: the Read
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ADS1240 AND ADS1241 tion needed to configure the part, such as data format,
multiplexer settings, calibration settings, data rate, etc. The
REGISTER set of the 16 registers are shown in Table III.
The operation of the device is set up through individual
registers. Collectively, the registers contain all the informa-
ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00H SETUP ID ID ID ID BOCS PGA2 PGA1 PGA0

01H MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
02H ACR DRDY U/B SPEED BUFEN BIT ORDER RANGE DR1 DR0
03H ODAC SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
04H DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0
05H DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0
06H IOCON IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
07H OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
0AH FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
0BH FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08
0CH FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
0DH DOR2 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
0EH DOR1 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR09 DOR08
0FH DOR0 DOR07 DOR16 FSR21 DOR04 DOR03 DOR02 DOR01 DOR00
TABLE III. Registers.
DETAILED REGISTER DEFINITIONS MUX (Address 01H) Multiplexer Control Register

SETUP (Address 00H) Setup Register Reset Value = 01H
Reset Value = iiii0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
ID ID ID ID BOCS PGA2 PGA1 PGA0
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
bit 7-4 Factory Programmed Bits Select
bit 3 BOCS: Burnout Current Source 0000 = AIN0 (default)
0 = Disabled (default) 0001 = AIN1
1 = Enabled 0010 = AIN2
0011 = AIN3
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier
0100 = AIN4
Gain Selection
0101 = AIN5
000 = 1 (default)
0110 = AIN6
001 = 2
0111 = AIN7
010 = 4
1xxx = AINCOM (except when xxx = 111)
011 = 8
1111 = Reserved
100 = 16
101 = 32 bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
110 = 64 Select
111 = 128 0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
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ACR (Address 02H) Analog Control Register ODAC (Address 03 ) Offset DAC
Reset Value = X0H Reset Value = 00H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DRDY U/B SPEED BUFEN BIT ORDER RANGE DR1 DR0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
bit 7 DRDY: Data Ready (Read Only)

bit 7 Sign
This bit duplicates the state of the DRDY pin.
0 = Positive
bit 6 U/B: Data Format 1 = Negative
0 = Bipolar (default)
1 = Unipolar VREF  OSET [6 : 0] 
Offset = •  RANGE = 0
2 • PGA  127 
U/B ANALOG INPUT DIGITAL OUTPUT (Hex)
+FSR 0x7FFFFF
VREF  OSET [6 : 0] 
0 Zero 0x000000 Offset = •  RANGE = 1
–FSR 0x800000 4 • PGA  127 
+FSR 0xFFFFFF
1 Zero 0x000000
NOTE: The offset DAC must be enabled after calibration or the calibration
–FSR 0x000000
nullifies the effects.
bit 5 SPEED: Modulator Clock Speed

DIO (Address 04H) Data I/O
0 = fMOD = fOSC/128 (default)
Reset Value = 00H
1 = fMOD = fOSC/256
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 4 BUFEN: Buffer Enable
0 = Buffer Disabled (default) DIO 7 DIO 6 DIO 5 DIO 4 DIO 3 DIO 2 DIO 1 DIO 0
1 = Buffer Enabled
If the IOCON register is configured for data, a value written
bit 3 BIT ORDER: Data Output Bit Order to this register appears on the data I/O pins if the pin is
0 = Most Significant Bit Transmitted First (default) configured as an output in the DIR register. Reading this
1 = Least Significant Bit Transmitted First register returns the value of the data I/O pins.
This configuration bit controls only the bit order Bit 4 to bit 7 is not used in ADS1240.
within the byte of data that is shifted out. Data is
always shifted out of the part most significant byte DIR (Address 05H) Direction Control for Data I/O
first. Data is always shifted into the part most Reset Value = FFH
significant bit first. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 2 RANGE: Range Select DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
0 = Full-Scale Input Range equal to ±V REF
(default). Each bit controls whether the corresponding data I/O pin is
1 = Full-Scale Input Range equal to ±1/2 VREF an output (= 0) or input (= 1). The default power-up state is
NOTE: This allows reference voltages as high as as inputs.
AVDD, but even with a 5V reference voltage the Bit 4 to bit 7 is not used in ADS1240.
calibration must be performed with this bit set to 0.
bit 1-0 DR1: DR0: Data Rate IOCON (Address 06H) I/O Configuration Register
(fOSC = 2.4576MHz, SPEED = 0) Reset Value = 00H
00 = 15Hz (default) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 = 7.5Hz
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
10 = 3.75Hz
11 = Reserved bit 7-0 IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bit 4 to bit 7 is not used in ADS1240.
OCR0 (Address 07H) Offset Calibration Coefficient

(Least Significant Byte)
Reset Value = 00H
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
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OCR1 (Address 08H) Offset Calibration Coefficient FSR2 (Address 0CH) Full-Scale Register
(Middle Byte) (Most Significant Byte)
Reset Value = 00H Reset Value = 55H
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
OCR2 (Address 09H) Offset Calibration Coefficient DOR2 (Address 0DH) Data Output Register
(Most Significant Byte) (Most Significant Byte) (Read Only)
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
FSR0 (Address 0AH) Full-Scale Register DOR1 (Address 0EH) Data Output Register
(Least Significant Byte) (Middle Byte) (Read Only)
FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR09 DOR08
FSR1 (Address 0BH) Full-Scale Register DOR0 (Address 0FH) Data Output Register
(Middle Byte) (Least Significant Byte) (Read Only)
FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 DOR07 DOR06 DOR05 DOR04 DOR03 DOR02 DOR01 DOR00
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ADS1240 AND ADS1241 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of Operands:
the ADS1240 and ADS1241. Some of the commands are n = count (0 to 127)
stand-alone commands (e.g., RESET) while others require
additional bytes (e.g., WREG requires the count and data r = register (0 to 15)
bytes). x = don’t care
COMMANDS DESCRIPTION OP CODE 2nd COMMAND BYTE

RDATA Read Data 0000 0001 (01H) —
RDATAC Read Data Continuously 0000 0011 (03H) —
STOPC Stop Read Data Continuously 0000 1111 (0FH) —
RREG Read from REG “rrrr” 0001 r r r r (1xH) xxxx_nnnn (# of regs-1)
WREG Write to REG “rrrr” 0101 r r r r (5xH) xxxx_nnnn (# of regs-1)
SELFCAL Offset and Gain Self Cal 1111 0000 (F0H) —
SELFOCAL Self Offset Cal 1111 0001 (F1H) —
SELFGCAL Self Gain Cal 1111 0010 (F2H) —
SYSOCAL Sys Offset Cal 1111 0011 (F3H) —
SYSGCAL Sys GainCal 1111 0100 (F4H) —
WAKEUP Wakup from SLEEP Mode 1111 1011 (FB H) —
DSYNC Sync DRDY 1111 1100 (FCH) —
SLEEP Put in SLEEP Mode 1111 1101 (FDH) —
RESET Reset to Power-Up Values 1111 1110 (FEH) —
NOTE: The received data format is always MSB First; the data out format is set by the BIT ORDER bit in the ACR register.
TABLE IV. Command Summary.
RDATA–Read Data RDATAC–Read Data Continuous

Description: Read the most recent conversion result from the Description: Read Data Continuous mode enables the con-
Data Output Register (DOR). This is a 24-bit value. tinuous output of new data on each DRDY. This command
Operands: None eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOPC
Bytes: 1
command or the RESET command. Wait at least 10 fOSC after
Encoding: 0000 0001
DRDY falls before reading.
Data Transfer Sequence:
Operands: None
Bytes: 1
DIN 0000 0001 • • •(1) xxxx xxxx xxxx xxxx xxxx xxxx
Encoding: 0000 0011
Command terminated when “uuuu uuuu” equals STOPC or
DOUT MSB Mid-Byte LSB
RESET.
DRDY
NOTE: (1) For wait time, refer to timing specification.
DIN 0000 0011 • • •(1) uuuu uuuu uuuu uuuu uuuu uuuu
•••
DRDY •••
NOTE: (1) For wait time, refer to timing specification.
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STOPC–Stop Continuous SELFCAL–Offset and Gain Self Calibration
Description: Ends the continuous data output mode. Issue Description: Starts the process of self calibration. The Offset
after DRDY goes LOW. Calibration Register (OCR) and the Full-Scale Register (FSR)
Operands: None are updated with new values after this operation.
Bytes: 1 Operands: None
Encoding: 0000 1111 Bytes: 1
Data Transfer Sequence: Encoding: 1111 0000
DRDY
DIN 1111 0000

DIN xxx 0000 1111
RREG–Read from Registers SELFOCAL–Offset Self Calibration

Description: Output the data from up to 16 registers starting Description: Starts the process of self-calibration for offset.
with the register address specified as part of the instruction. The Offset Calibration Register (OCR) is updated after this
The number of registers read will be one plus the second byte operation.
count. If the count exceeds the remaining registers, the ad- Operands: None
dresses wrap back to the beginning. Bytes: 1
Operands: r, n Encoding: 1111 0001
Bytes: 2 Data Transfer Sequence:
Encoding: 0001 rrrr xxxx nnnn
DIN 1111 0001
Read Two Registers Starting from Register 01H (MUX)
DIN 0001 0001 0000 0001 • • •(1) xxxx xxxx xxxx xxxx
SELFGCAL–Gain Self Calibration
DOUT MUX ACR

Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values after
NOTE: (1) For wait time, refer to timing specification. this operation.
Operands: None
Bytes: 1
WREG–Write to Registers
Encoding: 1111 0010
Description: Write to the registers starting with the register Data Transfer Sequence:
address specified as part of the instruction. The number of
registers that will be written is one plus the value of the second
byte. DIN 1111 0010
Operands: r, n
Bytes: 2
Encoding: 0101 rrrr xxxx nnnn
Write Two Registers Starting from 04H (DIO)
DIN 0101 0100 xxxx 0001 Data for DIO Data for DIR
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SYSOCAL–System Offset Calibration DSYNC–Sync DRDY
Description: Initiates a system offset calibration. The input Description: Synchronizes the ADS1240 and ADS1241 to an
should be set to 0V, and the ADS1240 and ADS1241 compute external event.
the OCR value that compensates for offset errors. The Offset Operands: None
Calibration Register (OCR) is updated after this operation. The
Bytes: 1
user must apply a zero input signal to the appropriate analog
inputs. The OCR register is automatically updated afterwards. Encoding: 1111 1100
Operands: None
Bytes: 1
DIN 1111 1100
Encoding: 1111 0011
SLEEP–Sleep Mode
DIN 1111 0011
Description: Puts the ADS1240 and ADS1241 into a low
power sleep mode. To exit sleep mode, issue the WAKEUP
SYSGCAL–System Gain Calibration command.
Operands: None
Description: Starts the system gain calibration process. For
a system gain calibration, the input should be set to the Bytes: 1
reference voltage and the ADS1240 and ADS1241 compute Encoding: 1111 1101
the FSR value that will compensate for gain errors. The FSR Data Transfer Sequence:
is updated after this operation. To initiate a system gain 1111 1101
DIN
calibration, the user must apply a full-scale input signal to the
appropriate analog inputs. FCR register is updated automati-
cally.
RESET–Reset to Default Values
Operands: None
Bytes: 1 Description: Restore the registers to their power-up values.
This command stops the Read Continuous mode.
Encoding: 1111 0100
Data Transfer Sequence: Operands: None
Bytes: 1
Encoding: 1111 1110
DIN 1111 0100
DIN 1111 1110

WAKEUP
Description: Wakes the ADS1240 and ADS1241 from SLEEP
mode.
Operands: None
Bytes: 1
Encoding: 1111 1011
DIN 1111 1011
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APPLICATION EXAMPLES output can be directly applied to the differential inputs of
ADS1240.
GENERAL-PURPOSE WEIGH SCALE
Figure 8 shows a typical schematic of a general-purpose HIGH PRECISION WEIGH SCALE
weigh scale application using the ADS1240. In this example, Figure 9 shows the typical schematic of a high-precision
the internal PGA is set to either 64 or 128 (depending on the weigh scale application using the ADS1240. The front-end
maximum output voltage of the load cell) so that the load cell differential amplifier helps maximize the dynamic range.
2.7V ~ 5.25V 2.7V ~ 5.25V

EMI Filter
AVDD DVDD VDD

VREF+
EMI Filter
AIN0
Load Cell DRDY
SCLK
DOUT MSP430x4xx
ADS1240 SPI
or other µP
DOUT
CS
EMI Filter
AIN1
XIN MCLK
VREF– XOUT
AGND DGND GND
EMI Filter
FIGURE 8. Schematic of a General-Purpose Weigh Scale.
2.7V ~ 5.25V 2.7V ~ 5.25V

EMI Filter
AVDD DVDD VDD

VREF+
EMI Filter
RI
OPA2335 AIN0
Load Cell
RF DRDY
SCLK
CI ADS1240 DOUT MSP430x4xx

RG SPI
ADS1241 or other µP
DIN
RF
CS
RI
EMI Filter OPA2335 AIN1
XIN MCLK
XOUT
VREF–
AGND DGND GND
EMI Filter
G = 1 + 2 • RF/RG
FIGURE 9. Block Diagram for a High-Precision Weigh Scale.
ADS1240, 1241 21
SBAS173F www.ti.com
fOSC fOSC
fMOD = =
mfactor 128 • 2 SPEED
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi- fSAMP—the frequency, or switching speed, of the input sam-
nology used in this data sheet. In that regard, the definition PGA SETTING SAMPLING FREQUENCY
of each term is given as follows: 1, 2, 4, 8 f SAMP =
fOSC
mfactor
Analog Input Voltage—the voltage at any one analog input
fOSC • 2
relative to AGND. 16 f SAMP =
mfactor
Analog Input Differential Voltage—given by the following fOSC • 4
32 f SAMP =
equation: (IN+) – (IN–). Thus, a positive digital output is mfactor
produced whenever the analog input differential voltage is fOSC • 8
64, 128 f SAMP =
positive, while a negative digital output is produced whenever mfactor
the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive pling capacitor. The value is given by one of the following
full-scale output is produced when the analog input differen- equations:
tial is 2.5V. The negative full-scale output is produced when
fDATA—the frequency of the digital output data produced by
the differential is –2.5V. In each case, the actual input
the ADS1240 and ADS1241, fDATA is also referred to as the
voltages must remain within the AGND to AVDD range.
Data Rate.
Conversion Cycle—the term conversion cycle usually refers
Full-Scale Range (FSR)—as with most A/D converters, the
to a discrete A/D conversion operation, such as that per-
full-scale range of the ADS1240 and ADS1241 is defined as
formed by a successive approximation converter. As used
the input, that produces the positive full-scale digital output
here, a conversion cycle refers to the tDATA time period.
minus the input, that produces the negative full-scale digital
Data Rate—The rate at which conversions are completed. output.
See definition for fDATA.
For example, when the converter is configured with a 2.5V
fOSC reference and is placed in a gain setting of 2, the full-scale
fDATA =
128 • 2 SPEED • 1280 • 2DR range is: [1.25V (positive full-scale) minus –1.25V (negative
full-scale)] = 2.5V.
SPEED = 0, 1
DR = 0, 1, 2 Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
fOSC—the frequency of the crystal oscillator or CMOS com- input has to change in order to observe a change in the
patible input signal at the XIN input of the ADS1240 and output data of one least significant bit. It is computed as
ADS1241. follows:
fMOD—the frequency or speed at which the modulator of the
Full− Scale Range
ADS1240 and ADS1241 is running. This depends on the LSB Weight =
2N – 1
SPEED bit as given by the following equation:
where N is the number of bits in the digital output.
tDATA—the inverse of fDATA, or the period between each data
SPEED = 0 SPEED = 1 output.
mfactor 128 256
5V SUPPLY ANALOG INPUT(1) GENERAL EQUATIONS

DIFFERENTIAL PGA OFFSET FULL-SCALE DIFFERENTIAL PGA SHIFT
GAIN SETTING FULL-SCALE RANGE INPUT VOLTAGES(2) RANGE RANGE INPUT VOLTAGES(2) RANGE
1 5V ±2.5V ±1.25V 2 • VREF ±VREF ± VREF
2 2.5V ±1.25V ±0.625V PGA PGA 2 • PGA
4 1.25V ±0.625V ±312.5mV
8 0.625V ±312.5mV ±156.25mV RANGE = 0
16 312.5mV ±156.25mV ±78.125mV VREF ± VREF ± VREF
32 156.25mV ±78.125mV ±39.0625mV PGA 2 • PGA 4 • PGA
64 78.125mV ±39.0625mV ±19.531mV
128 39.0625mV ±19.531mV ±9.766mV RANGE = 1
NOTES: (1) With a 2.5V reference. (2) Refer to electrical specification for analog input voltage range.
TABLE VI. Full-Scale Range versus PGA Setting.
22
ADS1240, 1241
www.ti.com SBAS173F
Revision History
DATE REVISION PAGE SECTION DESCRIPTION

10/13 F 21 Application Examples Changed Figure 9; switched plus and minus in upper op amp.
8/06 E 6 Timing Characteristics Table Clarified t10 specification.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
ADS1240, 1241 23
SBAS173F www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
ADS1240E ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1240E Samples
ADS1240E/1K ACTIVE SSOP DB 24 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1240E Samples
ADS1240EG4 ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1240E Samples
ADS1241E ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1241E Samples
ADS1241E/1K ACTIVE SSOP DB 28 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1241E Samples
ADS1241E/1KG4 ACTIVE SSOP DB 28 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1241E Samples
ADS1241EG4 ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1241E Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1240E/1K SSOP DB 24 1000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
ADS1241E/1K SSOP DB 28 1000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1240E/1K SSOP DB 24 1000 356.0 356.0 35.0
ADS1241E/1K SSOP DB 28 1000 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ADS1240E DB SSOP 24 60 530 10.5 4000 4.1
ADS1240EG4 DB SSOP 24 60 530 10.5 4000 4.1
ADS1241E DB SSOP 28 50 530 10.5 4000 4.1
ADS1241EG4 DB SSOP 28 50 530 10.5 4000 4.1
PACKAGE OUTLINE
DB0028A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
8.45
9.9
NOTE 3
14
15
0.38
28X
0.22
5.6 0.15 C A B
B
5.0
NOTE 4
2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE
0.95 0.05 MIN

0 -8 0.55
DETAIL A
A 15
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A SSOP - 2 mm max height
28X (1.85) SYMM
1 (R0.05) TYP
28X (0.45) 28
26X (0.65)
SYMM
14 15
(7)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A SSOP - 2 mm max height
28X (1.85) SYMM

(R0.05) TYP
1
28X (0.45) 28
26X (0.65)
SYMM
14 15
(7)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN
0,38
0,65 0,15 M
0,22
28 15
0,25
0,09
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°–ā8° 0,95
0,55
Seating Plane
2,00 MAX 0,05 MIN 0,10
PINS **
14 16 20 24 28 30 38
DIM
A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90
A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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ADS

● LIQUID /GAS CHROMATOGRAPHY

BUFEN DVDD DGND PDWN DSYNC RESET DRDY

DIGITAL CHARACTERISTICS: –40°C to +85°C, DVDD 2.7V to 5.25V

PARAMETER CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT (AIN0 – AIN7, AINCOM)

Offset Monotonicity 8 Bits

PARAMETER CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT (AIN0 – AIN7, AINCOM)

Offset DAC Monotonicity 8 Bits

DVDD 1 24 BUFEN DGND 2 27 DRDY

DGND 2 23 DRDY XIN 3 26 SCLK

XIN 3 22 SCLK XOUT 4 25 DOUT

XOUT 4 21 DOUT RESET 5 24 DIN

RESET 5 20 DIN DSYNC 6 23 CS

DSYNC 6 19 CS PDWN 7 22 POL

DGND 8 17 AVDD VREF+ 9 20 AGND

VREF+ 9 16 AGND VREF– 10 19 AINCOM

VREF– 10 15 AINCOM AIN0/D0 11 18 AIN3/D3

AIN0/D0 11 14 AIN3/D3 AIN1/D1 12 17 AIN2/D2

AIN1/D1 12 13 AIN2/D2 AIN4/D4 13 16 AIN7/D7

PIN DESCRIPTIONS (ADS1240) PIN DESCRIPTIONS (ADS1241)

1 DVDD Digital Power Supply 1 DVDD Digital Power Supply

NOTE: (1) Bit order = 0.

SCLK Reset Waveform ADS1240 or ADS1241

DRDY RESET, DSYNC, PDWN

TIMING CHARACTERISTICS TABLE

t1 SCLK Period 4 tOSC Periods

NOTES: (1) Load = 20pF 10kΩ to DGND.

PGA Setting PGA Setting

EFFECTIVE NUMBER OF BITS vs PGA SETTING NOISE vs INPUT SIGNAL

COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO

OFFSET vs TEMPERATURE GAIN vs TEMPERATURE

INTEGRAL NONLINEARITY vs INPUT SIGNAL ANALOG CURRENT vs TEMPERATURE

ANALOG CURRENT vs PGA DIGITAL CURRENT vs SUPPLY

Offset (ppm of FSR)

AIN3/D3 BURNOUT CURRENT SOURCES

New Conversion Begins, Previous Conversion Data

DIN MSB LSB

SETTLING ERROR vs DELAY TIME

FIGURE 2. Input Multiplexer Configuration.

SPEED DR BITS 1st NOTCH

System calibration corrects both internal and external offset XOUT

appropriate signal must be applied to the inputs. The system

ADS1240 AND ADS1241 FREQUENCY RESPONSE FROM 45Hz to 65Hz

ADS1240 AND ADS1241 FREQUENCY RESPONSE FROM 45Hz to 65Hz

fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1

FIGURE 6. Filter Frequency Responses.

00H SETUP ID ID ID ID BOCS PGA2 PGA1 PGA0

TABLE III. Registers.

DETAILED REGISTER DEFINITIONS MUX (Address 01H) Multiplexer Control Register

bit 7 DRDY: Data Ready (Read Only)

bit 5 SPEED: Modulator Clock Speed

OCR0 (Address 07H) Offset Calibration Coefficient

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00

COMMANDS DESCRIPTION OP CODE 2nd COMMAND BYTE

TABLE IV. Command Summary.

RDATA–Read Data RDATAC–Read Data Continuous